Save trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com BCS Serials ] ine ] 156.663 Sixth Semester B.E. Degree Examination, Dec.2018/Jan.2019 Digital System Design using Verilog ‘Time: 3 hs Max, Macks: 80 Note: Answer any FIVE full questions choosing ¥ ‘ONE full question from exch module. ° i Module-t Z1a ih ilustraton, a simple design methodology followed god Maks a 8 following conseaimts imposed in real word circuits 3 HASberaUR Mitral ay ostsi 2, Develop a verilog model for 8 7-segmecetdscoder. inclug ut blank. hat # ‘overrides the BCD ip and causes all segments not 9 be Ii Marks) OR 2 a. Develop a verilog module of « debouncer for teh that uses 4 dcbownece imersal oF 1ns. Assume the system clock fi (06 Marks) Design and develop a citcut apd verilog FA counters (06 Maths) ‘© Wht is the distinction between 2 Moore: fe slate machine? {04 Mar) 8. Wee a symbol for basie memory explain its parts (We Marks) ‘Explain abou the multipor: meme 106 Marks) © Compute the 12-bit ECC Ro the 8-it data word “OLL000I". (bs Marks) oR 4 Design #64 K = 1alcom rmory using 14K » Sit component (0 Marks) bb What is the difgentSgueen asynchronous static RAM and synehronous static RAM? (06 Marks Using many check bits are required for single error comrection and souble nt data wor? (02 Marks Modute-3 sa rcoder that has 16 inputs, JO» 1S|:a d-bi encoded output. 3:0] and a ‘when any input "1 Inpat 0] bas the highest priority and 15) i the (os Marks) b ‘concept of differential signating. How does dileremial signaling impeove noise ‘immunity? (8 Marks) oR at ace the purpose of logie Macks and U0 blacks in FPGA? (06 Marks) Explain different iypes of PCB design (aa tars Explain with «neat diggram of the imma organization ofa CPLD, (07 stark Vo? BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Viuresource Go Green initiativeSave trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com 15EC663, Modute-4 1 1. What ore the purpose of fllowing in an (0 controller: i) input register i) outp ii control register i) status register. Explain neay the designing s Resting DAC © Explain about triste buses ad weak drive on a Design and develop a verilng code for an input controler that has 8-bi input fiom a sensor. Tho valuo ean be read trom an 8-bit input reas shold snded Gurmut, When input value changes, “he only ‘What ate the serial input standards? Briefly explain eae, (os marks) Modules 9 a Fplain the design flow of hardware sofware eo-sign 0 Marks riely describe techniques used in power optim (06 Mark oO 10 a. What isthe distinetion betwen logical pa eal partition? 8 Marks) 1b Explain Bul-In-Self=Test BIST) techni (08 Marky BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Viuresource Go Green initiative