8086/8087/8088 MACRO ASSEMBLER POCKET REFERENCE 121674-001 Rev. A © Intel Corporation 19308086 REGISTER MODEL ACCUMULATOR BASE COUNT 3 2 DATA Ea | Ga ge STACK POINTER ae BASE POINTER w SOURCE INDEX DESTINATION INDEX INSTRUCTION POINTER STATUS FLAGS 4 3 CODE SEGMENT bE Zz DATA SEGMENT ag STACK SEGMENT 9 b EXTRA SEGMENT ao ~~ c instructions which reference the fiag register file as a 16-bit object use the symbol FLAGS to represent the file: 15 7 o [> ]x [x [lor or [re ]se]er [x]ar ] x]er [xfer] X = Don't Care AF: AUXILIARY CARRY — BCD CF: CARRY FLAG PF: PARITY FLAG [~ 8080 FLAGS SF: SIGN FLAG ZF: ZERO FLAG 4 DF: DIRECTION FLAG (STRINGS: | IF. INTERRUPT ENABLE FLAG OF: OVERFLOW FLAG (CF @ SF) [~ 8086 FLAGS TF: TRAP — SINGLE STEP FLAG Mnemonics ©latel, 1980 1OPERAND SUMMARY “reg” field Bit Assignments: 8-Bit (w = 0) Displacement 00 | DISP = 0°, disp-low and disp-high are absent 01 | DISP = disp-tow sign-extended to 16-bits, disp-high is absent 10 | DISP = disp-high: disp-low 11 | r/m is treated as a “reg” field Operand Address 000 | (BX) + (Sl) + DISP 001 | (BX) + (Dh) + DISP 010 | (BP) + iSl) + DISP 011} (BP) + |Dli + DISP 100 | 1Sli + DISP 101) (Dili + DISP 110 | (BP) + DISP* 111 | (BX: + DISP DISP follows 2nd byte of instruction (before data if required: ‘except if mod = 00 and r/m = 110 then EA = disp-high: disp-low. Operand Address (EA) Timing (clocks): Add 4 clocks for word operands at ODD ADDRESSES. Immed Offset = 6 Base (BX, BP, SI, DI1= 5 Base + DISP =9 Base + Index |BP + DI, BX + Sh =7 Base + index (BP + SI, BX + Dl) Base + Index (BP + Di, BX + SI; + DISP Base + Index (BP + SI, BX + Dl) + DISP Mnemonics ©tntel, 1980MEMORY SEGMENTATION MODEL 7 o Logicac FFF MEMORY SPACE eax CODE SEGMENT XXXXOH STACK SEGMENT [DISPLACEMENT ® of OrFser Corsets [Disecacement] | ATA SEGMENT | a & ro EE J SELECTED ‘SEGMENT REGISTER 5,58. 08. es Of NONE FOR 1/0, INT Extaa DATA SEGMENT TL —Toooo0n PHysicaL ADDRESS, LarcH SEGMENT OVERRIDE PREFIX 00 reg 110 Timing: 2 clocks USE OF SEGMENT OVERRIDE Operand Register TDetautt| With Override Pretix IP icode address! CS |Never SP (stack address! SS _ [Never BP (stack address or stack marker) SS |BP+ OSorES,orCS SI or DI not incl, strings: DS ES, $8, or CS SI ‘implicit source addr for strings) ] DS. ES. SS, or CS DI (implicit dest addr for strings) ES [Never Mnemonics © intel, 1980* 8086/8088 DATA TRANSFER INSTRUCTIONS MOV = Move Register/memory to/from register 100010dw| mod reg rim Timing (clocks): register to regi ister memory to register register to memory Immediate to register/memory 2 8+EA 9+EA 1100011w|mod 000 rm data data ifw=1 Timing (clocks): 10+ EA Immediate to register 1011w reg data data if w=1 Timing (clocks): 4 Memory to accumulator 1010000w addr-lo addr-hi Timing (clocks): 10 Accumulator to memory 1010001w addr-lo addr-hi Timing (clocks): 10 Register/memory to segment register [10007411 0|modOreg rim Timing (clocks): register to reg ister memory to register Segment register to register/memory 10001100jmod0reg rim PUSH = Push Register/memory Timing (clocks): register to register register to memory 11111111}mod110 rim Timing (clocks): register memory Register 01010 reg Timing (clocks): 11 (continued on following page) 2 8+EA 2 9+EA 1 16+EA 4 Moeenonics Intel, 1980Segment register 0001reg 110 Timing (clocks): 11 POP = Pop Register/memory 10001111}mod000 rim Timing (clocks): register 8 memory I7+EA Register 01011 reg Timing (clocks): 8 Segment register 000reg111 Timing (clocks): 8 XCHG = Exchange Register/memory with register 1000011 w| mod reg rim Timing (clocks): register with register 4 memory with register 17+EA Register with accumulator 10010 reg Timing (clocks): 3 IN = Input to AL/AX from Fixed port 1110010w port Timing (ciocks): 10 Variable port (DX) 1110110Ww Timing (clocks): 8 OUT = Output from AL/AX to Fixed port 1110011W port Timing (clocks): 10 (continued on following page) Mnomonies © intel, 1980Variable port (DX) 1110111W Timing (clocks): 8 XLAT = Translate byte to AL 11010111 Timing (clocks): 11 LEA =Load EA to register 10001101| mod reg rim Timing (clocks): 2+EA LDS = Load pointer to DS 11000101{| mod reg rim Timing (clocks): 16+EA LES =Load pointer to ES 11000100] mod reg rim Timing (clocks): 16+ EA LAHF =Load AH with flags 10011111 Timing (clocks): 4 SAHF = Store AH into flags 10011110 Timing (clocks): 4 PUSHF = Push flags 10011100 Timing (clocks): 10 POPF = Pop flags 10011101 Timing (clocks): 8 6 Mnemonics intel, 1980¢ ARITHMETIC INSTRUCTIONS ADD =Add Register/memory with register to either 000000dw/| mod reg rim Timing (clocks): register to register 3 memory to register 9+EA register to memory 16+EA Immediate to register/memory 100000sw|mod000 rim | data data if sw=01 Timing (clocks): immediate to register 4 immediate to memory 17+EA Immediate to accumulator 0000010w data data if w=1 Timing (clocks): 4 ADC = Add with carry Register/memory with register to either 000100dw| mod reg rim Timing (clocks): register to register 3 memory to register 9+EA register to memory 16+EA Immediate to register/memory 100000sw|mod010 rim data data if s:w=01 Timing (clocks): immediate to register 4 immediate tomemory 17+EA immediate to accumulator 0001010w data data if w=1 Timing (clocks): 4 INC = Increment Register/memory 1111111wjmod000 rim Timing (clocks): word register 2 memory 15+EA byte register 3 Register 01000 reg Timing (clocks): 2 Mnemonics intel, 1980AAA=ASCII adjust for aau 001101114 Timing (clocks): 4 DAA = Decimal adjust for add 00100111 Timing (clocks): 4 SUB = Subtract Register/memory and register to either [001010dw| mod reg rm Timing (clocks): register from register 8 memory from register 9+EA register from memory 16+EA Immediate from register/memory 100000sw|mod101 Fm data [data if sw=01 Timing (clocks): immediate from register 4 immed. from memory 17+EA Immediate from accumulator 0010110w data data if w=1 Timing (clocks): 4 SBB = Subtract with borrow Register/memory and register to either 000110dw| mod reg rim Timing (clocks): register from register 3 memory from register 9+EA register frommemory 16+EA Immediate from register/memory 100000swimod011 rm data data if sw =01| Timing (clocks): immediate from register 4 immed. frommemory 17+EA Immediate from accumulator 0001110W data data if w=1 | Timing (clocks): 4 8 Mnemonics @Intet, 1980DEC = Decrement Register/memory 1111111w]mod001 rm Timing (clocks): word register 2 memory 15+EA byte register 3 Register 01001 reg Timing (clocks): 2 NEG =Change sign 1111011w|mod011 rm Timing (clocks): register 3 memory 16+EA CMP =Compare Register/memory and register 001110dw} mod reg rim Timing (clocks): register with register 3 memory with register 9+EA register with memory 9+EA Immediate with register/memory 100000swjimod111 rm data data if s:w=01 Timing (clocks): immediate with register 4 immed. with memory 10+EA Immediate with accumulator 0011110wW data data if w=1 Timing (clocks): 4 AAS =ASCII adjust for subtract 00111111 Timing (clocks): 4 DAS = Decimal adjust for subtract 00101111 Timing (clocks): 4 Mnemonics Intel, 1980 9MUL = Multiply (unsigned) 1111011wjmod100 rm Timing (clocks): 8-bit register 70-77 16-bit register 118-133 8-bit memory 76-83 + EA 16-bit memory 124-139 + EA IMUL = Integer multiply (signed) 11110141w|mod101 dm Timing (clocks): 8-bit register 80-98 16-bit register 128-154 8-bit memory 86-104+EA 16-bit memory 134-160 + EA AAM= ASCII adjust for multiply [1 1010100[00001010 Timing (clocks): 83 DIV = Divide (unsigned) 1111011w|mod110 f/m Timing (clocks): 8-bit register 80-90 16-bit register 144-162 8-bit memory 86-96 +EA 16-bit memory 150-168 + EA IDIV = Integer divide (signed) 1111011w][mod111 rim] Timing (clocks): 8-bit register 101-112 16-bit register 165-184 8-bit memory 107-118+EA 16-bit memory 171-190 + EA AAD =ASCIl adjust for divide [11010101 00001010 Timing (clocks): 60 CBW = Convert byte to word 10011000 Timing (clocks): 2 10 Mnemonics ® intel, 1980CWD = Convert word to double word 10011001 Timing (clocks): 5 * LOGIC INSTRUCTIONS NOT = Invert 1111011w} mod 010rm Timing (clocks): register 3 memory 16+ EA SHL/SAL = Shift logical/arithmetic left 110100 vw[mod 100 rim] Timing (clocks): single-bit register 2 single-bit memory 15+EA variable-bit register 8+ 4/bit variabie-bit memory 20+EA +4/bit SHR = Shift logical right 110100vw|mod101 rim Timing (clocks): single-bit register 2 single-bit memory 15+EA variabte-bit register 8+ 4/bit variable-bit memory 20+EA + 4/bit SAR = Shift arithmetic right [i101 00vw[mod411 rm Timing (clocks): single-bit register 2 single-bit memory 15+EA variable-bit register 8+ 4/bit variable-bit memory 20+EA + A/bit Mnemonics ©Intel, 1980ROL = Rotate left 110100vw}mod000 rim Timing (clocks): single-bit register 2 single-bitmemory ~ 15+EA variable-bit register 8+ 4/bit variable-bit memory 20+EA + 4/bit ROR = Rotate right 110100vw|mod001 rim Timing (clocks): single-bit register 2 single-bit memory 154+ EA variable-bit register 0+ 4/bit variable-bit memory 20+EA + 4/bit RCL = Rotate through carry left [14.0700vw[mod010 rim Timing (clocks): single-bit register 2 single-bit memory 15+EA variable-bit register 84 4/bit variable-bit memory 20+EA +4lbit RCR = Rotate through carry right 110100vw|mod011 rm Timing (clocks): single-bit register 2 single-bit memory 15+EA variable-bit register 8+ 4/bit variable-bit memory 20+EA +4lbit AND =And Register/memory and register to either 001000dw| mod reg rim Timing (clocks): register to register 3 memory to register 9+EA register to memory 16+EA Immediate to register/memory 1000000 w|mod100 tim data___| dataifw=1 Timing (clocks): immediate to register 4 immediate tomemory 17+EA (continued on following page) 42 Mnemonics intel, 1980Immediate to accumulator 0010010w data data if w=1 | Timing (clocks): 4 TEST = And function to flags, no result Register/memory and register 1000010w| mod reg rim Timing (clocks): register to register 3 register with memory 9+EA Immediate data and register/memory 1111011wjmod000 rm data data if w=1 Timing (clocks): immediate with register 5 immediate with memory 11 + EA Immediate data and accumulator 1010100w data data ifw=1 Timing (clocks): 4 OR=Or Register/memory and register to either 000010dw{| mod reg rim Timing (clocks): register to register 3 memory to register 9+EA register to memory 16+EA Immediate to register/memory 1000000wj|mod001 rim data data if w=1 | Timing (clocks): immediate to register 4 immediate tomemory 17+EA Immediate to accumulator 0000110wW data data if w=1 Timing (clocks): 4 XOR = Exclusive or Register/memory and register to either 001100dwi| mod reg rim Timing (clocks): register to register 3 memory to register 9+EA register to memory 16+EA (continued on following page} Mnemonics @intel, 1980 13immediate to register/memory 1000000wj|mod110 rim data data if w=1 Immediate to accumulator Timing (clocks): immediate to register 4 immediate tomemory 17+EA 0011010W data data if w=1 Timing (clocks): 4 * STRING MANIPULATION INSTRUCTIONS REP = Repeat 1111001z Timing: 2 clocks/ioop MOVS = Move string 1010010w Timing: once only with repeat prefix CMPS = Compare string 1010011w Timing: once only with repeat prefix SCAS = Scan string 1010111W Timing: once only with repeat prefix LODS = Load string 1010110w Timing: once only with repeat prefix 18 clocks 9+17 Jrep clocks 22 clocks 9+22 /rep clocks 15 clocks 9415 Jrep clocks 12 clocks 9413 frep clocks 14 ‘Mnemonics ©Intel, 1980STOS = Store string 1010101w Timing: once only 11 clocks with repeat prefix 9+10 frep clocks * CONTROL TRANSFER INSTRUCTIONS NOTE: Queue reinitialization is not included in the timing information for transfer operations. To account for instruction loading, add 8 clocks to timing numbers. CALL = Call Direct within segment 11101000 disp-lo disp-hi Timing (clocks): 19 Indirect within segment 11111111};mod010 rim Timing (clocks): through register 16 through variable 21+EA Direct intersegment 10011010] offset-lo offset-hi seg-lo seg-hi Timing (clocks): 8 Indirect intersegment 11111111}mod011 rm Timing (clocks): 37+ EA JMP = Unconditional jump Direct within segment 11101001 disp-lo disp-hi Timing (clocks): 15 Direct within segment-short [11107011 disp Timing (clocks): 15 Mnemonics © intel, 1980 6Indirect within segment 11111111]mod100 rim indirect intersegment 11111111;mod101 tm Within segment 11000011 Timing (clocks): RET = Return from call 8 Timing (clocks): 24+EA clocks Within segment adding immediate to SP 11000010 data-lo data-hi Timing (clocks): Intersegment 11001011 Timing (clocks): 12 18 Intersegment, adding immediate to SP 11001010 data-lo data-hi Timing (clocks): 7 JE/JZ = Jump on equal/zero 01110100 disp Timing (clocks): jump is taken jump is not taken JL/JNGE = Jump on less/not 01111100 disp Timing (clocks): jump is taken jump is not taken Mnemonics © Intel, 1980 Timing (clocks): memory 18+EA register ant Direct intersegment 11101010! offset-lo offset-hi seg-lo seg-hi Timing (clocks): 15 greater or equal 16 4JLE/JNG=Jump on less or equal/not greater 01111110 disp Timing (clocks): jump is taken jump is not taken 01110010 disp Timing (clocks): jump is taken jump is not taken 01110110 disp Timing (clocks): : jump is taken jump is not taken JP/JPE= Jump on parity/parity even 01111010 disp Timing (clocks): : jump is taken jump is not taken JO=Jump on overflow 01110000 disp | Timing (clocks): jump is taken jump is not taken JS = Jump on sign 01111000 disp Timing (clocks): jump is taken jump is not taken JNE/JNZ=Jump on not equal/not zero 01110101 disp Timing (clocks): jump is taken jump is not taken 01111101 disp Timing (clocks): jump is taken jump is not taken Mnemonics ® Intel, 1980 16 4 JB/IJNAE = Jump on below/not above or equal 16 4 JBE/JNA = Jump on below or equal/not above . JNL/JGE = Jump on not less/greater or equal 16 4JNLE/JG = Jump on not less or equal/greater 01141111 disp Timing (clocks): jump is taken 16 jump is not taken 4 JNB/JAE = Jump on not below/above or equal 01110011 disp Timing (clocks): jump is taken 16 jump is not taken 4 JNBE/JA= Jump on not below or equal/above 01110111 disp Timing (clocks): jump is taken 16 jump is not taken 4 JNP/JPO = Jump on not parity/parity odd 01111011 disp Timing (clocks): jump is taken 16 jump is not taken 4 JNO = Jump on not overflow 01110001 disp Timing (clocks): jump is taken 16 jump is not taken 4 JNS = Jump on not sign 01111001 disp Timing (clocks): jump is taken 16 jump is not taken 4 LOOP = Loop CX times 71100010 disp Timing (clocks): jump is taken 7 jump is not taken 5 LOOPZ/LOOPE = Loop while zero/equal 11100001 disp Timing (clocks): jump is taken 18 jump is not taken 6 18 Mnemonics Sintel, 1980LOOPNZ/LOOPNE = Loop while not zero/not equal 11100000 disp Timing (clocks): jump is taken 19 jump is not taken 5 JCXZ = Jump on CX zero 11100011 disp Timing (clocks): jump is taken 18 jump is not taken 6 8086 CONDITIONAL TRANSFER OPERATIONS Instruction Condition Interpretation JEorJZ 9 ZF=1 “equal” or “zero” JLorJNGE (SF xor OF)=1 “Jess” or “not greater or equal” JLE or ING (SP xor OF) or ZF) “less or equal” or “not greater” JBorJNAE CF=1 “below” or “not above or equal” JBE or INA (CF or ZF}=1 “below or equal” or “not above” JPorJPE PF = “parity” or “parity even” JO OF=1 “overtiow" Js SF=1 “sign” JNE or JNZ ZF=0 “not equal” or “not zero” JNL or JGE {SF xor OF)=0 “not less” or "greater or equal” JNLE of JG (SF xor OF) or ZF)=0 “not less or equal” or “greater” JNBor JAE CF=0 “not below” or “above or equal” JNBE or JA (CF or ZF)=0 “not below or equal” or “above” JNP orJPO PF=0 “not parity” or “parity odd” JNO. “not overflow" JNS “not sign” “Above” and “below” refer to the relation between two unsigned values, while “greater” and “less” refer to the relation between two signed values. INT = Interrupt Type specified (not type 3) 11001101 type Timing (clocks): 51 Type 3 11001100 Timing (clocks): 52 INTO = Interrupt on overflow 11001110 Timing (clocks): if pass if fail Mnemonics @Intel, 1980 19IRET = Interrupt return 11001111 Timing (clocks): 24 * PROCESSOR CONTROL INSTRUCTIONS CLC =Clear carry STC =Set carry 11111000 11111004 Timing (clocks): 2 Timing (clocks): 2 : CMC =Complement carry © NOP=No operation 11110101 10010000 Timing (clocks): 2 Timing (clocks): 3 CLD = Clear direction STD =Set direction 11111100 11111101 Timing (clocks): 2 Timing (clocks): 2 CLI = Clear interrupt STI = Set interrupt 11111010 11111011 Timing (clocks): 2 Timing (clocks): 2 HLT= Halt WAIT = Wait 11110100 10011011 Timing (clocks): 2 _ .-..- Timing (clocks): 3+ 5n where n is # of times TEST line polled and found inactive ESC = Escape LOCK = Bus lock prefix (to external device) 11110000 11011xxx|modxxx r/m Timing (clocks): 2 Timing (clocks): register 2 memory 8+EA 20 Mnemonics ©tntel, 1980Footnotes: If d=1 then “to”; if d=0 then “from”. If w= 1 then word instruction; if w= 0 then byte instruction. If s: 1 then 16 bits of immediate data form the operand. ifs: 41 then an immediate data byte is sign extended to form the 16-bit operand. If v=0 then “count” = 1; if v=1 then “count” in (CL). x=don't care. zis used for some string primitives to compare with ZF FLAG. AL= 68-bit accumulator. AX = 16-bit accumulator. CX =Count register. DS = Data segment. DX = Variable port register. ES = Extra segment. Above/below refers to unsigned value. Greater = more positive. Less = less positive (more negative) signed values. See page 1 for Operand Summary. See page 2 for Segment Override Summary. ‘Mnemonics © intel, 1980 21* ASSEMBLER DIRECTIVES Symbol Definition: EQU LABEL PURGE Memory Reservation and Data Definition: DB DW DD dQ DOT RECORD Location Counter and Segmentation Control: SEGMENT/ENDS ORG GROUP ASSUME PROC/ENDP CODEMACRO/ENDM Program Linkage: NAME PUBLIC EXTRN END + PROCESSOR RESET REGISTER INITIALIZATION = (to disable interrupts Flags = ooo] and single-stepping) CS = FFFFH IP = 0000H (to begin execution at FFFFOH) ES = 0000H No other registers are acted upon during reset. Mnemonics Intel, 1980MCS-86™ RESERVED LOCATIONS Reserved Memory Locations Intel Corporation reserves the use of memory locations FFFFOH through FFFFFH (with the exception of FFFFOH - FFFF5H for JMP instr.) for Intel hardware and software products. If you use these locations for some other purpose, you may preclude compatibility of your system with certain of these products. Reserved Input/Output Locations Intel Corporation reserves the use of input/output locations F8H through FFH for Intel hardware and software products. Users who wish to maintain compatibility with present and future intel products should not use these locations Reserved Interrupt Locations Intel Corporation teserves the use of interrupts 0-31-i locations OOH through 7FH) for Intel hardware and software products. Users who wish to maintain compatibility with present and future Intel products should not use these locations. Interrupts 0 through 4 (00H-13H) currently have dedicated hardware functions as defined below. Interrupt Location Function 0 00H-03H_ Divide by zero 1 04H-07H Single step 2 08H-OBH Non-maskable interrupt 3 OCH-OFH One-byte interrupt instruction 4 10H-13H Interrupt on overflow INTERRUPT POINTER TABLE . INTERRUPT TYPE VECTOR cs; 418 LOCATION FOR TYPE, ADDRESS OF INTERRUPT8086 INSTRUCTION to Hi o 1 2 3 4 5 8 7 oy aco 7 aod 7 Aop | aod” | apd | AoD ] PusH | Por bicim | wietm | ptsim| wtrim | bia | wia | eS | eS 17 aoc f adc | adc | aoe [aoc | aoc | Pusn | Pop bicim | wtcrm| btrim| witrim | ba | ws | $8 | ss zy ano | (aNO |" ANO | and {ano {AND | SEC pag brim fow.tirim | btirdm | witcim bi we es a] xon] xan 7 xn | XR | xR (KOR | SEG | aq btrim fwirim| btm] warm | br | wi | oss 4) wc [inc [wwe T inc” } inc [inc] wwe] Ine Ax | cx | ox | ax | sp | pp si aL 5) push | pusH | pusH | push | Push | PusH | PUSH | PUSH Ax | cx | ox | Bx | se | ge si ol 6 7 sei] JNB/ | Jey | UNE” | JBE” | NDE? Je | NOT ivae | ae | le | Une] na | OM 8 | tmimed [iramed | immed | immed | Test | tes? | xcHo | xcHG Daim f wart | -brim | isrém | brim | wim | brim | wre 9] Nop | xcHG [xcHG | xcs | xcHG | xcHe | xcHo | xcHG [ cx ox Bx SP BP Si OF Ay Mov | mov | mov | mov | Movs | Movs | cMes | CMPS m —Al{m —AX|AL = m AX -m| db w bo w 8] Mov | mov | mov | mov | mov [ mov | mov | Mov pAb i= Cl} i OL] i Bt fee aH | i= CH a — OW} 1 BH c RET. Mov | Mov ish | RET | LES | LOS | rim | wa erm Of -ShiftS | Shit] Shit] Shit Df wt | SRP Sh nam | aan XUAT € [Loopnz/| toopz) in] NT our | our voopne | ioore | ‘OOP | Joxz | fy | ow D w F ep Gio? | &pt Lock nee | AEP ur | cmc |] Sit 7 See b= byte operation m= memory d = direct r/m ~ EA is second byte 1 = from CPU reg hort intrasegment (= immediate egment register ia = immed. to accum, t= to CPU reg id = indirect v= variable is = immed. byte. sign ext. Ww» word operation 4 long ie. intersegment 2 = zero 24SET MATRIX Hi Lo 8 g A B c 0 E F on | om | on | on | oA [OR [ PusH ptrim | wfrim | btrim | winimy 1 | wa | cS BB) see | S88 | S6B | SBB | Sas | pusH | FOP bi wisém bam witnim bo wa os os sus} sua | sue | Sus | sus { suB | SEG | pas bicim | wirm | phim Dr | ow | CS s cup | CMP | OMe cmp | cme [SEG | agg oicim | wiim | btrim | wt ba Wi \- DS vec | bec | Dec | DEC | vec | DEC | DEC | DEC ax | cx | ox | Be ft sp | are | St ol poe | pop | por | pop | pop | pop | pop | PoP AX Cx Ox Bx | SP _ Be __ St ol _] N wer) NP) | uty f uNUr TLE? | INLET JS | ONS | Spe | spo | NGe | “vee | UNG |G mov | mov | mov | Mov | MOV | gq | mov | PoP ofm | wir | oteim | witeim | sett sefrim im caw | cwo | CALL | wait | PUSHF | POPF | SAHF | LAHF Test | Test | Sts | sTos | Lops | Loos | scas | SCAS bi | wi |b w D w b w ov | mov | Mov | mov | Mov | Mov) mov | Mov ie AX | OX] a OX L1 BX | SP) 1 BP] St] OF Rel | RET | Int [INT uiesP}| 1 | Typed | canyy | INTO | RET esc } esc | esc | esc | esc | esc | esc | ESC 0 1 2 3 4 5 6 7 calc | ump | ump | ump | IN| IN | OUT | OUT ¢ a ia fos | vb | vw | vo | vw Grp2 | Grp2 cec | sto} cu | sm | co | sro | Se | where moe | wo [or [oo | mf im fm [io fw vamed | A0d | on | ADe_| sas | ano | sua | xoA | CMP Shit ROL ROR ACL RGR | SHiYSAL | SHR = SAR Get fuest | — | nor [nec | mu [imu [ow io pep inc fbf CALF cALL) rT ne | Pus [She |e | Mnemonics Sintel, 1980 28087 INSTRUCTIONS (All Timing Values Typical) ¢ DATA TRANSFER FBLD=Convert packed decimal memory to temp-real and load on top of stack escape 11 1{mod 100 rim disp-lo disp-hi Timing (clocks): 300+ EA FILD = Load integer to top of stack Type 1: Short- or word-integer memory escape m 11/mod000r/m disp-lo disp-hi_ | Type 2: Long-integer memory escape 111{mod101 rm disp-lo disp-hi Timing (clocks): word-integer 50+EA short-integer 56+EA long-integer 64+EA FLD = Load real to top of stack Type 1: Stack element to top of stack escape 001/11000 i Type 2: Real memory operand escape m 0 1; mod 000r/m disp-lo disp-hi Type 3: Temp-real memory operand escape 011 [mod 1011/m disp-lo disp-hi Timing (clocks): stack element 20 short-real 43+EA long-reat 46+EA temp-real 57+EA FLDCW = Load control word escape 00 t[mod 101 tim] displo disp-hi Timing (clocks): 10+ EA FLDENV = Load environment escape 0 0 1} mod 100 rm disp-lo disp-hi Timing (clocks): 40+ EA 26 ‘Mnemonics ©Intel, 1980FBSTP = Convert top of stack to packed-decimal and store in memory escape 11 1|mod 110 r/m disp-lo disp-hi Timing (clocks): 530+ EA FIST =Convert top of stack to integer and store in word- or short-integer memory escapem11|[mod010r/m] — disp-lo disp-hi Timing (clocks): short-integer 88+EA word-integer 86+EA FISTP = Store integer and pop stack Type 1: Top of stack to short- or word-integer memory escapem11|mod0111/m| _ disp-lo disp-hi__ | Type 2: Top of stack to long-integer memory escape 111|/mod111rm| — disp-lo disp-hi__| Timing (clocks): short-integer 90+EA word-integer 88+EA jong-integer 100+EA FST = Store real Type 1: Top of stack to stack element escape 101/11010 i displo | _disp-hi Type 2: Top of stack to short- or long-real memory escape m01 [mod 010 ria] disp-lo disp-hi Timing (clocks): stack element 18 short-real 87+EA long-real 100+ EA FSTP = Store real and pop stack Type 1: Top of stack into stack element and pop stack escape 111/11011 i Type 2: Top of stack to short- or long-real memory and pop stack escape m0 1|mod 0 11 t/m disp-lo disp-hi {continued on following page) Mnemonics ® intel, 1980 2Type 3: Top of stack to temporary-real memory and pop stac! [escape 011 |mod1111/m disp-lo | disp-hi Timing (clocks): stack element 20 short-reat - 89+EA long-real 102 + EA temp-real 55+EA FSTCW or FNSTCW = Store control word escape 001|modi1irm| disp-lo | disp-hi Timing (clocks): 15+ EA FSTENV or FNSTENV = Store 8087 environment escape 0 0 1 |mod 110 rlm|----disp-io disp-hi Timing (clocks): 45+ EA FSTSW or FNSTSW = Store 8087 status word [escape 10 1 [mod 111 +m disp-lo disp-hi Timing (clocks): 15+ EA FXCH = Exchange contents of stack element with top of stack [escape001/11001 i Timing (clocks): 12 ¢ CONSTANTS FLD1=Load +1.0 to top of stack [escape 00 7]17101000 Timing (clocks): 18 FLDZ= Load +0.0 to top of stack escape 001{11101110 Timing (clocks): 14 FLDL2T = Load loge 10 to top of stack escape 001/11101001 Timing (clocks): 19 28 Mnemonics © Intel, 1980FLDL2E = Load logge to top of stack [escape 001[11101010 Timing (clocks): 18 FLDLG2 = Load f0g192 to top of stack escape 001/11101100 Timing (clocks): 21 FLDLN2= Load loge2 to top of stack escape 001111101101 Timing (clocks): 20 FLDPI= Load 1 to top of stack escape 001111101011 Timing (clocks): 19 ¢ MATHEMATICAL FABS = Absolute value of top of stack escape 001/11100001 Timing (clocks): 14 FADD = Add reai Type 1: Add stack top and stack element escape d00}/11000 i d=1 for STO) — ST(0) + ST(i); 0 for ST(i) — ST(i) + STO) Type 2: Add stack top and memory operand; result in stack top escape m 0 0/mod 000 rim disp-lo disp-hi Timing (clocks): stack element 85 short-realmemory 105+EA long-realmemory 110+EA FADDP = Add real and pop stack; result in stack element escape 110/11000 i Timing (clocks): 90 Mnemonics ©intel, 1960 29FCHS = Change sign of top of stack escape 001111100000 Timing (clocks): 15 FDIV = Divide real Type 1; Stack top and stack element; resuit in dividend location escape d00/11110 i d=1 for ST(0) — ST(O)/ST(i); 0 for STi) — ST(iISTO) Type 2: Divide stack top by memory operand, result in stack top escape m0 0|mod110r/m disp-lo disp-hi Timing (clocks): stack element 198 short-realmemory 220+EA long-realmemory 225+EA FDIVP = Divide real and pop stack; result in stack element escape 110}/11110 i Timing (clocks): 202 FDIVR = Reversed divide real Type 1: Stack element and stack top; result in divisor location escaped OO|11111 i d=1 for ST(0) - ST(i/ST(O); 0 for ST(i) =STOVST(I) Type 2: Divide memory operand by stack element; result in stack top escape m0 0|mod 111 F/m disp-lo disp-hi Timing (clocks): stack element 199 short-real memory 221+ EA long-realmemory 226+EA FDIVRP = Reversed divide real with stack pop; result in stack element escape 170[171171 | Timing (clocks): 203 30 Maomonics ©intel, 1980FIADD = Integer addition; result in stack top [escape m 1 0[ mod 0.00 rm | _ disp-lo disp-hi__ | Timing (clocks): short-integer 125+EA word-intager 120+ EA FIDIV = Integer division, top of stack by memory operand; result in stack top escape m1 oy mod 110 f/m disp-lo disp-hi Timing (clocks): short-integer 236+ EA word-integer 230+ EA FIDIVR = Reversed integer division, memory operand by stack top; result in stack top escape m 10|mod 11 1 rm disp-lo disp-hi Timing (clocks): short-integer 237+EA word-integer 230+ EA FIMUL = Integer multiplication, stack top times memory operand; result in stack top escape m1 0] mod 001 r/m disp-lo disp-hi Timing (clocks): short-integer 136+ EA word-integer 130+ EA FISUB = Integer subtraction, stack top minus memory operand; result in stack top escape m 10|mod 100 rm disp-lo disp-hi Timing (clocks): short-integer 125+ EA word-integer 120+ EA FISUBR = Reversed integer subtract, memory operand minus stack top; result in stack top escape m 10] mod 101 1m disp-lo disp-hi Timing (clocks): short-integer 125+EA word-integer 120+ EA FMUL = Multiply real Type 1: Multiply stack top and stack element escape d00/11001 i d=1 for ST(0) + ST(O) * ST(I); 0 for ST(i) — STK) * ST(O) {continued on folfowing page) Mnemonics ©lntel, 1980 3tType 2: Multiply stack top and memory operand; result in stack top escape m 00|mod 001 rm disp-lo disp-hi Timing (clocks): stack element 138/97" short-real 118+EA long-real 161+ EA/120+EA’ FMULP = Multiply real and pop stack escape 110111001 i Timing (clocks): 142/100' FPREM = Partial remainder of stack top/stack element escape 001/11111000 Timing (clocks): 125 FRNDINT = Round to integer escape 001/11111100 Timing (clocks): 45 FSCALE = Scale [ST(0) + ST(0) + 2871] escape 001/11111101 Timing (clocks): 35 FSQRT = Square root of top of stack escape 00 1]11111010 Timing (clocks): 183 FSUB = Subtract real Type 1: Subtract stack top/element from element/top escape d00/11100 i d= 1 for ST(Q) = ST(0) - ST(); 0 for ST(i) = STI) - ST(O) Type 2: Subtract memory operand from stack top; result in stack top escape m0 0/ mod 100 rim disp-to disp-hi Timing (clocks): stack element 85 short-real 105+EA fong-real 110+ EA 32 Mnemonics «intel, 1980FSUBP = Subtract reai and pop srr. escape 110)/11100 i Timing (clocks): 90 FSUBR = Subtract real reversed Type 1: Subtract stack top/element from element/top escape d00]711101 1 d=1 for ST(0)=ST())— ST(O); 0 for ST(i) = ST(O) — ST(i) Type 2: Subtract stack top from memory operand; result in stack top escape m00|mod 101 r/m disp-lo | __disp-hi Timing (clocks): stack element 87 short-real 105+EA long-real 110+ EA FSUBRP = Subtract real reversed and pop stack escape 110111101 i Timing (clocks): 90 FXTRACT = Extract exponent and significand from top of stack escape 001/11110100 Timing (clocks): 50 * COMPARISON INSTRUCTIONS FCOM = Compare real Type 1: Compare stack top and stack element escape000/11010 i Type 2: Compare stack top and memory operand escape m 0 0|mod 0 10 rim disp-lo disp-hi Timing (clocks): stack element 45 short-real 65+ EA long-real 70+EA Mnemonics ©intel, 1980 33FCOMP = Compare real and pop stack Type 1: Compare stack top with stack element and pop stac! escape 000/11017 i Type 2: Compare stack top and memory operand and pop stac escape m 0 0| mod 0114 r/m disp-lo disp-hi Timing (clocks): stack element 47 short-real 68+EA long-real 72+EA FCOMPP = Compare real and pop stack twice escape 110 11011001 Timing (clocks): 50 FICOM = Integer compare, memory operand with top of stack escape m 1 0/ mod 0 10 rim disp-lo disp-hi Timing (clocks): short-integer 85+EA word-integer 80+EA FICOMP = Integer compare, memory with top of stack, FXAM = Examine stack top escape 001 11100101 Timing (clocks): * TRANSCENDENTAL FUNCTION INSTRUCTIONS 17 FPATAN = Partial arctangent function escape 001 11110011 Timing (clocks): 34 650 Mnemonics ®intet, 1980 and pop stack escape m 10jmod 011 rm disp-lo disp-hi__ | Timing (clocks): short-integer 87+EA word-integer 82+EA FTST = Test top of stack against +0.0 escape 00 1/11100100 Timing (clocks): 42FPTAN = Partial tangent function escape 001/11110010 Timing (clocks): 400 FYL2X = Compute y * log2x escape 001[11110001] Timing (clocks): 950 FYL2XP1 = Compute y * log2(x + 1) escape 001111111001 Timing (clocks): 850 F2XM1= Compute 2*-1 escape 001{11110000 Timing (clocks): 500 * PROCESSOR CONTROL FCLEX/FNCLEX = Clear exceptions escape 011/11100010 Timing (clocks): 5 FDECSTP = Decrement stack top pointer escape 001111110110 Timing (clocks): 9 FDISI/FNDISI = Disable interrupts escape 011111100001 Timing (clocks): 5 FENI/FNENI = Enable interrupts escape 011/11100000 Timing (clocks): 5 ‘Mnemonics 6 Intel, 1980FFREE = Free stack element escape 101111000 i i=stack element index Timing (clocks): 11 FINCSTP = Increment stack pointer [escape 007[11110111 Timing (clocks): 9 FINIT/FNINIT = initialize processor escape 011111100011 Timing (clocks): 5 FRSTOR = Restore saved state escape 10 1|mod 100 rim disp-lo disp-hi Timing (clocks): 210+ EA FSAVE/FNSAVE = Save state [escape 10 1[mod110rim| disp-lo disp-hi Timing (clocks): 210+ EA FWAIT = CPU wait 10011011 Timing (clocks): 3+5n , where n is the num- ber of times test line is polled and found inactive. 36 Mnemonics @ Intel, 1980NOTES For integer functions, m=0 for short-integer memory operand; 1 for word-integer memory operand. For real functions, m=0 for short-real memory operand; 1 for long- real memory operand. i= stack element index. If mod =00 then DISP =0", disp-lo and disp-hi are absent. if mod=01 then DISP =disp-lo sign-extended to 16 bits, disp-hi is absent. If mod = 10 then DISP = disp-hi; disp-lo. If mod= 11 then rim is treated as an ST(() field. If rfm=000 then EA =(BX) + (Sl) + DISP. If rm = 100 then EA = (SI) + DISP If rm =101 then EA = (DI) + DISP If rim =110 then EA =(BP) + DISP* If rm = 111 then EA =(BX) + DISP *Except if mod = 000 and r/m= 110 then EA = disp-hi; disp-lo. ST(0)= Current stack top ST()) = Ith register below stack top d= Destination 0 — Destination is ST(0) 1 — Destination is ST(i) P=Pop - Boo FSF oO) R= Reverse 0 — Destination (op) source 1 — Source (op) destination For FSQRT: -0 V2y2 For FPTAN: 0: You may also use RUN alone, and then enter ASM86 without the RUN CUSP as often as you wish: —{:dev:] RUN ‘SERIES-II| RUN 8086, V x > At the right angle-bracket prompt, you may enter: > [:dev:] ASM86 [:dev:] yourprogram [controls] Linking ASM86 programs to 8087.LIB, E8087, E8087.LIB: > [dev] LINK86 f:dev:} prog.obj, [:dev:] £8087, [:dev:] £8087.LiB [TO [:dev:] prog.LNK] This command links your program, prog.obj, to the 8087 emulator, £8087, and its associated interface library, €8087.LIB. Use this command if your system does not contain an 8087 Numeric Data Processor. If you have an 8087 NDP, use this command: > [:dev] LINKB6 [:dev:] prog.obj, [:dev:] 8087.LIB [TO [:dev:} prog.LNK} This links the 8087 interface to your program. Mnemonics @ Intel, 1980 39f ( I! 3065 Bowers Avenue, Santa Clara, California 95051 (408) 987-8080 Printed in USA, 4263/980/10K FL