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Logic Gates
Logic Gates
1) a > ee > : <— o ® ° Fig. 7095 10. Writ the loge functions for the circuit showin in Fig 7.96 (a, (B) and [@)AB+O4 CD) AVBAC (@ AB+ ED) —_D “ iD) a ¢ pl" @ o 0 Fig. 7096© 2582 _Eloctrical Technology 11, What would be the output signal ifswo signals = 101011, and B= 110101, are applied othe inputs ‘ofan AND gate? [100 001}2 12, What would be the output signa if input binary signals given by A = 100101 and 8 = 110110 are appli to (a) OR gate (b) NAND gate and(c) XNOR gate? [a 01412 6) 0110112 (6 1011002), 13, Sketch the output waveform at C-fora2-input OR gate shown in Fig, 70.97 and with he given 4 and 2B input waveforms. . Lr, —! L_, bPe De iy ip Fig. 7087 Fig. 70 14, Sketch the ouput waveform of 2-input AND gate shown in Fig 70.98 wih the input waveforms A and. 1S, Sketch the oust waveform at D for a3-input AND gate shown in Fig. 70.99, with he given 4, # and input waveforms. )- Fig. 70. Fig, 70.100 16, Sketch the output waveform atD for a3-input IVD gate shown in Fig 70.100, with the given 4,8 and input waveforms, ‘TLitt LLU JF RL hr a >> [AS ee eS . STULL Fig, 7.404 Fig, 0.302 17. Sketch the output waveform at C fora 2-input NOR gate shown in Fig 70.101, with tbe given A and B input waveforms. 18, Sketch the output waveform at D fora input NOR gate shown in Fig, 70.102, with the given 4,8 and input waveforms. STL tT eL ,, Fig. 70.103 19, Sketch the output waveform at C fora 2-input AND gate shown in Fig, 70.103, withthe given 4 and 2B input waveforms, ©© LogicGates 2583 20, SKeichthe output waveform D Tora input NAND gateshown in Fig 70.108, withthe given A,B and input waveforms, Fig. 70.104 OBJECTIVE TESTS ~ 70 A logic gates an cleewonieeteuit which (0) makes opie decision (@) allows eleeton flow ony in one diretion (@) works on binary algebra {d)_alternates between 0 and 1 values 2. In postive logic, logic state I corresponds to (2) positive voltage (©) higher voage evel, (@)_ zeovolagelevel (4) lower voltage evel In negative logic, the logic state 1 corresponds (0) negative volage @) rato voltage (6) morenegatve voltage (lover voltage lee! 4. The voltage levels of anepaive logic system (a) must nocessarily be negative (@) may be negative orpostive (must necessarily be postive (@) must necessarily be OV and ~SV 5, The output of a 2-input OR gate is zero only wien it (2) both inputs are 0 (@) either input is 1 (6) both inputs are 1 (dither input is 0 6. An XOR gate produces an ourput only when its two inputs are (a) high (e) diferent 7. An AND gate (a) implement logic addition (©) isequivalent toa series switching cic (@) isanany-orall gate () low (same. 10. 4. 2, B (4) is equivalent toa paaliel switching cir cuit ‘When an input electrical sign A = 10100 is applied to a NOT gas, its output signal is @ own @ 10101 (© 10100 @ vo101 ‘The only function of a NOT gate i to (2) stop asigaal (6) recomplementa signal (6) invert an inpatsignal (2) actasauniversl gate AOR gate is ON only when al its inputs are @ on (©) positive (© ih (@ OFF. For getting an output from an XNOR gate, its both inputs must be @) igh © tow (©) atthesame logic evel (@ atthe opposite logic levels. Ina cetuin input logic gate, when d =0, = thea C= and when 4 = 0, B= I, then again C1 Hemust be oon gate (@ xoR ( AND (@ NAND (@ NOR “The logic symbol shown in Fig 70.105 rpre- a Fig, 70.105 (@ single-output AND gate (®)NAND gate (e)_NAND gate sed as NOT gate (2) NOR gue. ©(2584 4. The output from the logic gate shown in Fig. 70.106 wil be available whe imps... are Electrical Technology reset (amc ga (®) Band C c © 4BmiC Fig T0108 dinis 15, To gotan output I fom ciceit of Fig, 70.107, the input must bed 8 C (a) 010 (101 =e e——_|_)- Fig. 70.107 @) 100 @ 110 16, Which ofthe following loge gates in Fi 70.108 will have an output of 1? © (a) NOR () NAND (© oR (@ AND 19, Which ofthe following represents anslog data?” (a) ON and OFF states (6) Oand 1 (©) OVandSV— (@)LS,3.2,4 and 5V 20, ‘The logic gate which produces a @or low-level output when one oF both ofthe iaputs are Lis Galle ate (@ AND (oR () NOR (d) NAND 21 The ouput X of he gated network shown in Fig. 701095 @ BOF () AB+ CD + EF (© AB+cD+EF @ (A+RC-DE+H =, 4 = Do Bo oo 2 @ o sy 0 D- A ° @ Fig. 70.108, 17. Abaleaddercan be constructed from (2) te XNOR gates only F Fig. 70.109 22, ‘The digital circuit shown in Fig 70.110 gener tesa mosified clock pulse at the output. Choose ‘he correct output waverorn from the options Bivenbelow. (GATE; 2008) emnninin 94 @ TPL (@) one XORand one OR gate withtheir out ( _—|_—T) pals connected in parallel @ (6) one XOR and one OR gate with their in) pus connected in paalet (4) one XOR gate and one AND gate Fig. 70.110 18. The digital equivalent of an clectie series c= cute the ate. ANSWERS L@ 26 3 46 S@ 6@ 726 &@ %@ wo. ILO) 2.O B@ KO 10 16@ I. 1@ 1. 20.10) 2.0 2