CHAPTER Learning Objectives > Detton ct ogi Gate Disime arc LOGIC GATES toate > ino oR Gato > Eguvalontfoly Creu DOr Gate. symbotzes (ogi asion > Ineo nut On Gato > Blcuave On cate > ihe aN cave > LfuvatontRetay Crout AND Gato ymbolaos togie Mutipse ston the NOt Gat tubbiod Gator yyy BP A logic gate is a circuit that has one or more Digital Signals Applied to input signals but only one output signal. All logic Logic Gates gates can be analysed by constructing a truth > Sequential Logie Circuits Sable > Addors and Subtractors > Half Adder > Full Adder > Parallel Binary Adder > Hal subtractor > Full Subtractor , conducts. The circuit current flows via R dropping yo 5V across it. In this way, point achieves potential Fig. 703 of SV. c 2. Whon + SV is aplied o B,D conducts cating BO—S4 gh point X to goto +5 V. D, 3. When both 4 and B are ~SY, the drop across is SV because voltages of A and B are in parallel. Fig. 7042558 Electrical Technology Again, point is driven to+5 V, 4. Obviously, when there isno voltage either at 4 or B, output X remains 0, 70.6. Transistor OR Gate Fig. 705 illustrates a possible tan- sistor OR gate consisting of three inter- connected transistors, Q,, and Oy supplied froma commoa Supply 7, — +5 v 1, When +5 Vis applied to 4,0, is forward biased and soitconducts. As- suming that Q, is saturated, entire V, 5 V drops across 2, thus eausing N'to {goto ground, This, in tum, cuts off Q, thereby causing X to goto V4.6. + SV. 2. When +5 V isapplied to B, O, conducts thereby driving N to ground ie, OV. With no forward bias on its base, Q, is cut-off thus driving X again to, Le.+SV. 4. Ifboth inputs 4 and # are grounded, Q, and Q, are cut-off driving N to+5 V. As aresult, Q, becomes forward-biased and conducts fully. In that ease, entre V. drops across R driving M and hence X to ground. 70.7. OR Gate Symbolizes Logic Addition According to Boolean algebra, OR gate performs logical addition, Its ruth table can be written as given below: [must be clearly understood that“ sign in Boolean algebra does no stand for ‘he addition as understood in the ordinary or numerical algebra, In symbolic logic, the "sign indicates OR operation whose rule are given above. Inlogicalgebra, 4 +B=X means thatif 4 is tue OR Bis tru, then X will be true. Itdoes not mean here ‘that sum of A and B equals X. The other symbols used for ‘= sign are U and V. Hence, the above equation could also be writen as 4UB=X or AV B=. ‘The meaning of the last three logic additions is that output is 1 when either input A or B or both are 1. The first addition implies that output is 0 only when both inputs are 0. ‘The meaning ofthe sign often becomes clear fr the context as shown below: Fig. 705 I+1 = 2 —decimaladiton Tél = 10 binary addition Leb = 1 OR addition ‘Weean putthe above OR laws ia more general A at terms 1 1 L 1 asta a Ate @ ® Ath =A 0124 Fig. 708 @ ati=1 ‘. As we know, A can have two values: 0 or 1. When 4 is 0, then we have 0-+ 1 = Las shown in Fig. 70.6(a. When 4 = 1, then the above expression becomes : 1+ find that irrespective ofthe value of A. 1 as shown in Fig. 70.6 (8), Hence, we ©Fig. 708 70.8, Thr Input OR Gate © LogicGates [2559 Atel (i) As0ma IFA =0, then 0 + 0=0¢. outputs 0 which is ‘correct and is shown in Fig, 70. 7(a). The outputs ‘what the value of 4 is, As shown in Fig, 70.7(b), when A = 1, outputis 1 because 1 +0= 1, Again, output is what the value of Ais, (ii) AtA=A With A sett 0, the outputs O because 0+0 shown inFig. 708 (a), ‘With A setto 1, the outputis I because I + 1 as shown in Fig. 70.8 (6). Obviously, the out- pul in both cases is 4 Tre electronic symbol for a 3-input (fan-in of 3) inclusive OR gate is shown in Fig. 70.9. Asis usual in logic algebra, the inputs 4, B, Cas well asthe output X can have only one ofthe two values ie.Oorl. ‘Truth Table Itis shown in Table 702. Following points are worth noting: |, The number of rows in the table is 2° combining the three inputs. In general, the number of horizontal rows is 2” where mis the number of inputs , Fig. 709 ive there are eight ways of 2. _Infirst column , logic values alternate between 0 and | every four rows twice, 3. The second input column B alternates between @ and I every two rows four times. 4. The third input column Caltemates between 0 and | every other row eight times. ‘The truth tble symbolizes the Bool- can equation 4 + 8 + C=X which means ‘that output X is I when either A or B or Cis J or all are 1. Alternatively, X is true when either or B or Cis true orall are true, whh Iiselectroniesymbolis shown in Fig, 70.10 (a) and its equivalent switching cit- cuitin Fig. 70.10), In this gate output is 1 if its either ‘input but not both, is 1. In other words, it sesoseooe ‘Table No.70.2 B c x ° 0 o ° 1 1 1 0 Il 1 1 1 ° o 1 ° 1 1 1 o 1 1 1 1 ‘has an output | when its inputs are different. The output is 0 only when inputs are the sume. To put it bit differently, this logic gate has output © when inputs are either all 0 or all 1.2560 Electrical Technology i >< ofele B 7 pian oo4 1 aenee yo rie fa @ wo ijt jo Tis gate works on the Boolean equation A @B=X ‘The circle around plus (+) sign is worth noting, The circuit is also called an inequality comparator or detector because it produces an output only when the two inputs are different. Explanation The inclusive OR gate exemplifies the everyday usage ofthe word OR which stands for one or the other orboth, Take the following statement: To qualify for a competition, you might have to subscribe to a magaine OR belong to a club. Obviously, here is no bar on your doing both. Bul now take exclusive statement: You can be rich OR you can be poor. ‘Obviously, you cannot be both atthe sanae time The change-over switching circuit of Fig. 70.10 (6) simulates the exclusive OR (XOR) gate. Switch positions 4 and B will individually light up the lamp but a combination of A and B is not possible. ‘The truth table fora 2-input XOR gates given in Table No,70.3.Itis instructive to compare itwith ‘that foran inclusive OR gate (Table 70.1) 70.10, The AND Gate Tae electronic (or logic) symbol for 8 2-input AND gate is shown in Fig. 70.12 (a) adits equiva lent switching circuit in Fig. 70.12 (6). Itis worth reminding the readers once again that the three variables 4, 8, Ccan havea value of ether 0 or 1. Logic Operation 1, The AND gate gives an output only when al inputs ae present. A 2 MeanDaseimatatainin A) boli and Bae Hence thisgae ismnaltor nothing gate whose out | "qe Pats ay bea 5 o 3. In ThulF ale terminology the out- Fig, 70.12 putofan AND gate will be tre only ifall its inputs are true. Its output would be false if any of is inputs is false. ‘The AND gate works on the Boolean algebra AXB=X or AB=X or AB=X isa logical multiplication ands different from the arithmetie multiplication. Often the sign °° is replaced by a dot which itself is generally omitted as shown above, The logical meaning of the above equation is that ©© LogicGates 2564 1. output is Lomly when both and B are | 2. output X is tue only when both A and B are tue Asseen from Fig, 70.12 (6), the lamp ‘Table 70.4 ‘Table 70.5 ‘would be ON when both switches 4 and B are closed, Even when one switch is es AB CX open, the lamp would be OFF. Obvi- o 0 Oo © 0 0 0 _ ously, an AND gate is equivalent to 8 o 1 0 0 0 1 6 series switehing cirewi 1 0 0 o 1 0 0 ‘Truth Table Fig. 70.13 shows truth 1 o4o4 0 11 9 tbe for 2-input 41ND gate and Fig, 70.14 gives the same fora 3-input AND 10 0 0 Fig, 70.43 gate 1 010 “As seen, X i at logic | only when all 110 0 inputsare at logic 1, not otherwise. The 11 11 procedure for writing down the first ‘ABC-X three columns isthe same as explained Fig. 70.14 in Ant 708 earlier 70.11. Equivalent Relay Circuit of an AND Gate The AND gate can be physically realized with the help of elay circuit shown in Fig. 70.15. Here, ‘the two relay contacts have been wired in series When 15 Vis applied to both input circuits, S/S relays K, and K, are energized thereby pulling M and N downwards which brings Cin contact with Pa the supply point S. Hence, ¥ goes to 45 V. FI x Itis obvious that energizing only one relay A 4 will notmake X goto 5 V. “ io 70.12. Diode AND Gate Itisshown in Fig. 70.16. Its logical operation is as under pe 1. When isat0V, diode D, conducts and Fig. 7045 the supply voltage of +5 V drops across R. Consequently, point N and hence point X are driven to 0 V. Therefore the output Cis 0 2. Similarly, when B is atO V, D, conducts thereby driving Nand hence X to ground, 3. Obviously, when both « and & are at O V, both diodes ny conduct and, again, the output X is 0 4, There sno supply current and hence no drop across R R only when both A and B are at +5 V. Only in that case, the %, output X goes to supply voltage of #5 ¥. oS 70.13. Transistor AND Circuit By Ilisshownin Fig. 70.17. Whenboth and areat+$ Vjthe | BM two transistors Q, and Q; conduct. The eurrent so produced drops the supply voltage of ~5 V across R, thereby driving point IV and hence base of Q, to ground or OV. This cuts off Q, so that X goes to supply voltage of +5. Fig. 70.16 ©© Obivously there i an output a V only when 2562 Electrical Technology “8 there is an input at 4 and 8. either eB st 0V then, oO wilde R ‘cut off and no drop will take place across R, A Ml ———+ x Hence, pe wil goo sop votage of, Consent, Ql cot nd whoo ply wolge willbe dropped scons Ry At ae 70.14. AND Gate symbolizes Logic Multiplication According to Boolean algebra, the AND gate v performs logical multiplication on its inputs as Fig, 70.47 given below: 00-0 01-0 10-0 1-1 ao 0 MIS 1 Ingeneral, we can putthe laws of Boolean multi- 1 — in plication in the following form Al=4 49-0 @ % Aa nord? Fig, 70.18, Tae above indemtties can be verified by giving values of 0 and 110. Lo AL=A When =0 then 01 =0 Fig. 70.1860) When A= then Ll Fig. 70.18 (6) iissen atin ech ease, ouput asthe same ales that o mo mre ko og 8 Wen = 0 aoc then 00 = 0 Fg TI90 @ ® Wien es then 100 Fig 70196) iissen that ups aya O whateer the value a ss When 420, thn0.0=0 — Fig7020(0 When dy Ben t--1— Fe 702006) 1eisseen tht uit las thes the ve wa Fig. 70.20 ©© Logic Gates | 2563 70.15. The NOT Gate Itis so called because its ouput is NOT the same asits input. Its also called an inverter because itinverts the input signal. It has one input and one output as shown in Fig. 70.21 (a). All it does isto invert (or complement) the input as seen from its teuth table of Fig. 70.21 (6). Te schematic symbol for inversion is a small circle as shown in Fig. 70.21 (2). The logical symbol {or inversion or negation or complementation is a ot bar over the function to indicate the opposite state Sometimes, a prime is also used as 4’. Fore arople, means not. Similerly, (AFB) means the complement of (4 syav Neoysy +B), Normally R Clase > 70.16. Equivalent Circuits for a at x NOT Gate a ‘The relay cireut of Fig. 70.22 (a) is a physical realization of the eomplemen- Ti {ation operation of the Boolean algebra . When +5 V is applied to input 4, K is ® ® energised and opens the normally closed contact thereby driving, output 2X00 V. Ofcourse, when A is at OV, has the supply voltage of +5 V applied to it because the relay contact is normally closed In the equivalent transistor circuit of Fig. 70.22 (6) when +5V is applied to, the transistor willbe fully tuned ON, drawing maximum collector current, Hence, whole of Vgg=5 V will drop across R thereby sending X to 0'V. With 0 V applied at 4, the transistor will be cut OFF and the output X, therefore, will goto V cite. +5 V, Obviously, in each case, outputs the opposite of input, Fig, 70.22 70.17. The NOT Operation It is a complementation operation and its sym- boli an averbar. It can be defined as under: a kee As stated earlier, 0 means taking the negation cor complement of which i | a1 Fig. 70.28 i-o It should also be noted that complement ofavaliccan beaker A ms sepestedly. For example, oa ‘ i=d=1 o d=i-0 c >*e Eee) id AAs seen double complementa- a a tion gives the original value as Shown inFig. 70.25. Fig. 70.24© Example 70.1. Find the Boolean equation for the output X of Fig. 70.24 (a). Evaluate Xwhen (i) A=1,B=1,C=1 {Computer Engg, Pune Univ. 1991] Solution, The output of the AND 2564 Electrical Technology . ae wae xeante @ wo —Fig. 70.24 (b) Fig. 70.25 @) X=01+1=0+1=1 err (@)XaL ett at Example 702. Find the Boolean expression for the output of Fig. 70.25 (a) and evaluate it when) A=0,B=1,C=1, (i) A=1,B=1,C=0, Solution, The output ofthe OR gate is (A + B). Afterwards, it becomes the input of the AND gate. ap When A1NDed with C,itbecomes (4 *B).C. aa X= (A+B) Fig. 70250) Gi) X = (+0. Ds vp Pa ten psn A=B=C=landX~ 0. (Digital Computations, Punjab Uni 1990) Solution, The circuit is made up of three AND gates, Obviously, itis equivalent toa single 4input AND x sey AD okt mietecinanD gate wihataninot 2 » four © » ‘Output of the frst gate is 4B, ‘thas of the second is ABC and that of the third is ABCD. Hence, final ouput is. ABCD. Fig. 7027 Substituting the given values, we get X= 1.110" 1,1.0=10=0 Example 704. Find the Boolean expression forthe output X of Fig, 70.27 (a) and compute its value when oA a s s ma Solution. As seen, one of the inputs to con the OR gateisinverted ie. becomes 4 as shown in Fig. 70.27 6). Hence, ouputis aot siven by X o © Fig. 7028© Logic Gates 2565 ox 1 Gi) x=i40 Example 70.5. What is the Boolean expression for the output X of Fig. 70.28 (a) ? Compute the value of X when (@ A=0.B=0 (i) A~LB Solution. As sc in this cae, both inputs to the OR gate have ben i in Fig. 70.28 (6), he inputs become Jad. Therefore, Boolean R expression for the-butput becomes a & B jrted. Hence as shown, Sm ® Fig. 70.28 Example 706 te down the Boolean equation or the ou ef Pig 7029 fa) Cemput svat hen 4-0. 8-0 =pD— 405-1 (i) 41,80 4B fi. 1030 Sotation. AS sen, inputs the AND gate tre AandB[Fig. 70.29), The oupatofthe AND gates. However ths out weedy th send inveirvonneted inthe ouput Hence, al opt equation i X=AB 0 2-88-15 ae) ee) a Wi) X=F1=T1 ® 5 ar i) X~ TO =00=0-1 @ o (iy X=T1 = 01 Fig 70-31 While evaluating expressions of the above type, you must remember the following two points, 1. take the NOT‘. inversion ofthe individual vem fist 2. When a NOT or inversion is applied to more than one term (ike 1.0), you should work out the OR (or AND) operation fist and then take the NOT of the result so obtained. 70.18. Bubbled Gates A bubbled gates one whose inpuls are NOTed or inverted 4 it ia negated gate. Fig. 70.30 (a) shows an AND gate whose both input are inverted. In practice, instead of this logic symbol, the one shown in Fig Table 70.6 70,30 (b) is widely used. As seen the inverter triangles have been. = As BX eliminated andthe two small circles orbubbleshave beenmovedtothe gg inputs ofthe gate, Such a gate is called a bubbled AND gate, the bubbles acting asa reminder ofthe inversion or complementation that. © = «1 takes place before ANDing the inputs 1 6 0 Irvwould be shown later that bubbled AND gateisequivalentto. = 11 aNOR gate Fig, 7032 ©© 2566 Eloctrical Technology Similarly, « bubbled OR gates equivalent to a AND gate. 70.19. The NOR Gate In fact, it isa NOT-OR gate. It can be made out of an OR gate by connecting an inverter in its ‘output as shown in Fig. 70.31 (a), The output equation is given by X= 058 A.NOR function is just the reverse ofthe OR function Fig, 70.33 Fig. 70.34 Logie Operation ANOR gate will have un output of | only when allits inputs are 0. Obviously, if any input is 1, the output will be 0. Alternatively, in a NOR gate, output is true only when all inputs are false. Te truth table for a 2-input NOR gate is shown in Fig. 70.32, It will b observed thatthe output Wis just the reverse ofthat shown in Fig, 70.2 ‘The equivalent relay circuit for a NOR gate is. 5) shown in Fig. 70.33, 3 Itis seen thatthe lamp glows under 00 input con- dition only but not under 01, 10,11 input conditions K-AtB Fig, 7038 The transistor equivalent of the NOR gate is shown in Fig. 70.34. Asseen, output. is 1 only when both transistors are cut-off ie. when 4 = Oand B=. Forany other input condition like 01, 10nd 11, one or both transistors saturate forcing point 2X to go to ground, 70.20. NOR Gate is a Universal Gate 11 is interesting to note that a VOR gate can be used to realize the basi logie functions : OR, AND and NOT. Thatis why itis oflen referred to as a universal gate. Examples are SY) can Benet 1 ASOR Gate As shown in Fig. 70.35, the output fom NOR gateis + B. By using another inverter in the output, the inal output is in- Fig, 7036 verted andis given by X= +B which isthe logic function of a normal OR gat. ta B ©© LogicGates 2567 2, ASANDGate Here, swo inverters have been used, one for each input Fig. 70.36). The inputs have, thus, been inverted before they are applied to the NOR gate The output is + B which can be proved (with the help of De Morgan's theorem) 10 be equal 10 AB, Incidentally, we could have used a bubbled NOR gate forthe above purpose. 3. AsNOTGate intrior ot Switch in | _doorelosed- 1 The two inputs have left door once) been tied together as shown in Fig. 70.37 (a) The interior itis A + A which can ‘be proved to be equal to 4 ‘Switch in |_door closed - 1 ™AND with the help of De right door | door open-0 ate Morgan's theorem, Instead ‘The NAND gate Is used to design an interior lighting system of a ear ofthe first symbol, the sec~ uch that he gh eswtched of only when bot doors are shut fond syanbol shown in Fig, A ras7( swt wl how ony ae FJ ATA Aa I hs bon sed ® ® Hereisa different way of making OR end AND gates. Fig, 7038 (a) showshow we ean use NOR gates to produce an OR gate. Simi- larly, Fig. 70.38 (6) shows the formation of an AND gate from throe NOR gates. Knowledge of De Morgan's theorem is needed to understand ther logic operation, A 5 70.21. The NAND Gate, er is infact,aNOT-AND gate. g By 4 Itean be obtained by connecting 5 @ o NOT gate in the output of an @ AND gate as shown in Fig, 70.39, Its output is given by the Boo! Fig. 7038 Fig, 7037 Tis gate gives an output of | ifits book inputs ae not 1. In other words, it gives an output 1 if cither A or B or both are 0 ‘The truth table for a2-input NAD gate is given in Fig, 70.40. Its just the opposite A A <=, of the uth for AND gate. Itis so because eI re 8 7H Nana pefommoseverse funtion ofan is © AND at. ; The equivalent relay circuit ofa.VAND Fig. 7029 gates shown in Fig. 70.41 ©© 2568 Eloctrical Technology Tks seen that lamp glows under input conditions of 00 01, 10 but not under 11 inp condition ‘Normally Seed a |e || x o fo |t “KG o fi |fo rfolfj4 1 |1 jlo Hh Fig, 7040 Fig, 7001 when both switches A and are ON. The diode transistor equivalent of NAND gates shown in Fig. 70.42. tis seen that point 4’ would be driven to aground when either D, or D, ox both D, and D, conduct. It represents input conditions of 10, 01 and 11*. Under such conditions, Qs eut off and hence X goes to V pcmeaning loge | state, Only time X is 0 is when 4 = 1 and B= 1 (ce. input Fig 7042 voltages a and are at+SV) so that Vis +5 V and Qis saturated 70.22. NAND Gate is a Universal Gate NAND gateis also called universal gate be- A cause it ean perform all the three logic funetions e x ofan OR gate, AND gate and inverteras shown Sa e a below. a o © ‘As shown in Fig. 70.43 (a), NOT gate can 7 eis Fig, 7043, ‘be made out of a NAND gate by connecting its two inputs together. When a NAND gate is used as a NOT gate, the logic symbol of Fig. 70.43 (6) employed instead. Te use of two NAND gates to produce an AND gate is shown in Fig. 70:44 (a) Similarly, Fig, 70.44 (8) shows how OR gate can be made out of three NAND gates. The OR fimetion may not be clear from the figure because we need De Morgan’s theorem to prove that @ B ANB. DD. ? Fig. 70.44© Logic Gates | 2569 70.23. The XNOR Gate isknown esanot-XOR gate Le. YOR gate A P| * Its logic symbol and truth table are shown in Fig. 71045, Came Its logic function and trth table are just the o}1 io reverse of those for XOR gate (Att 70.9), ede This gate has an output 1 if its both inputs are cther 0 oF 1, In other words, for getting an Fig, 70.45, ‘output, its both inputs should be at che same logic evel of either 0 ot 1, Obviously, it produces no output iis two inputs are atthe opposite logic level 70.24. Logic Gates at a Glance In Fig. 70.46 is shown the suramary ofall the 2-output logic gates considered so far along with their truth tables, Following points should prove helpful when writing these truth tables: 1. Infirstcolumn 4, logic values altemate between 0 and I every two rows 2. Insecond column B,logie values alternate every other row 3. Columan.X is filled up as per the logic function it performs sD a Fig. 70.48, 4. ‘Truth ables for NOR, NAND and XNOR (or KOR) gates are just the opposite ofthose for ORANDand | 1/9 10/1 1 XORexes, Example 70.7. An electrical signal is expressed as 101011. Explain its meaning. If this signal i applied to a NOT gate, what would be the output signal ? rfofijoja 4 ofilolijo o© Solution. The signal represents binary number 101011. Its electrically represented asa train ofpulses. Taking positive logic, | wll epresent high voltage and will represent low (or zero) voltage as shown in Fig, 70.47 ‘When sucha signal i applied to @ NOT gate, it would be inverted or complemented as shown in Fig. 7048, The NOT output will epresent the binary number 010100, Example 708. Two elecvical signals rep- resented by A= 101101 and B= 110101 are ‘applied to a 2-input AND gate. Sketch the culput signal and the binary number it repre~ sents. Solution. The pulse trains corresponding © rio oj1 joj tod and B are shown in Fig. 70.49. T Remember that in an AMD gat, Cis | only ee ‘when both 4 and B are 1. Itisanallor-nothing Fla, 7049 ‘gate. The output canbe found in different time intervals as under: Istinterval 2nd interval Sedimterva 4th interval Sthinterval 6th interval ence, ouput ofthe AND gate is 100101, Its sketched in Fig. 70.49, Example 70... Convert the Boolean expression (AB + C) into a logic circuit using different logic gates. (Computer Engg, Pune Univ. 1992) Solution. In such cases, itis best to stat with the ouput and work towards the input. As seen, Chas been ORed with 4B. Hence, the output gate must bea 2-input OR gate as shown in Fig. 70.50, @, Now. ism 4B isan AND fation, Heres weneedan 8 (apo) 2570, Electrical Technology 16 AND¢atowithinpuis 4 and, Thecompletclogiccieitis shown in Fig, 70.50 (b). @ xample 70:10. Design logic hardware Based onthe Aj Bevlanexpresion A+ BC). 21 ‘Solution, We will work from output to input, It is seen AB+C that he last gate isa 2anput OR gat wth inputs Of 4 and BC .Itisshown nig. 70510 @ © Since J hasbeen AND with C itequres an AND Fi, 70.50 gate as show in Fig. 7051 (6), For inversion of 2, a NOT fale hes been wed as shown in Fig. 7.51 (0. a a eT »B (Computer Science, Allahabad Un 1992) Solution, Working om ouputtoinput, we ind tat te ouput gate aso bea it AND gate with inputs of (4 + B) and AB. The first step of the circuit design is shown in Fig, 70.52 (a). tis also seen thatthe input tothe entze circuit consists of and B only. ©© LogicGates 2574 . —_— o Soa @ ana . . —)™ m—\ : ry eS © (A+B).AB — Ls Pel 5 Fig 7051 Fig. 7052 The input of (A +B) has been obtained with the help of an OR dl i] i] gate as shown in Fig, 70.52 (b). av Finally, aVAND gates con- 4 nected in parallel with the OR fale forgetting is inputs of and ‘Band thereafter for supplying an output of 4B. The compete cir carats teerpeser IT TTL 70.28. Digital Signals Applied to Logic Gates ov but the application of a time se- +5v y +5y waveforms can be ORed by ov y tiny tee ies JUUL 70.26. Applications of Fig. 70.53 Logic Gates A. to build more complex devices like binary counters ete 2. for decision making in automatic control of machines and various industil processes, 3. incalculators and computers, 4. indigital measuring techniques, ©2572 _ Electrical Technology Fig. 70.54 in digital processing of communica- tions, att 6. inmsicalinatruments games and do- mesic applinces et. Sometimes i is more convenient to show ® PLEA — x the digital signals or pulse waveforms without B thex-andy-axes The examples below wil fol low tis practice Example 7012. Fig. 70.55 shows an OR gate with rwo input waveforms. What isthe resulting ‘output waveform ? Solution, Remember thal the output ofan OR gules when ihe or both inputs are 1, Ther fore, we can sketch the ouput wave frm, Cas shown in Fig, 70.56 Fig. 7055 Fig. 70.56 Fig. 7057 Example 70.13, Fora three-input OR gate shown in Fig. 70.57 determine the output waveform. x UL, Fig, 70.58 Solution. Remember the output ofa three-input OR gate is 1 when one or more of the inputs are ©© LogicGates 2573 1. Therefore, we can sketch the output waveform, Das shown in Fig. 70.58 Example 70.14. Fig. 70.59 shows a 2-input AND gate with waveforms A and B. Sketch the resulting ouput waveform. 4 ne B x Fig. 7089 Solution. Remember the AND gate produces an output 1 only when alts inputs ae present. ‘Thus the ouput of AND gate is 1 whenboth 4 and are 1. Hsouput A! LT?L_ Te 11] is 0 when any of ts inputs s 0. Us- | a ing this concept, we ean sketch the PL ‘output waveform as shown in Fig 7000. xt St A Example 70.15. For a 3-input AND gate with waveforms A, Band Cat its inputs as shown in Fig. 7061, determine the resulting output waveform x Fig, 70.60 > etL ft M_ 3 Solution, A 3-input AND gate produces an output 1 only when all the thee inputs 4, Band Care 1. Its output is 0 when any one of tree inputs is 0. Using this concept, the resulting output ‘waveform is as shown in Fig, 70.62. Example 7016. Fig. 7063 shows the a—!/ J) S7 two maeforms apie oth NORote ms FL ‘pts. Sketch the resulting output waveform, B—'i) HI tt Solution. Remember, a NOR gate will | have an ouput oat wen aleinas eff | aie0, Obviouly.anyinputisttheouput willbe 0. Using tis concept, we can sketch the output waveform as shown in Fig, 70.64, Fig, 70.62 Example 70.17. ‘Sketch the output waveform for a 3-input NOR gate shown in Fig. 70.65. Showing the proper time relationship to the inputs. a a Sono Sb: Fig. 70632574 Electrical Technology alle TL. ate sp LI LiL Fig. 70.66 Solution. Remember, a3-input NOR gate will have an outputof I only whenall ‘the three inputs 4, B and Care 0. Obvi- ously ifany one of the three inputs 4, B and Corall are 1, the output will be 0, ‘Using this concept, we ean sketch the ‘ouiput waveform as shown in Fig 70.6. Fig. 70.65 1 a Example 70.18. Fig. 70.67 shows the nwo ‘waveforms A and B applied othe NAND gate tT lL inputs. Determine the resulting output wave- _e som Solution. Remember, the output of NAND gateis lifeither4 orB orboth are 0. Using ~ r this concept, we can sketch the output wave- Fig. 70.66 formas shown in Fig, 70.68, SUL ry, Jaa Fig. 70867 Example 70.19, Sketch the ouput waveform for a 3-input NAND gate shown in Fig. 70.69 ULL sto 1 x LL Fig. 70.68 TAL Solution, Remember, te ouput of@3in- : t put NAND gates only ifeitherany one ote inputs A, Band Coral a0, Using this con- a ie cpl, we can sketch the ouipt waveform as fo Showin Fig 7070 Fig. 70.69 ©Logic Gates (2575 ‘Example 70.20. The waveforms A and B are ap- ‘plied as an input to the XOR and XNOR gate as shown —“~|__17) I~ & x in Fig 70.71. Determine the output waveforms of $-—)_- ——~ these lope gates Solution. In exclusive-OR (XOR) gate, outputis — 1 ifits either input but not both, is 1. In other words, ‘thas an output 1 when its inputs are diferent. The iii Fig, 70.70 . cusps oly when ngs Sp) Selteame: Uangticon. curwecasheuhihexOR ety wevtorm shown | b= aes | in Fig. 7072, Swe In 1c, outputs ap tatt InXNOR gate, outputis 1 ifits both inputs are either 0 of L. Itproduces 0 output its two inputs are atthe opposite logic level. Using this concept, we ean, sketch the XNOR output waveform as shown in Fig, 70.72 L) Fig, 70.72 Circuit It isa circuit built from various logic gate combinations. ‘The circuit possesses a set of inputs, a memoryless logic network to operate on the inputs anda set of outputs as shown in Fig, 70.73 (a. ‘The output from a combinational logic circuit depends solely on the present input values and not on the previous ones, Moreover, output combinational networks are used to make logical decisions and control the operation of different circuits in digital electronic systems. For a given set of input conditions, the output of sucha circuits the same, Consequontly, ruth able can fly describe the Screams od ‘Memory oats tit Lit i oni ont Ea a TTT ll cera apt sells o o Fig. 70.73 ‘operation of such a circuit, Examples of such a circuit are : decoders, adders, multiplexer and demultiplexers ete ©© 2576 Electrical Technology 70.28. Sequential Logic Circuits Such circuits have inputs, logic network, outputs and a memory as shown in Fig. 70.73 (b). Their present output depends not only on their present inputs but also on the previous logic states of the outputs. Examples of such circuits area variety of latches and flip-flops, Sequential logic eieuits may be either synchronous or asynchronous. The synchronous sequential circuits are built to operate at a clocked rate whereas asynchronous ones are without clocking, 70.29. Adders and Subtractors Te logical gates discussed so far can be used for performing arithmetical functions like addi- ‘tion, subtraction, multiplication and division in electronic calculators and digital instruments. In the central processing unit (CPU) of a computer, these arithmetic functions are carried out by the arithmetic and logic unit (4L.U). The logic functions used generally are XOR, OR and AND. We will, consider the following: A. Half Adder—itis L-bitadder and earres out binary addition with the help of XOR and A gates, It has two inputs and two outputs, 2, Full Adder—It has three inputs and can add three bits at a time. I is made up of neo half ‘adders and one OR gate. ‘These adders can also perform subtraction by the method of I’s and 2's complements 3. Half Subtractor—it uses one XOR and one AND gate. 4. Pull Subtractor—it employs two half subtractors and one OR gate, 70.30. Halt Adder ‘Table 70.7 vD can add 2 binary digits at , , pat [Output time and produce a 2-bit data i. eee sum and carry aecording to the bi- i olololo nary addition ules (Art 70.10). s Block Diagram mw sin [ofi]ajo Iti shown in Fig. 70.74. AS c rlojijo can be seen, it has two inputs for cmy [ili loli applying the two binary digits to be rig. To.74 added. As is well known, binary addition of two bits always produces 2-bit output data -e. one SUM and one CARRY. For example, (11) givesasum of O anda carry of 1. Also, (0 0) gives the sum 0 and carry 0. That is why the adder has two outputs : one for SUM and the other for CARRY ‘Truth Table 70.7 lists the two columns of input, one of SUM and one of CARRY. ‘The SUM output has the same logic AT) > patemas when dis KORG with. Infact to add itto XOR. Also, the CARRY output has the same logie pattem as when 4 is ANDed with B. Thats why ahalf-adder ean be formed from a combination, of one XOR gate and one AND gate as shown in Fig. 70.75 © The circuit is called halfadder because it cannot accept ccary-in from previous additions. For that purpose, we need a 3+ Fig, 70.75 input adder called full-adder. ©© Logic Gates |2577 Incidentally, the logical equations for the SUM and CARRY are S gt sm [AT* Te a ee topoe ofo |r 3 a oft fo Ge Jo)a fi Gay G Bijele tfe fi tft fe tii Fig 1078 70.31. Full Adder As shown in the block diagram of Fig, 10.76, ithas three inputs and two ouputs. Itcan add 3 digits (or bits) atatime. The bits and B which are to be added come from the two reper and the third pt comes | cay \ cay from the cay gencated bythe pevie Ts | ==) f cus addition. I produces two outpus, Bt | MA [Sum 1 ‘SUMand CARRY-OUT. aa t The truth table 70.9 gives all pos- sible input/output relationships for the full adder. 4 and B are the inputs from Fig. 70.77 ‘the respective digits ofthe registers to be added and C, is the input for any carzy generated by the previous stage. The SUM output gives binary addition of 4, B and C, The other ourput generates the carry C, to be added to the next stage ‘The full adder can be constructed from two helf-adders and one OR gate (Fig. 70.77) Working, Let us illustrate, with the help of two examples, how this full adder adds three bits 4 ot loge) ot yale ae) leg i =i o Jo __o 1————+ es @ A=1,B=1,6 ‘The fll adder with these three inputs is shown in Fig. 70.78. First halfadder gives a sum of Oand ‘carry of I. The second H. givesa sum of 0 with acarry of 0, The final outputis: SUMO, CARRY 1, As we know fiom the rules of binary addition, | ~ 1+ 0=10, ({e decimal 2, ©2578 Electrical Technology (i) A=1,B=1,0=1 As detailed in Fig. 70.79, we geta final SUM 1 with A Cary a CARRY 1, The result conforms to the binary © addition: 1+ 1+1= 11, (ee. decimal) s Detailed Circuit © Fig. 70.80 shows more ciruit deals ofa fll B maa aaddes. The two half adders have been replaced by thei XORand AND gates. The final cary is given Sum by the OR gate and final sum by the XOR gate of the second adder Fig, 70.80 70.32, Parallel Binary Adder Poradding two 4-bitnumbers, we need 4 full adders connected in parallel as shown in Fig, 70.81. The two numbers being added are A, Ay 4, Ag and B, B, By Band their sum is 5, 5,5, 8, Sy ss a 4 s By po el rE car c ised Len rs SE) a fe Sea fp SS pq fg Died tend 5S 5 5, & Fig 70.81 ‘The frstadder could be a half adder though we may use a ill adder but leave its CARR Y-IN lead unconnected. As sees, differen bits are fed tothe four adders from two parallel registers which bold these bits. The final SUM appears as a S-igit display Operation Tae actual operation may be better understood with the help ofthe diagram of pose, we want to-add the following two 4-bit numbers Il ig. 70.82. Sup- Regiser-A Taf amt Teta stale Sum Register B Fig. 7082© LogicGates 2579 1010 10 Hou su TOrO! 21 ‘The first adder performs 0+ | binary addition, giving a sum of | and a carry of 0, The two bits 0 and | are supplied simultaneously from the two registers A and B. ‘The sum 1 appears onthe display panel and carry 0 is passed on tothe next fuller. feet The next adder adds 1 4 1 Topat_[_Oupur Hocarry=sum twithaeany 1. a. > Ate {w{p ‘The third adder performs 0+ 0-+ ns | Dittzence |o | 0 | 0 | o 1 cany = 1 with cary 0. The fourhadderalis1*1-Ocary—® perma ne sum 0 with eazry 1 both of rfo}o}i which appear on the display rfifolo unit. Hence, the final addition of the two numbers appears as Fig. 7085, 10101. It may be noted that the largest binary numbers that ean beaded by this parallel adder are 11 end 1111 which givea sum of 11110, (decimal 30), To increase its capacity, more full adders may be connected atthe left end of Fig. 70.82. For example, foradding 6-bit numbers, we will have to add two more adders thus making a total ofsix 70.33. Halt Subtractor Tan nye nay ii tine po nope of cece ad born hush nt ek gram ai thar apd wept The open ofs tse bod on tls by beacon ard ine at nse ab icaoetpeonpton Bitiar he auto wage te fa Shecinrasceslegopabeeat tance oie Sone wit ame he oer SUA An toa0) fees neces TOR gate elfen sas bin Thebo pt {Bib Gindcounn canbe clued by ANDi ae "ae The cca al wtracter shown a a ems pvtomone cuts ogo he tice en brow ashen D=A@BandW= 4B 70.34, Full Subtractor a ouput ‘As shown inthe block diagram of Fig. 70.85, it Borrow has three inputs and two outputs. As explained B Bs 3 above, half subtractor can handle only 2 bits at ‘time and can be used forthe least significant col- Input, Db umn of e subtraction problem. full subtractor BQO ies can, however, take care of higher-order columns. : Fig, 7085 ©© As shown in Fig. } 70,86, a fll subtractorcon- A Borww. i sits of two half subtractors pads] Borow) Quip and one OF gate. us ! Tt may be remarked 2 2580 Electrical Technology [Pilference —erethat by cascading 4 ull subtracts, we ean diretly Fig, 70.86 subtract 4-bit numbers ie wwe can subtract B, B; B, BofiomAsAzAy Ay Tutorial Problems No. 70.1 Find the Booleen equation for the ousput ofthe logie cireuit shown in Fig 70.87. What would be the outputita = 1,8 D=1 keaB +c =D [yy —_) > [ >> 7087 mg. 7088 2 Yiateoaupueqencielpcheshovn ing 189 Siteopt d= ea teasorn 3 Afi be Bos nin rt cen ini 1083 capi mp8 Sareea Meena r A >) —_—=_D- 3 Fig. 70.89 Fig. 70.90 4, Translate the hardware shown in Fig. 70.90 into Boolean expression. Compute the value of the output if =0,B = 1,C=0,D= 1 1k= a +BCD 30) ‘5. Whatis the Boolean expression forthe logic diagram shown in Fig. 70.917 Fvaluateits output if and C eB +C 1) aT ) a al L x [> Fig, 7091 Fig. 70.92© Logic Gates | 2584 6, Find Boolean expression rte logic eu oF. 7092. Whats the output fA = 1, X- (A+B). Asm 17. Give the loge funsions performed by the circuits shown in Fig. 70.93 (a) (6) and () [@)X= KBEFD) 6)X~ ABC (© AFH) 2 ® bo ye co > ® o © fig 7098 1. Suttle cis hv in 7098), fas BCD) ab CD)A+B. CEI >) “> > ° eo r ca

1) a > ee > : <— o ® ° Fig. 7095 10. Writ the loge functions for the circuit showin in Fig 7.96 (a, (B) and [@)AB+O4 CD) AVBAC (@ AB+ ED) —_D “ iD) a ¢ pl" @ o 0 Fig. 7096© 2582 _Eloctrical Technology 11, What would be the output signal ifswo signals = 101011, and B= 110101, are applied othe inputs ‘ofan AND gate? [100 001}2 12, What would be the output signa if input binary signals given by A = 100101 and 8 = 110110 are appli to (a) OR gate (b) NAND gate and(c) XNOR gate? [a 01412 6) 0110112 (6 1011002), 13, Sketch the output waveform at C-fora2-input OR gate shown in Fig, 70.97 and with he given 4 and 2B input waveforms. . Lr, —! L_, bPe De iy ip Fig. 7087 Fig. 70 14, Sketch the ouput waveform of 2-input AND gate shown in Fig 70.98 wih the input waveforms A and. 1S, Sketch the oust waveform at D for a3-input AND gate shown in Fig. 70.99, with he given 4, # and input waveforms. )- Fig. 70. Fig, 70.100 16, Sketch the output waveform atD for a3-input IVD gate shown in Fig 70.100, with the given 4,8 and input waveforms, ‘TLitt LLU JF RL hr a >> [AS ee eS . STULL Fig, 7.404 Fig, 0.302 17. Sketch the output waveform at C fora 2-input NOR gate shown in Fig 70.101, with tbe given A and B input waveforms. 18, Sketch the output waveform at D fora input NOR gate shown in Fig, 70.102, with the given 4,8 and input waveforms. STL tT eL ,, Fig. 70.103 19, Sketch the output waveform at C fora 2-input AND gate shown in Fig, 70.103, withthe given 4 and 2B input waveforms, ©© LogicGates 2583 20, SKeichthe output waveform D Tora input NAND gateshown in Fig 70.108, withthe given A,B and input waveforms, Fig. 70.104 OBJECTIVE TESTS ~ 70 A logic gates an cleewonieeteuit which (0) makes opie decision (@) allows eleeton flow ony in one diretion (@) works on binary algebra {d)_alternates between 0 and 1 values 2. In postive logic, logic state I corresponds to (2) positive voltage (©) higher voage evel, (@)_ zeovolagelevel (4) lower voltage evel In negative logic, the logic state 1 corresponds (0) negative volage @) rato voltage (6) morenegatve voltage (lover voltage lee! 4. The voltage levels of anepaive logic system (a) must nocessarily be negative (@) may be negative orpostive (must necessarily be postive (@) must necessarily be OV and ~SV 5, The output of a 2-input OR gate is zero only wien it (2) both inputs are 0 (@) either input is 1 (6) both inputs are 1 (dither input is 0 6. An XOR gate produces an ourput only when its two inputs are (a) high (e) diferent 7. An AND gate (a) implement logic addition (©) isequivalent toa series switching cic (@) isanany-orall gate () low (same. 10. 4. 2, B (4) is equivalent toa paaliel switching cir cuit ‘When an input electrical sign A = 10100 is applied to a NOT gas, its output signal is @ own @ 10101 (© 10100 @ vo101 ‘The only function of a NOT gate i to (2) stop asigaal (6) recomplementa signal (6) invert an inpatsignal (2) actasauniversl gate AOR gate is ON only when al its inputs are @ on (©) positive (© ih (@ OFF. For getting an output from an XNOR gate, its both inputs must be @) igh © tow (©) atthesame logic evel (@ atthe opposite logic levels. Ina cetuin input logic gate, when d =0, = thea C= and when 4 = 0, B= I, then again C1 Hemust be oon gate (@ xoR ( AND (@ NAND (@ NOR “The logic symbol shown in Fig 70.105 rpre- a Fig, 70.105 (@ single-output AND gate (®)NAND gate (e)_NAND gate sed as NOT gate (2) NOR gue. ©(2584 4. The output from the logic gate shown in Fig. 70.106 wil be available whe imps... are Electrical Technology reset (amc ga (®) Band C c © 4BmiC Fig T0108 dinis 15, To gotan output I fom ciceit of Fig, 70.107, the input must bed 8 C (a) 010 (101 =e e——_|_)- Fig. 70.107 @) 100 @ 110 16, Which ofthe following loge gates in Fi 70.108 will have an output of 1? © (a) NOR () NAND (© oR (@ AND 19, Which ofthe following represents anslog data?” (a) ON and OFF states (6) Oand 1 (©) OVandSV— (@)LS,3.2,4 and 5V 20, ‘The logic gate which produces a @or low-level output when one oF both ofthe iaputs are Lis Galle ate (@ AND (oR () NOR (d) NAND 21 The ouput X of he gated network shown in Fig. 701095 @ BOF () AB+ CD + EF (© AB+cD+EF @ (A+RC-DE+H =, 4 = Do Bo oo 2 @ o sy 0 D- A ° @ Fig. 70.108, 17. Abaleaddercan be constructed from (2) te XNOR gates only F Fig. 70.109 22, ‘The digital circuit shown in Fig 70.110 gener tesa mosified clock pulse at the output. Choose ‘he correct output waverorn from the options Bivenbelow. (GATE; 2008) emnninin 94 @ TPL (@) one XORand one OR gate withtheir out ( _—|_—T) pals connected in parallel @ (6) one XOR and one OR gate with their in) pus connected in paalet (4) one XOR gate and one AND gate Fig. 70.110 18. The digital equivalent of an clectie series c= cute the ate. ANSWERS L@ 26 3 46 S@ 6@ 726 &@ %@ wo. ILO) 2.O B@ KO 10 16@ I. 1@ 1. 20.10) 2.0 2