You are on page 1of 9
IPS ISAO7N65A N-Channel MOSFET ® Lead Free Package and Finish Applications: + Adaptor Voss | _Rosion) (Typ.) lo + Charger 650V 1.10 7.0A + SMPS Standby Power Features: + RoHS Compliant D + Low ON Resistance + Low Gate Charge call + Peak Current vs Pulse Width Curve f Wt + ESD improved Capability Y KO 64 a a Ordering Information 8 T0-220F Package PART NUMBER PACKAGE MARKING. hee oe ISAO7NGEA 0-220 ISAO7NG5A $ Absolute Maximum Ratings _Tc=25 °C unless otherwise specified ‘Symbol Parameter ISAO7N65A Units Vo Drain-to-Source Voltage (NOTE “1) 650 v Ib Continuous Drain Current 70" y@ 100°C | Continuous Drain Current Figure 3 A low. Pulsed Drain Current, Vas@ 10V (NOTE +2) Figure 6 p. Power Dissipation 42 w 2 Derating Factor above 25°C I 0.34 wie vi Gate-to-Source Voltage £20 v re Single Pulse Avalanche Engeray = = y Pulsed Avalanche Rating Figure 8 A vide Peak Diode Recovery dvidt (NOTE *3) 5.0 Vins VESD(G-S) | Gate to Source ESD(HBM-C=100pF,R=1.5KA) 3000 v Maximum Temperature for Soldering T Leads at 0.063 in (1.6 mm) from Case for 10 seconds 300 Tox Package Body for 10 seconds 260 c Operating Junction and Storage Tard ste | Temperature Range $510 180 * Drain Curent Liste by Maximum Junction Temperature Caution: Sresses greater har those listed in the ‘Absolute Maximum Ratings” Table may cause permanent damage to the device Thermal Resistance ‘Symbol | __ Parameter ISAO7NE5A Unit ‘Test Conditions Drain lead soldered to water cooled heatsink, Pp ack psec nena am juste for @ peak junction temperature of +150°C. Raya | Junction-to-Ambient 4100 “COW [1 cubic foot chamber, fee ai ©2014 InPower Semiconductor Co., Ltd Page 1 of 9 ISAOTNGSA REV.C Jun. 2014 OFF Characteristics + Tj=25°C unless otherwise specified ‘Symbol Parameter Min. | Typ. | Max. [Units Test Conditions BVoss Drain-to-Source Breakdown Voge | 650 | — Vv Ves=0V, 1g-250HA BreakdownVoltage Temperature Reference 10 25°C, 48Voss/4 Ty | Coefficient, Figure 11. 7] 98 | = | owe Ip=250qA - | - | 10 Vps=650V, Vas=0V loss Drain-to-Source Leakage Current WA - | = | 100 Vos: A Giate-o-Source Forward Leakage = [| = | 10 ss /Gate-to-Source Reverse Leakage =p- ps0] “ ON Characteristics TJ=25°C unless otherwise specified ‘Symbol Parameter Min. | Typ. | Max. | Units Test Conditions Static Drain-1o-Source On-Resistance Ves=T0V, I5=35K Rosiomy | Figure 9 and 10. ~| "i" ° (NOTE *4) fase | Gate Threshold Voltage, Figure 12 20 [=| 40 Vv Vos=Ves: lb=250:A fs Forward Transconductance Palade s VosS0V, tor3'5& (NOTE *4) RE [Gate Resistance = [16 = a ‘Vps =0,_fIMHz Dynamic Characteristics Essentially independent of operating temperature ‘Symbol Parameter Min. | Typ. | Max. | Units Test Conditions Con Input Capacitance =_ [107 [= Ves=0V Coes ‘Output Capacitance =} 400} _ Vos25V f=1.0MHz Coss Reverse Transfer Capacitance - | a7] - pared a Total Gate Charge = | ei ‘Vpp=350V Qe Gate-o-Source Charge =[e >=] re Ip=7A Oye Gate-o-Drain (Miler?) Charge -~|2]—- Figure 15 Resistive Switching Characteristics Essentially independent of operating temperature ‘Symbol Parameter Min. | Typ. | Max. [Units Test Conditions TON Turn-on Delay Time = [1 = oy Rise Time = [1 =] TwOFF) Tumn-Off Delay Time =| = Yat Fall Time = [7% 5 (©2014 inPower Semiconductor Co., Ltd. Page 2 of 9 ISAO7NGSA REV.C Jun. 2014 ‘Source-Drain Diode Characteristics Tc=25°C unless otherwise specified ‘Symbol Parameter Min. | Typ. | Max. | Units | Test Conditions 1s Continuous Source Curent (Body Diode) | —- | - | 7 | A Integral pr-diode Ts Maximum Pulsed Current (Body Diode) =~ [- | [A in MOSFET Veo) Diode Forward Voltage = [= fas Tv igs 7A, Vos=0V a Reverse Recovery Time = [ze = fe Ves=0V QO, Reverse Recovery Charge = [ses [= [ne |g 7A, dldt=100 As Notes: "1, Ty = 425°C to +150°C, “2, Repetitive rating; pulse width limited by maximum junction temperature. "3. Igo= 7A dildt < 100 Alps, Vop < BVpsg, Ty=*150°C. “4, Pulse width < 380s; duty cycle < 2%. (©2014 InPower Semiconductor Co., Lid. Page 3 of 9 ISAO7NOSA REV.C Jun. 2014 aay Factor — 20% 0% 3 Figure 1. Maximum Effective Thermal Impedance, Junction-to-Case 8 5 ff _ $4 oo a ak eR 22 Spit a 008 ‘NOTES 0.0001 Hl te wes oy + ca Ss ibe wie te ectanglr Puls Deaton) Figure 2. Moximum Powe Dissipation Figure 3. Maximum Continuous Bran Curent waCore Tenparohre ve Case Temperature ® s . g z a Bos 6 3 3 ee i 2 & 1g} 2 d 0 Se wm a ‘To, Case Temperature (°C) To, Case Temperature (°C) Figure 4. Typical Output Characteristics Figure 5. Typical Drain-to-Source ON Resistance ve Gate Votage and Drain Curent ” Raaneeae ps . maces = Zo . 330 ¢ [era 8 f 6 go 15 re oa 58 sas z ps. Drain-to-Source Voltage (V) Ves. Gate-to-Source Voltage (V) ©2014 InPower Semiconductor Co., Ltd. Page 4 of 9 ISAO7NG65SA REV.C Jun. 2014 Figure 6. Maximum Peak Current Capabil pron ereanes vr" aa z r= nal < 5 i face vrs 16 ry Es ro eal 1p, Pulse Width (s) Figure 7. Typical Transfer Characteristics Figure 8. Unclamped Inductive ‘Switching Capability _ ® [puseouRation= toy mo pe ; | a § Bema ic 4 a 4 ae a: 2 3 beet 2 4 ae Vos, ete Souce Vata (v) Ser Tis rete Figure 9. Typical Drain-to-Source ON Figure 10. Typical Drain-to-Source ON Resistance Meaerton: eet oa net Tacnpenns Demers 20 g_ sslowe / Bg im ae GS 200 ag" 4 Ess aa 3 2 150 : an fs ae f° ad BE om i: . «= = = =m “a a se oo lo ran Curent “nha Tampa} ©2014 InPower Semiconductor Co., Ltd. Page Sof 9 ISAO7N65A REV.C Jun. 2014 Figure 11. Typical Breakdown Voltage vs Figure 12. Typical Threshold Voltage vs ‘Junction Temperature Junction Temperature us 12 i gu B20 a5 Bw age 3B os af ee oS 100 ee’ 3 ar & Z oss 3 i Wes 3 08 | ves¥0s Ionia ears as0 os a8 0 2% 0 a 0 7 109 125 150 78 S020 25 80 75 100 125 180 Ty, Junction Temperature (C) Ty. duneton Temperature ) Figure 13. Maximum Forward Bias Safe Figure 14. Typical Capacitance vs Operating Area Drain-to-Source Voltage 1000 10000 = 00 | 100 : & E 8 3 10 2 z & 2 0 See 6 ys maxmaren oor ten25% 1 0 100 1000 Vos, Orin-to-Source Votage(V) Vp, Drain Votage(V) Figure 15. Typical Gate Charge Figure 16. Typical Body Diode Transfer vs Gate-o-Source Voltage Characteristics .® « ee eae | Hc § i ele aaa Eo» “Be oa g sf i 4) wo Eo 3° ip=708 3° ae vaso" a 0 20 Ey 02 0a 06 0810 Total Gate Charge (6) ‘Veo, Source-o-Drain Volage (V) (©2014 InPower Semiconductor Co., Ltd. Page 6 of 9 ISAOTNGSA REV.C Jun. 2014 Test Circuits and Waveforms Vos Ves 1A, Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveform nist ri tyon) tise tyorr) Matt Figure 19, Resistive Switching Test Circuit Figure 20. Resistive Switching Waveforms (©2014 InPower Semiconductor Co., Ltd Page 7 of 9 ISAO7NGSA REV.C Jun. 2014 Test Circuits and Waveforms dildt adj. Current Pump r/ Double Pulse ous. (ff Figure 22. Diode Reverse Recovery Waveform Figure 21. Diode Reverse Recovery Test Circuit Series Switch (MOSFET) Voo ‘Commutating Diode o Ves Ves —! a sil Figure 23. Unclamped Inductive Switching Test Circuit Figure 24, Unclamped Inductive Switching Waveforms (©2014 inPower Semiconductor Co., Ltd Page 8 of 9 ISAO7NESA REV.C Jun. 2014 Disclaimer: InPower Semiconductor Co,, Ltd (IPS) reserves the right to make changes without notice in order to improve reliability, function ‘or design and to discontinue any product or service without notice. Customers should obtain the latest relevant information before lorders and should verity that such information is current and complete. All products are sold subject to IP's terms and conditions supplied at the time of order acknowledgement. InPower Semiconductor Co,, Lid warrants performance of its hardware products to the specifications atthe time of sale, Testing reliability and quality control are used to the extent IPS deems necessary to support this warrantee. Except where agreed upon by contractual agreement, testing ofall parameters of each product is not necessarily performed. InPower Semiconductor Co., Ltd does not assume any labilty arising from the use of any product or circuit designs described herein. Customers are responsible for their products an applications using IPS's components. To minimize risk, customers must provide adequate design and operating safeguards. InPower Semiconductor Co., Ltd does not warrant or convey any license either expressed or implied under its patent rights, nor the rights of others. Reproduction of information in IPSs data sheets or data books is permissible only if reproduction is without ‘modification or alteration. Reproduction of this information with any alteration is an unfair and deceptive business practice. InPower Semiconductor Co., Ltd is not responsible or liable for such altered documentation. Resale of IPS's products with statements different from or beyond the parameters stated by InPower Semiconductor Co., Lid for that product or service voids all express or implied warrantees for the associated IPS's product or service and is unfair and deceptive business practice. InPower Semiconductor Co., Ld is not responsible or lable for any such statements, Life Support Policy: InPower Semiconductor Co., Ltd's products are not authorized for use as critical components in ife support devices or systems without the expressed written approval of InPower Semiconductor Co.,Ltd. ‘As used herein 1. Life support devices or systems are devices or systems which: 8. are intended for surgical implant into the human body, '. support or sustain life, ©. whose failure to perform when properly used in accordance with instructions {or used provided in the labeling, can be reasonably expected to result in significant injury to the user 2. A.citical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure ofthe life support device or system, orto affect its safely or effectiveness: (©2014 InPower Semiconductor Co., Ltd Page 9 of 9 ISAO7NEBA REV.C Jun. 2014

You might also like