INPUT ~ OUTPUT ORGANIZATION Input — Output Organization: The Input ~ Output (VO) organization of a computer provides the mode of communication between the computer and the outside world i.c with the help of the 1/O devices. users can interact with the computer, The ers, VO devices that are attached to the computer are also known as peripherals Some of the {/O devices that are conimonly used in a computer are: Input Devices: Keyboard, Mouse, Joystick, Scanuics cic Output Devices: Monitor, Printer etc. _ Input — Output Interface Units: VO interface units are special hardware components that Tie between the /O devices and the processor bus. These des communication links, between the CPU and the peripherais, actually siserving an ef synchronize and supervise ie. control all input and output tansfers. Need of Interface Units: Certain differences between the characteristics (functional and behavioral) of the peripherals and the ‘CPU (and also memory) exist. Interface Units are needed to resolve the differences, which are: 1. Operations of the peripherals, which are either electromagnetic or electromechanical devices. are different from that of the CPU and memory, which are generally electronic devices. So a signal conversion between the two is required and is done hy the interface unit between them, 2. The interface unit has to synchronize the data transfer mechanism between the slow peripherals and the fast CPU, Totes face units handle the differences between the data codes and formats in peripherals and the CPU or memory word formats. Working mechanism of Interface Units: Bach of the VO devices has their own in erface unit. The LO devices have got their own identifying addresses also, with which the CPU identifies an /O device. in order to communicate with, an VO device, the CPU places the address of that VO device in the address bus and places the appropriate control command in the conttol bus. The VO bus from the processor is attached to all Peripherals ia the reapeetive peripheral interfaces. Te address ftom the processor 1s received Fy all the interfaces, jacls oi them decodes the address. Only that particular interface which detects its own address activ ates the path between the bus lines and the device that it controls, All other VO device whose address dose not match with the address provided by the CPU. are not activated by their respective inter!ated /O and Memory Mapped UO In.a computer system, the CPU communicates with the memory unit as well as with the /O devices via buses. Generally there are three ways that computer buses ean be used to serve as a communicating link ‘sven the CPU, memory and the UO deviees. 1 CPU communicates with the memory and the VO devices via evo separate buses, the memory bus (for memory units) and I/O bus (for the VO devices). 2, CPU communicates with the memory and 1/0 units via one common bus (address and data fines) but uses two different pairs of control lines (one for memory and another for 1/0), 3. CPU uses a completely common bus for both memory and VO units [solated I/O or /O mapped VO: Tn this mechanism, CPU communicates with the memony and VO units via one commen bus (with same address and data lines) having two differ pais of contral lines (separate read and write tines for memory and 1/0). This differentiates between memory mu /O wansfere: ‘While communicating, the CPU specifies whether the address on the address lines is meant for memory or for an 11 device by enabling the either the memory control lies (memory read or write tine) o1 the VO eontrol lines (VO read or write Tine). So during @ memory transfer, either of the memory read and memory write lines are enabled wil during an V/O transfer, either of the 1/0 read and VO write lines are enabled. This configuration 1solates all YO deklco addresses from the memory addresses i.e. in this rpechanism; CPU treats the VO addresses separately fiom the memory addresses, Each has its own separate address spaces. Henee this mechanism is known as isolated /O method. Bessy Mapped 10: Of tr metnory Mapped DO method, same address space is used for both memory and VO auldicsses. In such configuration, CPU communicates with the memory and VO devices via the same bus sion between memory and VO addresses and having completely common lines. Here there is no dist the assigned adatess spaces’ for the VO registers are nesnmed to be part of the memory system. Though the assignéd HO addresses are Kept in the memory itself, however they ean not be used to store any memory words. Hence the total storate capacity ofthe memory is reducedbetween Isolated VO and Memory Mapped 1/0: Isolated VO ] Memory Mapped UO. mon address and data Tines but distinct | 1- Completely common address. data and control | of control lines is there for memory and 1/0 | lines for both memory and /O communications with ommunications with the CPU. the CPU. CPU uses distinct instructions for handling memory | 2. No separate instructions for 1/O units CPU uses nd 1/0 devices the same instructions for handling memory and 1/0 devices. ‘Memory and VO address spaces are different, 3, Memory and VO address Spates are the same. WO} addresses are reside in the memory unit. +. Memory address range or space available is more. | 4. Due to mapping. of VO addresses in the memory, | the available memory address range or space is reduced. «Number of instructions needed in such computers is | 5. Number of instructions needed in such computers | nore, as separate memory and 1/0 instructions are | is less, as same instructions can be used for handling weeded. samemory and I/O data. Different modes of data transfer between the processor and the peripherals: There are three possible modes of data transfer between the processor and the I/O devices. 1. Programmed 1/0: - Such transfer are initiated as a result of VO instructions written in the computer program. Once the transfer is initiated, the CPU has to constantly monitor the interface units of the YO devices to see when the transfer can be actually made i.c, when the device will be ready to transfer the data. This constant monitoring requires lot of time of CPU time. In this time, the CPU remains idle as it can not do any other work but to check whether the /O device is ready to transfer data or not. Lot of CPU time is wasted in this mechanism. Interrupt 1/0 or Interrupt Initiated 1/0: - In this mechanism, the CPU need not eonstanily monitor to «see when the VO device will be ready to transfer data. Here the UO device itself will let the CPU know that itis ready to transfer data and that it wants service from the CPU. meanwhile the CPU! cap continue to executé other programs, When the device gets ready to transfer data. it will send a signal (interrupt) to the CPU to provide servies. CPU will then stop other tasks and will branch to the service program of that device to process the /O data transfer. When flnished. CPU will retum to the task It was originally performing and continue with it, Here CPU cycle is not wasted. as the CPU need not remain idle3. Direct Memory Access (DMA): - In prouramimed /O data transfer occur between CPU a, peripherals. In DMA, data transfer occurs between 1/O devices and the memory unit without direct intervention by the CPL] CPU! only initiates the transfer hy supplying the starting address of the memory location from where data is to be transferred and the number of words to be transferred. Comparison of the relative advantages and disadvantages of three modes: "Programmed /O | Interrupt Initiated VO | DMA Slaw [1 Medium. 1. Fastest. Least expensive. 2. Medium. 7 ‘2. Most expensive. a Simpletodesign. —=—=—~« 3. Slightly complicated, 3. Highly complicated. ae. Wasted of CPU cycle degrades the [4 CPU cycle is not wasted. | 4. CPU divecily does not play any role in srformance of the computer, ‘such transfer. aterrupt: os Interrupt is a signal from an /O device to let the CPU know thafit is ready to transfer data and that it is questing service from the CPU. As soon as receives t signal, it leaves its current unfinished task as it is and ‘anches to the interrupting device's interrupt servige routine and executes it to process the transfer. When nished, CPU again comes back to its unfinished task { atlicontinnes with it ‘unt Service Re ~ An Interrupt Service Routine (ISR) is actually a program stored in the ice, CPU has to secute the ISR of that particular I/O device. Each of the I/O devices has its own interrupt service routine emory of the computer. In order to handle or process an interrupt request from an /O di Different types of Interrupts: 1. External Interrupts:.- Such type of interrupts may come from any extemal sources like. fio VO devices when they are ready to transfer data, from a timing device to signify that the time ot ‘an event 1s over, may occur due to some power failures ete. Internal Interrupts: - Such type of interrupts, called traps, may occur due to some illegal or erroneous conditions in the program. Whenever there are internal errors, like register overflow stack overflow, attempt to divide by zero ete, in the program, they give rise to intemal interrupts. 3. Software Interrupts: - Such type of interrupts may be incorporated or embedded in the program scan instruction hy a programmer and are thus initiated by executing that instruction. So if the programmer want to initiate any sort of interrupt procedure at any desired puint in the prograu he may write an interrupt instruction in that point in the program,ce between external and internal inter External Interrupt fated by an external event ~~ Internal Interrupt j 1 Initiated by some exceptional | conditions caused by the | program itself “Asynchronous ta nature ‘As external interrupts are dependent on the external conditions and are dependent of the program being executed at any time, hence on rerunning © program there is very less chance that interrupt will occur in the same ace each time. Synchronous in nature. z. 3. On rerunning the program imternal interrupt will occur in the same place each time. Vectored and Non ~ Vectored Interrupts: When an interrupt request comes from an I/O deviee, CPU: stores the retum address of the next instruction to be executed in the current program from the program counter to the stack and branches to the ISR that processes the required VO transfer of that particular device. There are generally two ways by which the processor chooses the branch address of the ISR. 1, Vectored Interrupt: - In this method, the branch address (i.e. address of the ISR) is supplied by the interrupting WO device itself and the processor branches accordingly 2. Non - Vectored Interrupt: - In this method, the branch address (i.e. address of the ISR) is always assigned to a fixed location in the memory and the processor always branches to that particular location