INPUT ~ OUTPUT ORGANIZATION Input — Output Organization: The Input ~ Output (VO) organization of a computer provides the mode of communication between the computer and the outside world i.c with the help of the 1/O devices. users can interact with the computer, The ers, VO devices that are attached to the computer are also known as peripherals Some of the {/O devices that are conimonly used in a computer are: Input Devices: Keyboard, Mouse, Joystick, Scanuics cic Output Devices: Monitor, Printer etc. _ Input — Output Interface Units: VO interface units are special hardware components that Tie between the /O devices and the processor bus. These des communication links, between the CPU and the peripherais, actually siserving an ef synchronize and supervise ie. control all input and output tansfers. Need of Interface Units: Certain differences between the characteristics (functional and behavioral) of the peripherals and the ‘CPU (and also memory) exist. Interface Units are needed to resolve the differences, which are: 1. Operations of the peripherals, which are either electromagnetic or electromechanical devices. are different from that of the CPU and memory, which are generally electronic devices. So a signal conversion between the two is required and is done hy the interface unit between them, 2. The interface unit has to synchronize the data transfer mechanism between the slow peripherals and the fast CPU, Totes face units handle the differences between the data codes and formats in peripherals and the CPU or memory word formats. Working mechanism of Interface Units: Bach of the VO devices has their own in erface unit. The LO devices have got their own identifying addresses also, with which the CPU identifies an /O device. in order to communicate with, an VO device, the CPU places the address of that VO device in the address bus and places the appropriate control command in the conttol bus. The VO bus from the processor is attached to all Peripherals ia the reapeetive peripheral interfaces. Te address ftom the processor 1s received Fy all the interfaces, jacls oi them decodes the address. Only that particular interface which detects its own address activ ates the path between the bus lines and the device that it controls, All other VO device whose address dose not match with the address provided by the CPU. are not activated by their respective inter!ated /O and Memory Mapped UO In.a computer system, the CPU communicates with the memory unit as well as with the /O devices via buses. Generally there are three ways that computer buses ean be used to serve as a communicating link ‘sven the CPU, memory and the UO deviees. 1 CPU communicates with the memory and the VO devices via evo separate buses, the memory bus (for memory units) and I/O bus (for the VO devices). 2, CPU communicates with the memory and 1/0 units via one common bus (address and data fines) but uses two different pairs of control lines (one for memory and another for 1/0), 3. CPU uses a completely common bus for both memory and VO units [solated I/O or /O mapped VO: Tn this mechanism, CPU communicates with the memony and VO units via one commen bus (with same address and data lines) having two differ pais of contral lines (separate read and write tines for memory and 1/0). This differentiates between memory mu /O wansfere: ‘While communicating, the CPU specifies whether the address on the address lines is meant for memory or for an 11 device by enabling the either the memory control lies (memory read or write tine) o1 the VO eontrol lines (VO read or write Tine). So during @ memory transfer, either of the memory read and memory write lines are enabled wil during an V/O transfer, either of the 1/0 read and VO write lines are enabled. This configuration 1solates all YO deklco addresses from the memory addresses i.e. in this rpechanism; CPU treats the VO addresses separately fiom the memory addresses, Each has its own separate address spaces. Henee this mechanism is known as isolated /O method. Bessy Mapped 10: Of tr metnory Mapped DO method, same address space is used for both memory and VO auldicsses. In such configuration, CPU communicates with the memory and VO devices via the same bus sion between memory and VO addresses and having completely common lines. Here there is no dist the assigned adatess spaces’ for the VO registers are nesnmed to be part of the memory system. Though the assignéd HO addresses are Kept in the memory itself, however they ean not be used to store any memory words. Hence the total storate capacity ofthe memory is reducedIsolated VO Memory Mapped VO J} common address and data lines but distinct it of control lines is there for memory and 0 ‘ommunications with the CPU, ig memory nd /O devices. 1. Completely common address. data and control lines for both memory and [/O communications with the CPU. "2. No separate instructions for VO units CPU uses the same instructions for handling memory and /O devices, ~ Memory and 1/O address spaces are different. Memory address range or space available is more, 3. Memory and VO address spaces are the same. WO addresses are reside in the memory unit 4. Due to mapping of V/O° addresses in the memory, | the available memory address range or space ts reduced. “Number of instructions needed in such computers is nore, as separate memory and I/O instructions are weeded, 5. Number of instructions needed in such computers is less, as same instructions can be used for handling ‘memory and {/0 data,