LAB 2

FIRNA FRILANISA / 175060307111004

2-1. Output 4-bit binary input onto one LED (most significant bit) and the right most 7-
segment display (least significant digit) after converting them into two-digit decimal
equivalent (BCD). Use only dataflow modeling.

Structural Model :
Desain :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lab2_1 is
Port ( v : in STD_LOGIC_VECTOR (3 downto 0);
z : out STD_LOGIC;
s : out STD_LOGIC_VECTOR (6 downto 0));
end lab2_1;

architecture Structural of lab2_1 is

component comparator
Port ( v : in STD_LOGIC_VECTOR (3 downto 0);
z : out STD_LOGIC );
end component comparator;

component circuitA
Port ( v : in STD_LOGIC_VECTOR (2 downto 0);
a : out STD_LOGIC_VECTOR (2 downto 0) );
end component circuitA;
signal p : std_logic_vector (2 downto 0);

component tugas2_1
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
s : in STD_LOGIC;
m : out STD_LOGIC );
end component tugas2_1;
signal m : std_logic_vector (3 downto 0);
signal q : std_logic;

component tugas5_2
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
an : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0));
 end component tugas5_2;

begin
z <= q;
komparator : comparator port map (
v => v,
z => q );

sirkuit : circuitA port map (

v => v (2 downto 0),
a => p (2 downto 0) );

mux0 : tugas2_1 port map (

x => v(0),
y => p(0),
s => q,
m => m(0) );

mux1 : tugas2_1 port map (

x => v(1),
y => p(1),
s => q,
m => m(1) );

mux2 : tugas2_1 port map (

x => v(2),
y => p(2),
s => q,
m => m(2) );

mux3 : tugas2_1 port map (

x => v(3),
y => '0',
s => q,
m => m(3) );

sevseg : tugas5_2 port map (

x => m (3 downto 0),
an => "1110",
seg => s );

end Structural;

Testbench :
 LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb_lab2_1 IS
END tb_lab2_1;

ARCHITECTURE behavior OF tb_lab2_1 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT lab2_1
PORT(
v : IN std_logic_vector(3 downto 0);
z : OUT std_logic;
s : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;

--Inputs
signal v : std_logic_vector(3 downto 0) := (others => '0');

--Outputs
signal z : std_logic;
signal s : std_logic_vector(6 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: lab2_1 PORT MAP (
v => v,
z => z,
s => s
);

-- Stimulus process
stim_proc: process
begin
 v <= "0000";
wait for 50 ns;
v <= "0001";
wait for 50 ns;
v <= "0010";
wait for 50 ns;
v <= "0011";
wait for 50 ns;
v <= "0100";
wait for 50 ns;
v <= "0101";
wait for 50 ns;
v <= "0110";
wait for 50 ns;
v <= "0111";
wait for 50 ns;
v <= "1000";
wait for 50 ns;
v <= "1001";
wait for 50 ns;
v <= "1010";
wait for 50 ns;
v <= "1011";
wait for 50 ns;
v <= "1100";
wait for 50 ns;
v <= "1101";
wait for 50 ns;
v <= "1110";
wait for 50 ns;
v <= "1111";
wait for 50 ns;

end process;

END;

Simulasi
2-2. Model a 2-out-of-5 binary code and display a 4-bit binary coded decimal input
number onto five LEDs. Use dataflow modeling.

Dataflow Model
Desain :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lab2_2 is
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (4 downto 0));
end lab2_2;

architecture Dataflow of lab2_2 is

begin

y(0) <= ((not x(3)) and x(2) and (not x(1))) or (x(3) and x(2) and x(1));
y(1) <= ((not x(3)) and (not x(2)) and x(1) and x(0)) or ((not x(3)) and x(2) and x(1) and
(not x(0))) or (x(3) and x(2) and (not x(1)) and x(0));
y(2) <= ((not x(3)) and (not x(2)) and x(1) and x(0)) or ((not x(3)) and x(2) and x(1) and
x(0)) or (x(3) and x(2) and (not x(1)) and (not x(0)));
y(3) <= ((not x(3)) and (not x(2)) and (not x(1)) and x(0)) or (x(3) and (not x(2)) and
(not x(1)) and (not x(0))) or (x(3) and (not x(2)) and x(1) and x(0));
y(4) <= ((not x(3)) and (not x(2)) and (not x(1)) and (not x(0))) or (x(3) and (not x(2))
and (not x(1)) and x(0)) or (x(3) and (not x(2)) and x(1) and (not x(0)));

end Dataflow;
Testbench :

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_lab2_2 IS
END tb_lab2_2;

ARCHITECTURE behavior OF tb_lab2_2 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT lab2_2
PORT(
x : IN std_logic_vector(3 downto 0);
y : OUT std_logic_vector(4 downto 0)
);
END COMPONENT;

--Inputs
signal x : std_logic_vector(3 downto 0) := (others => '0');

--Outputs
signal y : std_logic_vector(4 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: lab2_2 PORT MAP (
x => x,
y => y
);

-- Stimulus process
stim_proc: process
begin

x <= "0000";
 wait for 50 ns;
x <= "0001";
wait for 50 ns;
x <= "0010";
wait for 50 ns;
x <= "0011";
wait for 50 ns;
x <= "0100";
wait for 50 ns;
x <= "0101";
wait for 50 ns;
x <= "0110";
wait for 50 ns;
x <= "0111";
wait for 50 ns;
x <= "1000";
wait for 50 ns;
x <= "1001";
wait for 50 ns;
x <= "1010";
wait for 50 ns;
x <= "1011";
wait for 50 ns;
x <= "1100";
wait for 50 ns;
x <= "1101";
wait for 50 ns;
x <= "1110";
wait for 50 ns;
x <= "1111";
wait for 50 ns;

end process;

END;

Simulasi
3-1. Create a 4-bit ripple carry adder using dataflow modeling.

Structural Model
Desain :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lab3_1 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end lab3_1;

architecture Structural of laB3_1 is

component FullAdder_1bit is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
s : out STD_LOGIC;
cout : out STD_LOGIC
);
end component FullAdder_1bit;

signal c1,c2,c3 : STD_LOGIC;

begin

FA1 : FullAdder_1bit port map(

 a => a(0),
b => b(0),
cin => cin,
s => s(0),
cout => c1
);

FA2 : FullAdder_1bit port map(

a => a(1),
b => b(1),
cin => c1,
s => s(1),
cout => c2
);

FA3 : FullAdder_1bit port map(

a => a(2),
b => b(2),
cin => c2,
s => s(2),
cout => c3
);

FA4 : FullAdder_1bit port map(

a => a(3),
b => b(3),
cin => c3,
s => s(3),
cout => cout
);

end Structural;

Testbench :

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_lab3_1 IS
END tb_lab3_1;

ARCHITECTURE behavior OF tb_lab3_1 IS

 COMPONENT lab3_1
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
cin : IN std_logic;
s : OUT std_logic_vector(3 downto 0);
cout : OUT std_logic
);
END COMPONENT;

--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
signal cin : std_logic := '0';

--Outputs
signal s : std_logic_vector(3 downto 0);
signal cout : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: lab3_1 PORT MAP (
a => a,
b => b,
cin => cin,
s => s,
cout => cout
);

-- Stimulus process
stim_proc: process
begin

a <= "0000";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "0001";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "0010";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "0010";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "0100";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "1000";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "0000";
b <= "0001";
cin <= '0';
wait for 50 ns;

a <= "0001";
b <= "0001";
cin <= '0';
wait for 50 ns;

a <= "0010";
b <= "0001";
cin <= '0';
wait for 50 ns;

a <= "0100";
b <= "0001";
 cin <= '0';
wait for 50 ns;

a <= "1000";
b <= "0001";
cin <= '0';
wait for 50 ns;

a <= "0000";
b <= "0010";
cin <= '0';
wait for 50 ns;

a <= "0001";
b <= "0010";
cin <= '0';
wait for 50 ns;

end process;

END;

Simulasi

3-2. Modify the design of 3-1 by treating the 4-bit input as BCD, performing addition,
generating result in BCD, and displaying it on LED0 and right most 7-segment display.
Use switches to input two 4-bit BCD input and BTNU for carry-in. Reuse models
developed in 2-1 and 3-1 as needed. Use dataflow modeling.

Dataflow Model
Desain :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity lab3_2 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
s : inout STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC;
z : out STD_LOGIC;
seg : out STD_LOGIC_VECTOR (6 downto 0));
end lab3_2;

architecture Structural of lab3_2 is

component lab3_1 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC
);
end component lab3_1;

component lab2_1 is
Port ( v : in STD_LOGIC_VECTOR (3 downto 0);
z : out STD_LOGIC;
s : out STD_LOGIC_VECTOR (6 downto 0)
);
end component lab2_1;

begin

FA_4bit : lab3_1 port map (

a => a,
b => b,
cin => cin,
s => s,
cout => cout );

BCD : lab2_1 port map (

v => s,
z => z,
s => seg );

end Structural;
Testbench :

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_lab3_2 IS
END tb_lab3_2;

ARCHITECTURE behavior OF tb_lab3_2 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT lab3_2
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
cin : IN std_logic;
s : INOUT std_logic_vector(3 downto 0);
cout : OUT std_logic;
z : OUT std_logic;
seg : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;

--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
signal cin : std_logic := '0';

--BiDirs
signal s : std_logic_vector(3 downto 0);

--Outputs
signal cout : std_logic;
signal z : std_logic;
signal seg : std_logic_vector(6 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: lab3_2 PORT MAP (
a => a,
b => b,
cin => cin,
s => s,
cout => cout,
z => z,
seg => seg
);

-- Stimulus process
stim_proc: process
begin

a <= "0000";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "0001";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "0010";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "0010";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "0100";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "1000";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "0000";
b <= "0001";
cin <= '0';
wait for 50 ns;

a <= "0001";
b <= "0001";
cin <= '0';
wait for 50 ns;

a <= "0010";
b <= "0001";
cin <= '0';
wait for 50 ns;

a <= "0100";
b <= "0001";
cin <= '0';
wait for 50 ns;

a <= "1000";
b <= "0001";
cin <= '0';
wait for 50 ns;

a <= "0000";
b <= "0010";
cin <= '0';
wait for 50 ns;

a <= "0001";
b <= "0010";
cin <= '0';
wait for 50 ns;

a <= "0010";
b <= "0010";
cin <= '0';
wait for 50 ns;

a <= "0100";
b <= "0010";
 cin <= '0';
wait for 50 ns;

end process;

END;

Simulasi

4-1. Create a carry-look ahead adder circuit by modifying the project of 3-1 and using dataflow
modeling.

Dataflow Model
Desain :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lab4_1 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end lab4_1;

architecture Structural of lab4_1 is

component FullAdder_1bit is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
s : out STD_LOGIC;
 cout : out STD_LOGIC
);
end component FullAdder_1bit;

component CarryLookAhead is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC);
end component CarryLookAhead;

signal c1,c2,c3 : STD_LOGIC;

begin

FA1 : FullAdder_1bit port map(

a => a(0),
b => b(0),
cin => cin,
s => s(0)
);

CLA1 : CarryLookAhead port map (

a => a(0),
b => b(0),
cin => cin,
cout => c1
);

FA2 : FullAdder_1bit port map(

a => a(1),
b => b(1),
cin => c1,
s => s(1)
);

CLA2 : CarryLookAhead port map (

a => a(1),
b => b(1),
cin => c1,
cout => c2
);

FA3 : FullAdder_1bit port map(

 a => a(2),
b => b(2),
cin => c2,
s => s(2)
);

CLA3 : CarryLookAhead port map (

a => a(2),
b => b(2),
cin => c2,
cout => c3
);

FA4 : FullAdder_1bit port map(

a => a(3),
b => b(3),
cin => c3,
s => s(3)
);
CLA4 : CarryLookAhead port map (
a => a(3),
b => b(3),
cin => c3,
cout => cout
);

end Structural;

Testbench :

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_lab4_1 IS
END tb_lab4_1;

ARCHITECTURE behavior OF tb_lab4_1 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT lab4_1
PORT(
 a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
cin : IN std_logic;
s : OUT std_logic_vector(3 downto 0);
cout : OUT std_logic
);
END COMPONENT;

--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
signal cin : std_logic := '0';

--Outputs
signal s : std_logic_vector(3 downto 0);
signal cout : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: lab4_1 PORT MAP (
a => a,
b => b,
cin => cin,
s => s,
cout => cout
);

-- Stimulus process
stim_proc: process
begin

a <= "0000";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "0001";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "0010";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "0010";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "0100";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "1000";
b <= "0000";
cin <= '0';
wait for 50 ns;

a <= "0000";
b <= "0001";
cin <= '0';
wait for 50 ns;

a <= "0010";
b <= "0100";
cin <= '1';
wait for 50 ns;

a <= "0100";
b <= "0100";
cin <= '1';
wait for 50 ns;

a <= "1000";
b <= "0100";
cin <= '1';
wait for 50 ns;
 a <= "0000";
b <= "1000";
cin <= '1';
wait for 50 ns;

a <= "0001";
b <= "1000";
cin <= '1';
wait for 50 ns;

a <= "0010";
b <= "1000";
cin <= '1';
wait for 50 ns;

a <= "0100";
b <= "1000";
cin <= '1';
wait for 50 ns;

a <= "1000";
b <= "1000";
cin <= '1';
wait for 50 ns;

a <= "1111";
b <= "1111";
cin <= '1';
wait for 50 ns;

end process;

END;

Simulasi