Major Documentation On

Novel High speed Vedic Multiplier proposal incorporating Adder based on
Quaternary Signed Digit number system
CHAPTER 1
INTRODUCTION
The challenge of the verifying a large design is growing exponentially. There
is a need to define new methods that makes functional verification easy. Several
strategies in the recent years have been proposed to achieve good functional
verification with less effort. Recent advancement towards this goal is methodologies.
The methodology defines a skeleton over which one can add flesh and skin to their
requirements to achieve functional verification.
Complex multiplication is of immense importance in Digital Signal Processing

(DSP) and Image Processing (IP). To implement the hardware module of Discrete
Fourier Transformation (DFT), Discrete Cosine Transformation (DCT), Discrete Sine
Transformation (DST) and modem broadband communications; large numbers of
complex multipliers are required. Complex number multiplication is performed using
four real number multiplications and two additions/ subtractions. In real number
processing, carry needs to be propagated from the least significant bit (LSB) to the
most significant bit (MSB) when binary partial products are added. Therefore, the
addition and subtraction after binary multiplications limit the overall speed. Many
alternative method had so far been proposed for complex number multiplication like
algebraic transformation based implementation, bit-serial multiplication using offset
binary and distributed arithmetic , the CORDIC (coordinate rotation digital computer)
algorithm , the quadratic residue number system (QRNS) , and recently, the redundant
complex number system (RCNS). Blahut et. al proposed a technique for complex
number multiplication, where the algebraic transformation was used. This algebraic
transformation saves one real multiplication, at the expense of three additions as
compared to the direct method implementation. A left to right array for the fast
multiplication has been reported in 2005, and the method is not further extended for
complex multiplication. But, all the above techniques require either large overhead for
pre/post processing or long latency. Further many design issues like as speed,
accuracy, design overhead, power consumption etc., should not be addressed for fast
multiplication . In algorithmic and structural levels, a lot of multiplication techniques
had been developed to enhance the efficiency of the multiplier; which encounters the
reduction of the partial products and/or the methods for their partial products addition,
but the principle behind multiplication was same in all cases. Vedic Mathematics is
1 Dept. of ECE, SDES

the ancient system of Indian mathematics which has a unique technique of

calculations based on 16 Sutras (Formulae). "Urdhva-tiryakbyham" is a Sanskrit word
means vertically and crosswise formula is used for smaller number multiplication.
"Nikhilam Navatascaramam Dasatah" also a Sanskrit term indicating "all from 9 and
last from 10", formula is used for large number multiplication and subtraction. All
these formulas are adopted from ancient Indian Vedic Mathematics. In this work we
formulate this mathematics for designing the complex multiplier architecture in
transistor level with two clear goals in mind such as: i) Simplicity and modularity
multiplications for VLSI implementations and ii) The elimination of carry
propagation for rapid additions and subtractions. Mehta et al. have been proposed a
multiplier design using "Urdhva-tiryakbyham" sutras, which was adopted from the
Vedas. The formulation using this sutra is similar to the modem array multiplication,
which also indicating the carry propagation issues. A multiplier design using
"Nikhilam Navatascaramam Dasatah" sutras has been reported by Tiwari et. al in
2009, but he has not implemented the hardware module for multiplication.
Multiplier implementation in the gate level (FPGA) using Vedic Mathematics

has already been reported but to the best of our knowledge till date there is no report
on transistor level (ASIC) implementation of such complex multiplier. By employing
the Vedic mathematics, an N bit complex number multiplication was transformed into
four multiplications for real and imaginary terms of the final product. "Nikhilam.
Navatascaramam Dasatah" sutra is used for the multiplication purpose, with less
number of partial products generation, in comparison with array based multiplication.
When compared with existing methods such as the direct method or the strength
reduction technique, our approach resulted not only in simplified arithmetic
operations, but also in a regular array like structure. The multiplier is fully
parameterized, so any configuration of input and output word-lengths could be
elaborated. Transistor level implementation for performance parameters such as
propagation delay, dynamic leakage power and dynamic switching power
consumption calculation of the proposed method was calculated by spice spectre
using 90 nm standard CMOS technology and compared with the other design like
distributed arithmetic, parallel adder based implementation and algebraic
transformation based implementation. The calculated results revealed

(16,16)x(16,16) complex multiplier have propagation delay only 4 ns with 6.5 mW

dynamic switching power.
1.1 Why Vedic Mathematics
Many Indian Secondary School students consider Mathematics a very difficult
subject. Some students encounter difficulty with basic arithmetical operations. Some
students feel it difficult to manipulate symbols and balance equations. In other words,
abstract and logical reasoning is their hurdle. Many such difficulties in learning
Mathematics enter into a long list if prepared by an experienced teacher of
Mathematics. Volumes have been written on the diagnosis of 'learning difficulties'
related to Mathematics and remedial techniques.
Learning Mathematics is an unpleasant experience to some students mainly

because it involves mental exercise. Of late, a few teachers and scholars have revived
interest in Vedic Mathematics which was developed, as a system derived from Vedic
principles, by Swami Bharati Krishna Tirthaji in the early decades of the 20th century.
Dr. Narinder Puri of the Roorke University prepared teaching materials based on
Vedic Mathematics during 1986 - 89. A few of his opinions are stated hereunder:
i) Mathematics, derived from the Veda, provides one line, mental and superfast
methods along with quick cross checking systems.
ii) Vedic Mathematics converts a tedious subject into a playful and blissful one which
students learn with smiles.
iii) Vedic Mathematics offers a new and entirely different approach to the study of
Mathematics based on pattern recognition. It allows for constant expression of a
student's creativity, and is found to be easier to learn.
iv)In this system, for any problem, there is always one general technique applicable to
all cases and also a number of special pattern problems. The element of choice and
flexibility at each stage keeps the mind lively and alert to develop clarity of thought
and intuition, and thereby a holistic development of the human brain automatically
takes place.
v) Vedic Mathematics with its special features has the inbuilt potential to solve the
psychological problem of Mathematics - anxiety.

The Sanskrit word “Veda” means house of knowledge and this gift that the Indians
gave to the world, thousands of years ago and this knowledge is now currently
employed in our global silicon chip technology of engineering. Vedic mathematics is
used to solve the complex calculations involved in usual mathematics. This is so
because, the Vedic formula is claimed to be based on the natural principles on which
the human mind works, so typical to
the typical calculation that can be performed by a normal person, and hence Vedic
mathematic provides techniques to solve operations with a large magnitude number
easily. It consents to incorporate the arithmetic rules along with high speed and easy
implementation,
thereby viable for a range of applications based on computing. This is a very
interesting field and presents some effective algorithms which can be applied to
various branches of engineering such as computing and digital system
1.2 Vedic Mathematical Formulae

VEDIC MATHEMATICS is a mathematical elaboration of 'Sixteen Simple
Mathematical formulae from the Vedas' as brought out by Sri Bharati Krishna
Tirthaji.
In the text authored by the Swamiji, nowhere has the list of the Mathematical
formulae (Sutras) been given. But the Editor of the text has compiled the list of the
formulae from stray references in the text. The list so compiled contains Sixteen
Sutras and Thirteen Sub - Sutras as stated here under.
1. Ekadhikena Purvena – By one more than the previous one.
2. Nikhilam Navatascaramap Dasatah – All from 9 and last from 10.
3. Urdhva-Tiryagbhyam – Vertically and crosswise.
4. Paravartya Yojayet – Transpose and adjust.
5. Shunyam Samyasamuccaye – When the sum is the same that sum is zero.
6. (Anurupye) Shunyamanyat – If one is in ratio, the other is zero.
7. Sankalana-Vyavakalanabhyam – By addition and by subtraction.
8. Puranapuranabyham – By the completion or no completion.
9. Calana-Kalanabyham – Differences and Similarities.
10. Yaavadunam – Whatever the extent of its deficiency.
11. Vyastisamanstih – Part and Whole.

12. Sesanyankena Caramena – The remainders by the last digit.

13. Sopantyadvayamantyam – The ultimate and twice the penultimate.
14. Ekanyunena Purvena – By one less than the previous one.
15. Gunitasamuccayah – The product of the sum is equal to the sum of the product.
16. Gunakasamuccayah – The factors of the sum is equal to the sum of the factors.
In the text, the words Sutra, aphorism, formula is used synonymously. So are
also the words Upa-sutra, Sub-sutra, Sub-formula, corollary used. Now we shall have
the literal meaning, contextual meaning, process, different methods of application
along with examples for the Sutras. Explanation, methods, further short-cuts,
algebraic proof, etc follow. What follows relates to a single formula or a group of
formulae related to the methods of Vedic Mathematics.
1.3 Urdhva – tiryagbhyam
Urdhva-Tiryagbhyam sutras are the basic sutras which is applicable for all
case of multiplication. This itself is very short and compendious consisting of only
one combine word and means “vertically and crosswise” i.e. the first bit of
multiplicand and the first bit of multiplier are multiplied with vertically and crosswise
method. Vertically and crosswise multiplication procedure is also known as array
multiplication technique. Fig-1 represents the 6×6 multiplier using vertically and
crosswise method.
Urdhva – tiryagbhyam is the general formula applicable to all cases of multiplication
and also in the division of a large number by another large number.
Vedic multipliers are based on the principle Vedic Sutras. In Sanskrit word
terminology ‘Veda’ stands for ‘knowledge’. Vedic mathematics is believed to be
reinvestigated from Vedas by swami Sri Bharti Krishna Tirathaji between the years
1911 to 1918 . The Vedic mathematics has been portioned intosixteen different Sutras
which can be applied to any branch of math’s like algebra, trigonometry, geometry,
mensuration etc. Its methods reduce thecomplex calculations turns into simpler ones
because they are basically based on methods similar to working method of human
mind thereby making them easier. It has been observed that being coherent and
symmetrical; they consume much lesser power and use lower chip area. Designs
based on Vedic Sutra have been used in many applications like ALU, MAC etc. and
have shown better results

The multipliers have been proven as an essential component, while designing

microprocessors and other applications where the processing of a signal is in the
foreground. With the advent and improvements in VLSI technology that has enabled
the integration of transistors based on different technologies like CMOS, BICMOS
technologies, etc., the speed of computation has been increased dramatically.
To obtain the performance, parallel processing and pipelining techniques are

used to perform the various operations. High-speed processors and hence we require
high- speed multipliers. Since a processor depends on its multiplier, multiplication is
the key arithmetic procedurefor the improvement of fast processor. A reduction in
time delay along with power “VEDA” comprising an accumulation of knowledge at a
single platform. Further more, it exhibits 16 sutras that deal with several subdivisions
including arithmetic,algebra, geometry and so on. Jagadguru Swami Sri Bharati
Krishna Trithaji projected the concept of this ancient that became very popular to
achieve high-speed processing of the data. As arithmetic operations are very
important in the design of digital processors and application specific
circuits,arithmetic circuits form an important class of circuits in digital systems.
Multiplication is the scaling operation performed one number by another used
frequently invarious applications like convolution, Fast Fourier Transforms, Filters,
ALU of Processors, etc. Hence the development of fast and accurate multipliers is
necessary. ALU is an execution unit which not only performs the arithmetic
operation, but also logicalconsumption is the important requirement. The word
“VEDIC” is a consequential ofoperation and therefore ALU is called as a heart of
Microprocessor, Microcontroller, and CPUs.The organization of the paper

starts with a brief introduction and Section 1, proposes the steps approaching Vedic
methodology. Section 2, illustrates Vedic Wallace Multiplier. Section 3, illustrates the
designing of different multipliers based on the bit size, followed by aNxN Vedic
Wallace Multiplier in Section 4. Furthermore, Section 5 focuses on the realization of
the Vedic Wallace Multiplier unit in XilinxISE 14.5. Section 6 comprises the design
of ALU, whereas an in-depth discussion of the important outcomes is included .

1.4 Multiplication of Two Decimal Numbers
To illustrate this scheme, let us consider the multiplication of two decimal

numbers 252x846 by Urdhva-Tiryakbhyam method as shown in Figure 1. The digits
on both sides of the line are multiplied and added with the carry from the previous
step. This generates one of the bits of the result and a carry. This carry is added in the
next step and hence the process goes on. If more than one line is there in one step, all
the results are added to the previous carry. In each step, least significant bit acts as the
result bit and all other bits act as carry for the next step. Initially, the carry is taken to
be zero

CHAPTER 2
LITERATURE SURVEY
1. Preyesh Dalmia et al (2018): One of the primary features that help us

determine the computational power of a processor is the speed of its
arithmetic unit. An important function of an arithmetic block is multiplication
because, in most mathematical computations, it forms the bulk of the
execution time. Thus, the development of a fast multiplier has been a key
research area for a long time. The UT sutra is an ancient Vedic Mathematics
sutra that can be used for multiplication of two numbers in any number
system. It is based on “Vertical and Crosswise” multiplication.
2. Sushma R. et al (2013): With the advent of new technology in the fields
of VLSI and communication, there is also an ever growing demand for high
speed processing and low area design. It is also a well-known fact that the
multiplier unit forms an integral part of processor design. Due to this regard,
high speed multiplier architectures become the need of the day. We introduce
a novel architecture to perform high speed multiplication using ancient Vedic
maths techniques. A new high speed approach utilizing 4:2 compressors and
novel 7:2 compressors for addition has also been incorporated in the same and
has been explored. Upon comparison, the compressor based multiplier
introduced is almost two times faster than the popular methods of
multiplication.
3. Karanam Deepak et al (2019): This present work deals with a
reversible Vedic type multiplier using the earliest Urdhva Tiryagbhyam sutras
of Vedic type mathematics combine with the QSD adder (Quaternary Signed
digit number adder). The proposed multiplier configuration is contrasted and
a reversible Vedic multiplier consolidates a QSD Quaternary Signed digit
number adder viper among a transformation section for quaternary to paired
change. The proposition demonstrates a most extreme speed enhancement.
4. G.Sameer et al (2015): With the advent of new technology in the fields
of VLSI and communication, there is also an ever growing demand for high
speed processing and low area design. It is also a well-known fact that the
multiplier unit forms an integral part of processor design. Due to this regard,
high speed multiplier architectures become the need of the day. In this paper,
we introduce a novel architecture to perform high speed multiplication using
ancient Vedic math’s techniques. A new high speed approach utilizing 4:2
compressors and novel 7:2 compressors for addition has also been
incorporated in the same and has been explored. Upon comparison, the
compressor based multiplier introduced in this paper, is almost two times
faster than the popular methods of multiplication.

5. T. Amy Prasanna et al (2019): The rapid Vedic multiplier dependent

on the Urdhva Tiryagbhyam sutra of Vedic science that consolidates a novel
viper dependent on Quaternary Marked digit number framework. Three tasks
are inalienable in augmentation: fractional items age, incomplete items
decrease and expansion. A quick viper engineering subsequently significantly
upgrades the speed of the general procedure. A Quaternary rationale viper
design is recommended that chips away at a half breed of parallel and
quaternary number frameworks.
6. Ankit trivedi et al (2017): Multipliers are the most important unit in
high speed arithmetic logic units, multiplier and accumulate units, digital
signal processing units. etc. To increase speed many adjustments over the
standard modified booth algorithm, many new techniques are being comes
work in action. Amongst these various multiplier Vedic multipliers based on
Vedic mathematics are currently under focus due to these being one of the
super fastest and low power multiplier. There are sixteen basic sutras in Vedic
multiplication in which “Urdhva Tiryakbhyam” has been found to be the most
feasible one in terms of speed.
7. Ila Chaudhary et al (2016): Rapidly growing technology has raised
demands for fast and efficient real time digital signal processing applications.
Multiplication is one of the primary arithmetic operations every application
demands. A large number of multiplier designs have been developed to
enhance their speed. Active research over decades has lead to the emergence
of Vedic Multipliers as one of the fastest and low power multiplier over
traditional array and booth multipliers.
8. Poornima M et al (2013): Vedic mathematics is the name given to the
ancient
Indian system of mathematics that was rediscovered in the early twentieth
century from ancient Indian sculptures (Vedas). Vedic Mathematics has a
unique technique of calculations based on 16 Sutras. It is the study of high
speed 8x8 bit Vedic multiplier architecture which is quite different from the
Conventional method of multiplication like add and shift. Further, the Verilog
HDL coding of Urdhva Tiryakbhyam Sutra for 8x8 bits multiplication and
their FPGA implementation by Xilinx Synthesis Tool on Spartan 3 kit have
been done and output has been displayed on LED’s of Spartan 3 kit.
9. Harsha R et al (2019): The multiplier is a key building block of all
processors, which improves the speed of Digital Signal Processor (DSP), a
special application in which we need to reduce the time delay. In the proposed
method, we design a Vedic multiplier by using a Vedic Mathematics Sutra
called Urdhva Tiryagbhyam, which means “vertically and crosswise”. Vedic
Mathematics is mainly based on 16 Sutras and was rediscovered in the early
20th century. In ancient times in India, people used this Sutra for decimal
number multiplications effectively. The same basic concept of the above-
mentioned Sutra is extended to the multiplication of binary numbers to make

use in the digital hardware system. The computation of partial products in

parallel in the Urdhva Tiryagbhyam Sutra increases the speed of the
computation process and the processing time is reduced in comparison with
the use of inbuilt MATLAB functions. In our proposed multiplier design, the
delay for the 4X4 Vedic multiplier is reduced and also the number of
transistors is reduced by a large amount compared to the previously proposed
design.
10. Nagamani a.n. et al (2011): Arithmetic operations in digital signal
processing applications suffer from problems including propagation delay and
circuit complexity. QSD number representation allows a method of fast
addition/subtraction because the carry propagation chains are eliminated and
hence it reduces the propagation time in comparison with common radix 2
system. Here we propose an Arithmetic unit based on QSD number system
based on quaternary system. The proposed design is developed using VHDL
and implemented on FPGA device and results are compared with
conventional arithmetic unit. The implementation of quaternary addition and
multiplication results in a fix delay independent of the number of digits.
Operations on a large number of digits such as 64, 128, or more, can be
implemented with constant delay and less complexity
This sector discusses the effort done by researchers on submissions of Vedic

mathematics. The judgment between conventional and Vedic mathematics realized in
VLSI for RSA algorithm, ALU, curve encryption etc. with respect to effectiveness
analysis and complexity has been offered in. It displays that Vedic mathematical
method is fast and modest. 'Urdhva Tiryagbhyam Sutra' and ‘Nikhilam Sutra'
multiplication methods are planned in . 16 X 16 multiplier by “Urdhva Tiryagbhyam
Sutra” is offered and prolonged by using 'Nikhilam Sutra' 16X16 multiplier modules
practices two 8x8 modules, one 16 bit carry save adder and two 17 bit full adder
stages are realized here. The carry save adder raises the speed of addition of partial
products.
The multiplier is realized in SPARTAN 2 FPGA Device XC2S30-5pq208.
The presented technique shows speed enhancements in . The ‘Urdhva Tiryagbhyam
Sutra' plus 'Nikhilam Sutra' multiplication methods are establish to be speedy when
magnitude of together operands are extra than partial of their extreme values. A
floating point multiplier through 24X24 bit integer multiplication operation is
accessible using ‘Urdhva Tiryagbhyam Sutra' algorithm, improvement in speed ,
proficiency and power has been establish by this sutra. In this the 24 X 24
multiplication structural design is split to four 12 X 12 bit multiplication modules.

The 12 X 12 modules are realized by 4X4 bit multiplier modules. The projected
method shows advantages similar power saving, configurability, self-reparability etc.
The method can be extended for DFT . A low power Multiplier is offered in . The
realized multiplier is based on the ancient Vedic Multiplication Method. At this point
the 'Urdhva tiryakbhyam sutra’ and 'Nikhilam sutras’ are used for multiplication. The
multiplier founded on this technique is equated with the modern multiplier to
highpoint the power and speed rewards in the Vedic Multipliers. To check the Vedic
multiplier BIST (Built inSelf-Test) is realized and it is establish Fault free. The
outcomes are compared with the Booth's Multiplier in terms of constraints like power
and time delay. The multiplier is realized using VHDL and Spartan 2G FPGA. The
simulation outcomes are offered based on power and time delay. Reference offerings
a squarer based high enactment multiplier for which Vedic multipliers and two
flexible constant coefficient multipliers are castoff. Outcomes are stored in ROM
which rises power consumption. The arrangement proposed in attains increased speed
and compact area as equated to array multipliers. Conferring to authors its only
drawback is increment in dynamic power. According to multiplier is very essential
part of any processor and needs more hardware resources and handing out time than
subtractors and adders.
The 8.72 percentages of instructions of every processor are multiplication centered
and substantial amount of time is spent on this process by any CPU. A relative study
of diverse multipliers with respect to low power requirement and high speed is
accessible in by using ‘Urdhva tiryakbhyam’ algorithm, it like wise proposes to use
'Nikhilam sutras' for least iterations. Array multiplier, Wallace multiplier and Booth
multiplier are equated and Vedic mathematical procedures are used in all. The results
displayed that Booth multiplier is superior in aspects like speed, delay, area,
complication and power consumption. Array Multiplier needs more power
consumption and gives optimal number of components; the delay for this multiplier is
larger than Wallace Tree Multiplier. 'Nikhilam sutras’ needs less number of iterations
to perform multiplication. 'Nikhilam sutras' establish to be less complex as compared
with 'Urdhva tiryakbhyam' algorithm. Additional work can be carried out to
minimalize delay and to advance the speed. The efficacy comparison between
Karatsuba multiplier by polynomial multiplication with multiplier realizing 'Nikhilam
Sutras’ have been offered in which states that Karatsuba multiplier displays speed

improvement as equated to Vedic multiplier. Animproved ‘Urdhva tiryakbhyam'

algoriothm has been realized on new multiplier for low power, high speed uses. The
new algorithm creates concurrent carry for succeeding stage which is built on
generation and addition of coexisting partial sums formed within matrix architecture .
A MAC unit built on ‘Urdhva tiryakbhyam’ algoriothm has beenrealized on FPGA
in .
In this the multiply accumulate unit calculates product of two numbers and
sum the product to accumulator. MAC unit contains of multiplier, adder and
accumulator register to store the outcome. Conferring to authors the 16X16 and
32X32 bit MAC modules display improved speed which may be castoff in DSP
applications. it can be agreed that FFT is an algorithm which computes N point DFT,
FFT execution needs large number of multiplications which are very compound and
time consuming. Such problems can be resolved by implementing multipliersby
means of Vedic mathematical actions. ‘Urdhva tiryakbhyam’algorithm is reflected to
be the best method for speedy multiplication. Vedic FFT is superior in features like
speed, simplicity, delay, area, power consumption etc. But for huge numbers it
agonizes from high carry propagation delay.
Vedic multiplier with high speed and lesser area 'Urdhava Triyakbhyam’
algorithm of early Indian Vedic Mathematics is employed to improve its efficiency. It
contains of 4x4 bit multiplication operation which is split in reconfigurable FFT
modules. Here the 4x4 multiplication process units are executed using small 2x2 bit
multipliers. Re-configurability at real time has been delivered for power saving. The
re-configurable FFT has been intended and implemented on an FPGA based system
which displays high speed and small area as equated to the conventional FFT. FFT is
very beneficial in Digital Signal Processing which is measured to be difficult to
implement. Vedic mathematics is a practice based on 16 sutras which lessens
complexity, completing time, area, power etc. By using ‘Urdhava Triyakbhyam’
algorithm reconfigurable FFT plan is proposed here. There is a requirement to find
new algorithms to advance the speed .
Vedic algorithm for the execution of multipliers to be used in the FFT.
Conferring to authors the conventional multiplication method needs more time & area
on silicon than Vedic algorithms which aids to speed up the signal processing task.
offerings an efficient method for multiplying two binary numbers using limited power

and time. The work emphases on speed upgrading of multiplication operation of

multipliers, by decreasing the number of bits using Vedic mathematics. The planned
algorithm is modeled using Verilog. It was found that for 3.3 V supply voltage, the 4
bit multiplier dispels a power of 47.35 mW. The transmission delay of the architecture
was set up to be 6.63 ns which displayedupgrading in power dissipation and speed.
Raise the ability of the processors and to holder complex processes large number of
processor cores is realized on chip. This creates load over processors which can be
concentrated by assigning tasks to coprocessors. Conferring to authors ALU speed
rest on upon multipliers, if multipliers are executed using Urdhva Tiryagbhyam,
various NxN multipliers have been planned. project presents judgment between
employment of normal multiplication and Vedic multiplication spending ‘Urdhva
Tiryakbhyam Sutra’ on hardware. It requisite same number of multiplication and
addition actions. All multipliers have been tried for 16 X 16 multiplications for
comparison. Test vectors have been given over and done with a text file. Designed
multipliers were realized on Xilinx FPGA platform and Virtex XCV 300-6PQ240.
Various multiplier employments have been tested and equated for optimum area and
speed. It shows that the approaches adopted by using Vedic mathematics is very
influential regarding speed, low Power dissipation, area on silicon etc.
Digital Signal Processing (DSP) operations are very important part of
engineering as well as medical discipline. Designing of DSP operations have many
approaches. For the designing of DSP operations, multiplication is play important role
to perform signal processing operations such as Convolution and Correlation. The
new approach of this implementation is mentally and easy to calculate of DSP
operations for small length of sequences. In this paper a fast method for DSP
operations based on ancient Vedic mathematics is contemplated.
The implementation of high speed DSP operations of two finite length
sequences using Vedic Urdhava-Triyagbhayam Multiplication Sutra
(approach/method) is done. Urdhava-Triyagbhayam Sutra is very efficient
multiplication formula applicable for all types of multiplication.

CHAPTER 3
EXISTING METHODS
3.1 Vedic Wallace Multiplier

In general, Wallace tree addition uses full adders to extensively reduce the
partial products.
Figure 3.1 Multiplication of Two Decimal Numbers: 252x846
When the critical path is compared between the critical path in 4 bit conventional and
Vedic multiplier, for a 4-bit multiplier, 4 partial products will be generated and are
named as p0 to p3. For Wallace tree multiplier, a 3:2 reduction is used, so that the

partial products are reduced from 4 to 3. The Delay in critical path is given by the
addition of 3 full adder sums, 2 full adder carry, and half adder carry. The critical path
for Vedic mathematics as shown in Figure 3, is given by 2FAS is reduced by 3HAS
and in terms of XOR gates, Vedic-Wallace uses 3XOR gates instead of 4XOR i.e.,
less carry propagation delay than the conventional method. Hence, Vedic-Wallace has
a variable improvement over design ware depending upon the number of bits in
multiplication.
Figure 3.2 4x4 Multiplier using Wallace Tree

Figure 3.3 4x4 Multiplier using Vedic Reduction
3.2 Different Multiplier Architectures

The hardware architecture of 2x2, 4x4, 8x8, 16x16, 32x32 bit Vedic Wallace
multiplier (VW) modules are displayed in below sections. Here, “Urdhva-
Tiryakbhyam” (Vertically and crosswise) sutra is used to propose such an architecture
for the multiplication of two binary numbers. The beauty of Vedic Wallace multiplier
is that, here partial product generation and additions are done concurrently. Hence, it
is a well-adapted parallel processing. The features make it more attractive for binary
multiplications. This reduces delay and this is the primary motivation behind this
work.
3.3 Vedic Wallace Multiplier for 2x2 Bit Module
The method is explained for two, 2-bit numbers A and B where A=aa and
B=bb as shown in Figure 4. Firstly, the 1 0 1 0 least significant bits are multiplied
which gives the least significant bit of the final product (Vertical). Then, the LSB of

the multiplicand is multiplied with the next higher bit of the multiplier and added to,
the product of LSB of the multiplier and the next higher bit of the multiplicand
(crosswise). The sum gives the second bit of the final product and the carry is added
to the partial product obtained by multiplying the most significant bits to give the sum
and carry. The sum is the third corresponding bit and the carry becomes the fourth bit
of the final product.
s0=a0b0 (1)
c1s1=a1b0+a0b1 (2)
c2s2=c1+a1b1 (3)
The final result will be c2s2s1s0. This multiplication method is applicable for all the
cases. The 2x2 bit Vedic Wallace multiplier is implemented by using four input AND
gates along with two half-adders. In the same way, 4, 8, 16, 32 and N bit multipliers
are designed with a little modification.
3.4 Vedic Wallace Multiplier for 4x4 Bit Module
The 4x4 bit Vedic Wallace multiplication unit is further realized by
incorporating four similar modules of 2x2 multipliers. The processing in the form of a
block diagram is depicted in Figure 4 for the 4x4 multiplier.
3.4.1 Vedic Wallace Multiplier for 8x8 Bit Module
The 8x8 Vedic Wallace Multiplier modules are realized using four 4x4
multiplier modules. The processing of 8x8 multiplier based on Vedic Wallace
methodology is
depicted in Figure 5. Demonstrating with an example of the two digits consisting of 8
bits, the output is obtained in 16 bits length.

Figure 3.4 Schematic Diagram of 4x4 bit Multiplier
Figure 3.5 Schematic Diagram of 8x8 bit Vedic Wallace based multiplier

3.4.2 Vedic Wallace Multiplier for 16x16 Bit Module

The 16x16 Vedic Wallace Multiplier modules are realizedusing four 8x8
multiplier modules. The processing of the16x16 multiplier based on Vedic Wallace
methodology is depicted in Figure 6. Demonstrating with an example of two digits
consisting of 16 bits, the output is obtained in 32 bits length.

CHAPTER 4
PROBLEM STATEMENT
One of the primary features that help us determine the computational power of
a processor is the speed of its arithmetic unit. An important function of an arithmetic
block is multiplication because, in most mathematical computations, it forms the bulk
of the execution time. Thus, the development of a fast multiplier has been a key
research area for a long time. Some of the important algorithms proposed for fast
multiplication in literature are Array, Booth and Wallace multipliers. Vedic
Mathematics is a methodology of arithmetic rules that allows for more efficient
implementations regarding speed. A high-speed Vedic multiplier based on the Urdhva
Tiryagbhyam sutra of Vedic mathematics that incorporates a novel adder based on
Quaternary Signed digit number system. Multipliers are the most important unit in
high speed arithmetic logic units, multiplier and accumulate units, digital signal
processing units etc. With the high demand in increasing constraints limits on delay,
more and more emphasis is being put on design of high speed multiplications. To
increase speed many adjustment over the standard modified .

CHAPTER 5
PROPOSED METHOD
5.1 INTRODUCTION
One of the primary features that help us determine the computational power of
a processor is the speed of its arithmetic unit. An important function of an arithmetic
block is multiplication because, in most mathematical computations, it forms the bulk
of the execution time. Thus, the development of a fast multiplier has been a key
research area for a long time. Some of the important algorithms proposed for fast
multiplication in literature are Array, Booth and Wallace multipliers. Vedic
Mathematics is a methodology of arithmetic rules that allows for more efficient
implementations regarding speed. Multiplication in this methodology consists of three
steps: generation of partial products, reduction of partial products, and finally carry
propagate addition. Multiplier design based on Vedic mathematics has many
advantages as the partial products and sums are generated in one step, which reduces
the carry propagation from LSB to MSB. This feature helps in scaling the design for
larger inputs without proportionally increasing the propagation delay as all smaller
blocks of the design work concurrently. References compared Vedic Multiplier with
other multiplier architectures namely Booth, Array and Wallace on the basis of delay
and power consumption. Vedic multiplier showed improvements in both the
parameters over other architectures. Thus, many implementations of multiplication
algorithms based on Vedic sutras have been reported in literature. Vedic multiplier
schemes proposed in literature are based on Urdhva Tiryagbhyam and Nikhilam
sutras of Vedic Mathematics. As Nikhilam sutra is only efficient for inputs that are
close to the power of 10, in this paper a design to perform high-speed multiplication
based on the Urdhva Tiryagbhyam sutra of Vedic Mathematics which is generalized
method for all numbers, has been presented. The final step, carry-propagate addition,
requires a fast adder scheme because it forms a part of the critical path. A variety of
adder schemes have been proposed in literature to optimize the performance of Vedic
multiplier. Adder based on QSD shows an improvement in speed over other state of
the art adders. Earlier implementations of QSD adder were based on Multi Voltage or
Multi Value Logic (MVL). The difficulty in application of quaternary addition outside
MVL (Multi Voltage logic) is that, the adder is only a small unit of the design whose
outputs will need to be converted back to binary for further processing. However, use

of a conversion module undermines the advantages gained in speed by using QSD. In

this paper, a novel implementation of an adder based on QSD is proposed, which
reduces the carry propagation delay in the design by making use of carry free
arithmetic. The proposed adder design works on a hybrid of binary and quaternary
number systems wherein the sum is directly generated in binary using the concept of
an adjusting bit, eliminating the conversion module. The design can be scaled to
larger bit implementations such as 32, 64, 128 or more with minimal increase in
propagation delay owing to the parallelism prevalent in the design. We have
compared our design with a Vedic multiplier based on MVL logic that uses a ripple
carry adder, Vedic Multiplier that incorporates a QSD adder and a conversion module
for quaternary to binary conversion, Vedic multiplier that uses state of the art fast
adder scheme such as Carry select adder and a commonly used fast multiplication
mechanism such as Booth multiplier , to prove the feasibility of our design across
important comparison points.
5.2. BASIC TERMINOLOGY
Urdhva Tiryagbhyam (UT) Sutra ,The UT sutra is an ancient Vedic

Mathematics sutra that can be used for multiplication of two numbers in any number
system. It is based on “Vertical and Crosswise” multiplication. A 2x2 multiplier based
on UT sutra is depicted in Fig. 1 and Fig. 2, where X and Y represent inputs while Z
corresponds to output. Stepwise procedure is outlined below. Step1: Vertical
Multiplication: The least significant digits of the multiplicand and the multiplier are
multiplied, as in (1). Z0=X0.Y0 (1) Step2: Crosswise Multiplication and Addition:
Z1, in (2), is obtained by cross multiplying X1 and Y0, and Y1 and X0 and
subsequently adding the two products. In this stage a carry C1, as in (3), might be
generated, that is propagated to the next step. Z1= (X0.Y1) ⊕ (X1.Y0) (2)
C1=X0.X1.Y0.Y1 (3) Step3: Vertical Multiplication and Addition: The most
significant digits of the multiplicand and the multiplier are multiplied, and the product
is added with the carry of the previous step to obtain Z3 and Z2, as in (4) and (5)
respectively. Z2= (X1.Y1) ⊕ C1 (4) Z3= X0.X1.Y0.Y1 (5) The final result is
concatenation of Z3, Z2, Z1 and Z0. Fig. 1. Vertical and Crosswise multiplication The
logic circuit for 2x2 UT multiplier is shown Fig. 2x2 UT multiplier

Figure 5.1 2x2 UT multiplier
5.3 Quaternary Signed Digit (QSD number system)
The QSD is a radix-4 number system that provides the benefit of faster
arithmetic calculations over binary computation, as it eliminates rippling of carry
during addition. Every number in QSD can be represented using digits from the set {-
3,-2,-1, 0, 1, 2, 3}. Being a higher radix number system it utilizes less number of gates
and hence saves on time and reduces circuit complexity. The stages involved in
addition of two numbers in QSD are: Stage1: Generation of intermediate carry and
sum: When two digits are added in QSD number system, the resulting sum ranges
between -6 to +6. Numbers with magnitude higher than 3 are represented by multiple
digits with least significant digit representing sum and the next digit corresponds to
carry. Also, every number in QSD can have multiple representations. The
representation is chosen such that the magnitude of sum digit is 2 or less than 2 and
the magnitude of carry digit is 1 or less than 1, the reason for which is explained in
the next stage. Stage2: The intermediate sum and carry have a limit fixed on their
magnitude because this allows carry free addition in the second step. The result can be
obtained directly by adding the sum digit with the carry of the lower significant digit.

5.4 PROPOSED DESIGN
4x4 Multiplier
Block diagram of a 4x4 multiplier is shown in Fig.4.2 In this multiplier, four

2x2 multipliers are arranged systematically. Each multiplier accepts four input bits;
two bits from multiplicand and other two bits from multiplier. Addition of partial
products is done using two four bit Quaternary adders, a two-bit adder and a half
adder. The final result is obtained by concatenating the least significant two bits of the
first multiplier, four sum bits of the second four-bit Quaternary adder and the sum bits
of two-bit adder.
Figure 5.2 proposed 4x4 multiplier
Table I shows all intermediate and final results involved in the multiplication
process of two binary numbers, A = (1111)2 and B = (1001)2. The data flow in the
proposed 4x4 multiplier is given below: 1) A[1:0] and B[1:0], A[3:2] and B[1:0],

A[1:0] and B[3:2], and A[3:2] and B[3:2] are multiplied by 2x2 Vedic multipliers,
giving output D0[3:0], D1[3:0], D2[3:0] and D3[3:0] respectively.
2) D1 [3:0] and D2[3:0] are added by the proposed 4 bit QSD adder, giving D4[3:0]
and a carry out as the outputs. 3) D4[3:0] and {D3[1:0], D0[3:2]} are added by the
second 4 bit QSD adder, giving D5[3:0] and a carry out as the outputs. 4) The half
adder is used to add the carry outs of the QSD adders. The output obtained is fed to
the 2 Bit Adder along with D3[3:2]. 5) The result, C, in binary is obtained by
concatenation of output of 2 Bit Adder, D5[3:0] and D0[1:0]. The proposed design
can be extended to multiply both negative and positive integers by an addition of a
sign bit in both inputs. An XOR logic can then be used to compute the sign bit of the
final output. The multiplication of the magnitudes will proceed simultaneously in a
similar manner to the example described above.
5.5 32x32 multiplier
The 4x4 multiplier design can be scaled to multiply larger numbers as shown
in Fig. 4, where the design is scaled up for a 32 bit multiplier.

Figure 5.3 proposed 32x32 multiplier
5.6 Proposed adder design based on QSD
A novel idea of an adder, based on QSD (Quaternary Signed Digit) is

proposed. The algorithm for the proposed adder uses a hybrid of quaternary and
binary number systems. The outputs from smaller multipliers are obtained as binary
strings. Inside the addition module, this string is broken into quaternary digits of two
bits each. Addition using QSD allows us to reduce the carry propagation delay by
making use of carry free arithmetic i.e. the carry doesn’t ripple past the subsequent
quaternary digit. Especially for higher bit input strings this method is extremely
efficient. The difficulty in application of quaternary addition outside MVL (Multi
Voltage logic) is that the least significant 2 bits of the binary representation of the
quaternary digits can’t be directly concatenated to form an output binary string for
every case as depicted in Table II. Each string would have to be read individually and
a conversion module that converts quaternary to binary would have to be employed.
To overcome this limitation, the concept of an adjusting bit has been introduced.

The Intermediate sum lies in the range [0, 6], as the operands are unsigned
numbers. From [16], for quaternary addition to be carry free beyond the first stage,
the intermediate sum can’t be greater than 2. To ensure this stipulation holds true, the
(1 )4 representation of 3 needs to be chosen while adding. However, this represents a
blocking case when converting the final output string back into binary as it prohibits
us from simply concatenating the lower two bits of quaternary output strings to get the
binary equivalent. For addition of unsigned numbers, if the (03)4 representation
would have been used, direct concatenation of results could have been possible. But,
then that wouldn’t have always been carry free after the initial stage. Thus, the
concept of an adjusting bit has been devised to solve the dilemma of which
representation of 3 to use, such that both carry free addition and concatenation of
output string bits to get the final output can be realized in the same design. The
solution to the problem described above, is that the (03)4 representation of 3 is
required to be taken instead of the (1)4 representation in some cases. But, determining
when such a change is required before proceeding with the addition will increase the
delay of the design and be counter-productive. Thus, the (1)4 representation of 3 is
always selected in stage 1, to satisfy necessary conditions for carry free arithmetic.
While necessary adjustments are made in stage 2 if (03)4 representations was to be
taken, the need for such an adjustment is determined via an adjusting bit.
OBSERVATION 1: In both quaternary representations of 3, (03)4 or (1 )4, the two

least significant bits of the least significant digit are 11. Thus, regardless of which
representation was supposed to be taken, the lower two bits of the intermediate sum
will remain same and these are the twobit positions that would be concatenated in the
end. The problem of incorrect representation would come under certain cases. To
better understand these cases an example is described. The example uses two numbers
as inputs represented using three quaternary digits each: Input A= (X3X2X1)4 =
(A8A7A6A5A4A3A2A1A0)2 = (030)4 Input B = (Y3Y2Y1)4 =

(B8B7B6B5B4B3B2B1B0)2 = (001)4 The Base case: For addition of X2 and Y2, if

the intermediate sum comes out to be 3, as stated above (1 )4 representation will be
chosen in stage 1. The Intermediate sum for this digit addition becomes or (111)2. If
then the intermediate carry from the addition of X1 and Y1 is 0, the final output after
stage 2 for this addition would be . The intermediate carry that will be added to
addition of X3 and Y3 would be 1. The binary output thus received after the
concatenation of lower two bits will be wrong, as shown in Table III. As established
above, this problem wouldn’t have been there if the (03)4 representation of 3 would
have been used. According to the findings of observation 1, the intermediate carry
from addition of X2 and Y2 needs to be negated for the correct result because for
(03)4 there would have been no carry. This negation will be done by the adjusting bit.
Mathematically this can be written as: Final output = Intermediate sum +

Intermediate carry – Adjusting bit. Thus, adjusting bit can be said to be 1 when (Sn-1.
) is true where Sn-1 and are defined as: Sn-1: True if n-1th intermediate sum digit is 3.
: True if there is no carry from n-2th digits sum. Secondly, another special case could
arise when the intermediate sum for addition of X2 and Y2 and X1 and Y1 are both 3.
For example if A = (030)4 and B = (003)4. Now as per previously devised logic the
addition would have proceeded as in Table IV. Thus, the final result as shown in
Table IV, would have been (01 11 11)2 which is incorrect. The intermediate carry
from the addition of X2 and Y2 hasn’t been negated while carry from addition of X1
and Y1 has. This is because intermediate carry from X1 and Y1 is taken as 1 while
calculating the adjusting bit for X3 and Y3 While an adjustment is made to it later to
negate it to 0. This adjustment hasn’t been factored into the formula. Thus, the
modified and complete formula for adjusting bit becomes as in (10).


Figure 5.4 proposed adder
Where Sn-2 is true if n-2th intermediate sum digit is 3. This formula can cover
the problem of n consecutive 3’s in a similar manner. The adjusting bit can be
predicted based on the initial inputs to the adders itself. It can be computed in parallel
with Stage 1. Thus, effect on delay of the adder is minimal. The above example is
revaluated with the modified formula: Input A= (X3X2X1)4 =
(A8A7A6A5A4A3A2A1A0)2 = (030)4 Input B = (Y3Y2Y1)4 =
(B8B7B6B5B4B3B2B1B0)2 = (003)4 Adjusting Bit for addition of Xn and Yn is Sn-
1.(Sn-2+ ). As can be seen from the flow of data shown in Table V. The modified
formula gives the correct binary output after concatenation. The proposed adder
works in two stages, as shown in Fig. 5. 1) In the first stage, as in Fig. 5(a), every
individual digit at the same position in the quaternary representation of two n-bit
numbers A and B is added using a 2 Bit Adder to generate a sum. This sum lies in the
range [0, 6]. From the sum obtained from the adder, the intermediate sum and
intermediate carry for the next stage are calculated in parallel using 2x1 multiplexers.

The logic for the selection of the representation of sum and carry has been explained
in [16]. The adjusting bit is also computed in parallel with the addition process. The
input to the adjusting bit calculation block for every quaternary digit addition are the
previous two quaternary digits of A and B signified by [n-2: n-5]. 2) Second stage has
two modules as shown in Fig. 5(b). One is a one-bit module that performs the
computation (A+BC). In this case A would be LSB of intermediate sum, B would be
carry from the previous quaternary digit addition and C would be the adjusting bit.
The other module will be a half adder which will add the carry from the (A+B-C)
module and the bit to the left of the least significant bit of the intermediate sum. As
for the final concatenation, the sign bit would not be used owing to the adjustments
proposed in the design. Thus, its final value is not computed.
5.7 EXTENSION
Vedic Wallace Multiplier for 32x32 Bit Module

The 32x32 Vedic Wallace Multiplier modules are realized using four 16x16
multiplier modules. The processing of 32x32 multiplier based on Vedic Wallace
methodology is depicted in Figure 7. Demonstrating with an example of two digits
consisting of 32 bits, the output is obtained in 64 bits length
Module of NxN Vedic Multiplier

The Schematic block diagram of NxN bit Vedic Wallace based Multiplier is shown in
Figure.

Figure 8: Schematic block diagram of N*N bit vedic Wallace based mulitiplier

5.8 DESIGN OF ARITHMETIC LOGIC UNIT
ALU was designed to perform the arithmetic and logical operations for the
controller. Arithmetic operations performed are the 32-bit addition, subtraction, and
multiplication. Logical operations performed are AND, OR, XOR, NAND, NOR,
XNOR, NOT and Data Buffer. For designing the ALU, the authors had followed a
flexible design that consists of smaller, but more manageable blocks, some of which
can be re-used [2]. Designing of half-adder, 2-bit multiplier, 4-bit Brent-Kung, 4-bit
multiplier, 8-bit Brent-Kung adder, 8-bit multiplier, 8-bit full adder, 8-bit subtractor,
32-bit Brent-Kung adder, 32-bit multiplier, 32-bit full adder, 32-bit subtractor, 32-bit
arithmetic unit, logical unit and 32-bit ALU has been done[7].
ARITHMETIC UNIT
·An Arithmetic unit does the following task: Addition with carry, multiplication, and
subtraction.
Figure 5.9. Schematic Block Diagram of Arithmetic Logic Unit
·A half adder is used to make the 4-bit Brent-Kung adder and then a 4-bit multiplier.
·4-bit Brent-Kung adder is used to make the 8 bit Brent- Kung adder.
·The 8-bit multiplier is made by using the 4-bit multiplier and 8-bit Brent-Kung adder.
·8-bit subtractor.
·The 32-bit multiplier is made by using the 16-bit multiplier and the 16-bit Brent-
Kung adder.·32-bit subtractor.

LOGICAL UNIT
For designing of the logical unit, the performance of logic circuits have been
analysed by employing the commonly used logic gates and a multiplexer. A Logic
unit does the
various operations such as Logical AND, OR, XOR, NOT, NAND, NOR, XNOR, and
data buffer. In addition to this arithmetic unit and logical unit, they have been
combined into the arithmetic logic units. The schematic block diagram of an
arithmetic logic unit is shown in Figure 9, that is self-explanatory in itself. The output
of the ALU and Logical Unit is 64 bits. Table 1 shows the control word for ALU
operations
Lowest path delay for various multipliers. This section also deals with the
quantitative and comparative result analysis of the different approach to Vedic
mathematics through various multipliers and adder design and implementation.
Additionally, to validate the proposed Vedic mathematics based various multipliers
and adder designs and their implementation, the synthesis and the simulated results
have been compared with some other trendy multiplier structures which are designed
based on the different multiplication algorithms. Table 2 shows the efficacy of the
proposed Vedic Wallace multiplier at 32- bit level. It has been compared and showed
the lowest path delays in comparison to others. Figure 10 shows the schematic block
diagram of 32-bit RTL implementation by using Vedic Mathematics, whereas, the
simulation results of 32-bit multiplier based on the Vedic Wallace and 32-bit
Arithmetic Logic Unit as per the control word are shown in Figure 11 and Figure 12,
respectively. Besides this, Table 3, summarized the ALU with different multipliers
and adders.

CHAPTER 6
GENERAL DOCUMENT
Very-large-scale integration (VLSI) is the process of creating integrated

circuits by combining thousands of transistor-based circuits into a single chip. VLSI
began in the 1970s when complex semiconductor and communication technologies
were being developed. The microprocessor is a VLSI device. The term is no longer as
common as it once was, as chips have increased in complexity into the hundreds of
millions of transistors.
Overview:
The first semiconductor chips held one transistor each. Subsequent advances
added more and more transistors, and, as a consequence, more individual functions or
systems were integrated over time. The first integrated circuits held only a few
devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making it
possible to fabricate one or more logic gates on a single device. Now known
retrospectively as "small-scale integration" (SSI), improvements in technique led to
devices with hundreds of logic gates, known as large-scale integration (LSI), i.e.
systems with at least a thousand logic gates. Current technology has moved far past
this mark and today's microprocessors have many millions of gates and hundreds of
millions of individual transistors.
At one time, there was an effort to name and calibrate various levels of large-scale
integration above VLSI. Terms like Ultra-large-scale Integration (ULSI) were used.
But the huge number of gates and transistors available on common devices has
rendered such fine distinctions moot.
Terms suggesting greater than VLSI levels of integration are no longer in widespread
use. Even VLSI is now somewhat quaint, given the common assumption that all
microprocessors are VLSI or better.
As of early 2008, billion-transistor processors are commercially available, an example
of which is Intel's Montecito Itanium chip. This is expected to become more
commonplace as semiconductor fabrication moves from the current generation of 65
nm processes to the next 45 nm generations (while experiencing new challenges such

as increased variation across process corners). Another notable example is NVIDIA’s

280 series GPU.
This microprocessor is unique in the fact that its 1.4 Billion transistor count,
capable of a teraflop of performance, is almost entirely dedicated to logic (Itanium's
transistor count is largely due to the 24MB L3 cache). Current designs, as opposed to
the earliest devices, use extensive design automation and automated logic synthesis to
lay out the transistors, enabling higher levels of complexity in the resulting logic
functionality. Certain high-performance logic blocks like the SRAM cell, however,
are still designed by hand to ensure the highest efficiency (sometimes by bending or
breaking established design rules to obtain the last bit of performance by trading
stability).
What is VLSI?
VLSI stands for "Very Large Scale Integration". This is the field which
involves packing more and more logic devices into smaller and smaller areas.
VLSI
 Simply we say Integrated circuit is many transistors on one chip.
 Design/manufacturing of extremely small, complex circuitry using modified
semiconductor material
 Integrated circuit (IC) may contain millions of transistors, each a few mm in
size
 Applications wide ranging: most electronic logic devices
History of Scale Integration:

 late 40s Transistor invented at Bell Labs
 late 50s First IC (JK-FF by Jack Kilby at TI)
 early 60s Small Scale Integration (SSI)
 10s of transistors on a chip
 late 60s Medium Scale Integration (MSI)
 100s of transistors on a chip

 early 70s Large Scale Integration (LSI)

 1000s of transistor on a chip
 early 80s VLSI 10,000s of transistors on a
 chip (later 100,000s & now 1,000,000s)
 Ultra LSI is sometimes used for 1,000,000s
 SSI - Small-Scale Integration (0-102)
 MSI - Medium-Scale Integration (102-103)
 LSI - Large-Scale Integration (103-105)
 VLSI - Very Large-Scale Integration (105-107)
 ULSI - Ultra Large-Scale Integration (>=107)
Advantages of ICs over discrete components:
While we will concentrate on integrated circuits , the properties of integrated

circuits-what we can and cannot efficiently put in an integrated circuit-largely
determine the architecture of the entire system. Integrated circuits improve system
characteristics in several critical ways. ICs have three key advantages over digital
circuits built from discrete components:
 Size. Integrated circuits are much smaller-both transistors and wires are
shrunk to micro meter sizes, compared to the millimeter or centimeter scales
of discrete components. Small size leads to advantages in speed and power
consumption, since smaller components have smaller parasitic resistances,
capacitances, and inductances.
 Speed. Signals can be switched between logic 0 and logic 1 much quicker
within a chip than they can between chips. Communication within a chip can
occur hundreds of times faster than communication between chips on a printed
circuit board. The high speed of circuits on-chip is due to their small size-
smaller components and wires have smaller parasitic capacitances to slow
down the signal.
 Power consumption Logic operations within a chip also take much less
power. Once again, lower power consumption is largely due to the small size
of circuits on the chip-smaller parasitic capacitances and resistances require
less power to drive them.

6.1 VLSI and systems
These advantages of integrated circuits translate into advantages at the system level:
 Smaller physical size. Smallness is often an advantage in itself-consider
portable televisions or handheld cellular telephones.
 Lower power consumption. Replacing a handful of standard parts with a single
chip reduces total power consumption. Reducing power consumption has a
ripple effect on the rest of the system: a smaller, cheaper power supply can be
used; since less power consumption means less heat, a fan may no longer be
necessary; a simpler cabinet with less shielding for electromagnetic shielding
may be feasible, too.
 Reduced cost. Reducing the number of components, the power supply
requirements, cabinet costs, and so on, will inevitably reduce system cost. The
ripple effect of integration is such that the cost of a system built from custom
ICs can be less, even though the individual ICs cost more than the standard
parts they replace.
Understanding why integrated circuit technology has such profound influence on the
design of digital systems requires understanding both the technology of IC
manufacturing and the economics of ICs and digital systems.
Applications
 Electronic system in cars.
 Digital electronics control VCRs
 Transaction processing system, ATM
 Personal computers and Workstations
 Medical electronic systems.

Applications of VLSI
Electronic systems now perform a wide variety of tasks in daily life. Electronic
systems in some cases have replaced mechanisms that operated mechanically,
hydraulically, or by other means; electronics are usually smaller, more flexible, and
easier to service. In other cases electronic systems have created totally new
applications. Electronic systems perform a variety of tasks, some of them visible,
some more hidden:
 Personal entertainment systems such as portable MP3 players and DVD
players perform sophisticated algorithms with remarkably little energy.
 Electronic systems in cars operate stereo systems and displays; they also
control fuel injection systems, adjust suspensions to varying terrain, and
perform the control functions required for anti-lock braking (ABS) systems.
 Digital electronics compress and decompress video, even at high-definition
data rates, on-the-fly in consumer electronics.
 Low-cost terminals for Web browsing still require sophisticated electronics,
despite their dedicated function.
 Personal computers and workstations provide word-processing, financial
analysis, and games. Computers include both central processing units (CPUs)
and special-purpose hardware for disk access, faster screen display, etc.
 Medical electronic systems measure bodily functions and perform complex

processing algorithms to warn about unusual conditions. The availability of
these complex systems, far from overwhelming consumers, only creates
demand for even more complex systems.
The growing sophistication of applications continually pushes the design and
manufacturing of integrated circuits and electronic systems to new levels of
complexity. And perhaps the most amazing characteristic of this collection of systems
is its variety-as systems become more complex, we build not a few general-purpose
computers but an ever wider range of special-purpose systems. Our ability to do so is
a testament to our growing mastery of both integrated circuit manufacturing and
design, but the increasing demands of customers continue to test the limits of design
and manufacturing

6.2 ASIC
An Application-Specific Integrated Circuit (ASIC) is an integrated circuit (IC)
customized for a particular use, rather than intended for general-purpose use. For
example, a chip designed solely to run a cell phone is an ASIC. Intermediate between
ASICs and industry standard integrated circuits, like the 7400 or the 4000 series, are
application specific standard products (ASSPs).
As feature sizes have shrunk and design tools improved over the years, the maximum
complexity (and hence functionality) possible in an ASIC has grown from 5,000 gates
to over 100 million. Modern ASICs often include entire 32-bit processors, memory
blocks including ROM, RAM, EEPROM, Flash and other large building blocks. Such
an ASIC is often termed a SoC (system-on-a-chip). Designers of digital ASICs use a
hardware description language (HDL), such as Verilog or VHDL, to describe the
functionality of ASICs.
Field-programmable gate arrays (FPGA) are the modern-day technology for

building a breadboard or prototype from standard parts; programmable logic blocks
and programmable interconnects allow the same FPGA to be used in many different
applications. For smaller designs and/or lower production volumes, FPGAs may be
more cost effective than an ASIC design even in production.
 An application-specific integrated circuit (ASIC) is an integrated circuit (IC)
customized for a particular use, rather than intended for general-purpose use.
 A Structured ASIC falls between an FPGA and a Standard Cell-based ASIC
 Structured ASIC’s are used mainly for mid-volume level design. The design
task for structured ASIC’s is to map the circuit into a fixed arrangement of
known cells.
6.3 SOFTWARE
INTRODUCTION TO XILINX
Migrating Projects from Previous ISE Software Releases

When you open a project file from a previous release, the ISE® software prompts you
to migrate your project. If you click Backup and Migrate or Migrate Only, the
software automatically converts your project file to the current release. If you click
Cancel, the software does not convert your project and, instead, opens Project
Navigator with no project loaded.
Note: After you convert your project, you cannot open it in previous versions of the
ISE software, such as the ISE 11 software. However, you can optionally create a
backup of the original project as part of project migration, as described below.
To Migrate a Project
1. In the ISE 12 Project Navigator, select File > Open Project.
2. In the Open Project dialog box, select the .xise file to migrate.
Note You may need to change the extension in the Files of type field to display .npl
(ISE 5 and ISE 6 software) or .ise (ISE 7 through ISE 10 software) project files.
3. In the dialog box that appears, select Backup and Migrate or Migrate Only.
4. The ISE software automatically converts your project to an ISE 12 project.
Note If you chose to Backup and Migrate, a backup of the original project is created
at project_name_ise12migration.zip.
5. Implement the design using the new version of the software.
Note Implementation status is not maintained after migration.
Properties
For information on properties that have changed in the ISE 12 software, see ISE 11 to
ISE 12 Properties Conversion.
IP Modules:
If your design includes IP modules that were created using CORE Generator™
software or Xilinx® Platform Studio (XPS) and you need to modify these modules,
you may be required to update the core. However, if the core netlist is present and you
do not need to modify the core, updates are not required and the existing netlist is
used during implementation.
Obsolete Source File Types:
The ISE 12 software supports all of the source types that were supported in the ISE 11
software.

If you are working with projects from previous releases, state diagram source files
(.dia), ABEL source files (.abl), and test bench waveform source files (.tbw) are no
longer supported. For state diagram and ABEL source files, the software finds an
associated HDL file and adds it to the project, if possible. For test bench waveform
files, the software automatically converts the TBW file to an HDL test bench and adds
it to the project. To convert a TBW file after project migration, see Converting a
TBW File to an HDL Test Bench
6.4 Using ISE Example Projects

To help familiarize you with the ISE® software and with FPGA and CPLD designs, a
set of example designs is provided with Project Navigator. The examples show
different design techniques and source types, such as VHDL, Verilog, schematic, or
EDIF, and include different constraints and IP.
To Open an Example
1. Select File > Open Example.
2. In the Open Example dialog box, select the Sample Project Name.
Note To help you choose an example project, the Project Description field describes
each project. In addition, you can scroll to the right to see additional fields, which
provide details about the project.
3. In the Destination Directory field, enter a directory name or browse to the
directory.
4. Click OK.
The example project is extracted to the directory you specified in the Destination
Directory field and is automatically opened in Project Navigator. You can then run
processes on the example project and save any changes.
Note If you modified an example project and want to overwrite it with the original
example project, select File > Open Example, select the Sample Project Name, and
specify the same Destination Directory you originally used. In the dialog box that
appears, select Overwrite the existing project and click OK.
Creating a Project
Project Navigator allows you to manage your FPGA and CPLD designs using an
ISE® project, which contains all the source files and settings specific to your design.

First, you must create a project and then, add source files, and set process properties.
After you create a project, you can run processes to implement, constrain, and analyze
your design. Project Navigator provides a wizard to help you create a project as
follows.
Note If you prefer, you can create a project using the New Project dialog box instead
of the New Project Wizard. To use the New Project dialog box, deselect the Use New
Project wizard option in the ISE General page of the Preferences dialog box.
To Create a Project
1. Select File > New Project to launch the New Project Wizard.
2. In the Create New Project page, set the name, location, and project type, and
click Next.
3. For EDIF or NGC/NGO projects only: In the Import EDIF/NGC Project page,
select the input and constraint file for the project, and click Next.
4. In the Project Settings page, set the device and project properties, and click
Next.
5. In the Project Summary page, review the information, and click Finish to
create the project
Project Navigator creates the project file (project_name.xise) in the directory you
specified. After you add source files to the project, the files appear in the Hierarchy
pane of the
Design panel
Project Navigator manages your project based on the design properties (top-level
module type, device type, synthesis tool, and language) you selected when you
created the project. It organizes all the parts of your design and keeps track of the
processes necessary to move the design from design entry through implementation to
programming the targeted Xilinx® device.
Note For information on changing design properties, see Changing Design Properties.
You can now perform any of the following:
• Create new source files for your project.
• Add existing source files to your project.

• Run processes on your source files.

Modify process properties.
Creating a Copy of a Project

You can create a copy of a project to experiment with different source options and
implementations. Depending on your needs, the design source files for the copied
project and their location can vary as follows:
• Design source files are left in their existing location, and the copied project
points to these files.
• Design source files, including generated files, are copied and placed in a
specified directory.
• Design source files, excluding generated files, are copied and placed in a
specified directory.
Copied projects are the same as other projects in both form and function. For
example, you can do the following with copied projects:
• Open the copied project using the File > Open Project menu command.
• View, modify, and implement the copied project.
• Use the Project Browser to view key summary data for the copied project and
then, open the copied project for further analysis and implementation, as described in
Using the Project Browser
Alternatively, you can create an archive of your project, which puts all of the project
contents into a ZIP file. Archived projects must be unzipped before being opened in
Project Navigator. For information on archiving, see Creating a Project Archive.
To Create a Copy of a Project
1. Select File > Copy Project.
2. In the Copy Project dialog box, enter the Name for the copy.
Note The name for the copy can be the same as the name for the project, as long as
you specify a different location.
3. Enter a directory Location to store the copied project.
4. Optionally, enter a Working directory.

By default, this is blank, and the working directory is the same as the project
directory. However, you can specify a working directory if you want to keep your
ISE® project file (.xise extension) separate from your working area.
5. Optionally, enter a Description for the copy.
The description can be useful in identifying key traits of the project for reference
later.
6. In the Source options area, do the following:
Select one of the following options:
• Keep sources in their current locations - to leave the design source files in
their existing location.
If you select this option, the copied project points to the files in their existing location.
If you edit the files in the copied project, the changes also appear in the original
project, because the source files are shared between the two projects.
• Copy sources to the new location - to make a copy of all the design source
files and place them in the specified Location directory.
If you select this option, the copied project points to the files in the specified
directory. If you edit the files in the copied project, the changes do not appear in the
original project, because the source files are not shared between the two projects.
Optionally, select Copy files from Macro Search Path directories to copy files from
the directories you specify in the Macro Search Path property in theTranslate
Properties dialog box. All files from the specified directories are copied, not just the
files used by the design.
Note: If you added a netlist source file directly to the project as described in Working
with Netlist-Based IP, the file is automatically copied as part of Copy Project because
it is a project source file. Adding netlist source files to the project is the preferred
method for incorporating netlist modules into your design, because the files are
managed automatically by Project Navigator.
Optionally, click Copy Additional Files to copy files that were not included in the
original project. In the Copy Additional Files dialog box, use the Add Files and
Remove Files buttons to update the list of additional files to copy. Additional files are
copied to the copied project location after all other files are copied.To exclude
generated files from the copy, such as implementation results and reports, select

Exclude generated files from the copy

When you select this option, the copied project opens in a state in which processes
have not yet been run.
7. To automatically open the copy after creating it, select Open the copied
project.
Note By default, this option is disabled. If you leave this option disabled, the original
project remains open after the copy is made.
Click OK.
Creating a Project Archive

A project archive is a single, compressed ZIP file with a .zip extension. By default, it
contains all project files, source files, and generated files, including the following:
• User-added sources and associated files

• Remote sources
• Verilog `include files
5.5 INTRODUCTION TO VERILOG

In the semiconductor and electronic design industry, Verilog is a hardware
description language(HDL) used to model electronic systems. Verilog HDL, not to be
confused with VHDL (a competing language), is most commonly used in the design,
verification, and implementation ofdigital logic chips at the register-transfer level of
abstraction. It is also used in the verification ofanalog and mixed-signal circuits.
Overview
Hardware description languages such as Verilog differ from software
programming languages because they include ways of describing the propagation of

time and signal dependencies (sensitivity). There are two assignment operators, a
blocking assignment (=), and a non-blocking (<=) assignment. The non-blocking
assignment allows designers to describe a state-machine update without needing to
declare and use temporary storage variables (in any general programming language
we need to define some temporary storage spaces for the operands to be operated on
subsequently; those are temporary storage variables). Since these concepts are part of
Verilog's language semantics, designers could quickly write descriptions of large
circuits in a relatively compact and concise form. At the time of Verilog's introduction
(1984), Verilog represented a tremendous productivity improvement for circuit
designers who were already using graphical schematic capturesoftware and specially-
written software programs to document and simulate electronic circuits.
The designers of Verilog wanted a language with syntax similar to the C

programming language, which was already widely used in engineering software
development. Verilog is case-sensitive, has a basic preprocessor (though less
sophisticated than that of ANSI C/C++), and equivalent control flow keywords
(if/else, for, while, case, etc.), and compatible operator precedence. Syntactic
differences include variable declaration (Verilog requires bit-widths on
net/regtypes[clarification needed]), demarcation of procedural blocks (begin/end
instead of curly braces {}), and many other minor differences.
A Verilog design consists of a hierarchy of modules. Modules encapsulate

design hierarchy, and communicate with other modules through a set of declared
input, output, and bidirectional ports. Internally, a module can contain any
combination of the following: net/variable declarations (wire, reg, integer, etc.),
concurrent and sequential statement blocks, and instances of other modules (sub-
hierarchies). Sequential statements are placed inside a begin/end block and executed
in sequential order within the block. But the blocks themselves are executed
concurrently, qualifying Verilog as a dataflow language.
Verilog's concept of 'wire' consists of both signal values (4-state: "1, 0,

floating, undefined") and strengths (strong, weak, etc.). This system allows abstract
modeling of shared signal lines, where multiple sources drive a common net. When a
wire has multiple drivers, the wire's (readable) value is resolved by a function of the
source drivers and their strengths.

A subset of statements in the Verilog language is synthesizable. Verilog

modules that conform to a synthesizable coding style, known as RTL (register-
transfer level), can be physically realized by synthesis software. Synthesis software
algorithmically transforms the (abstract) Verilog source into a net list, a logically
equivalent description consisting only of elementary logic primitives (AND, OR,
NOT, flip-flops, etc.) that are available in a specific FPGA or VLSI technology.
Further manipulations to the net list ultimately lead to a circuit fabrication blueprint
(such as a photo mask set for an ASIC or a bitstream file for an FPGA).
6.6 History
Beginning
Verilog was the first modern hardware description language to be invented. It
was created by Phil Moorby and PrabhuGoel during the winter of 1983/1984. The
wording for this process was "Automated Integrated Design Systems" (later renamed
to Gateway Design Automation in 1985) as a hardware modeling language. Gateway
Design Automation was purchased by Cadence Design Systems in 1990. Cadence
now has full proprietary rights to Gateway's Verilog and the Verilog-XL, the HDL-
simulator that would become the de-facto standard (of Veriloglogic simulators) for
the next decade. Originally, Verilog was intended to describe and allow simulation;
only afterwards was support for synthesis added.
Verilog-95
With the increasing success of VHDL at the time, Cadence decided to make
the language available for open standardization. Cadence transferred Verilog into the
public domain under the Open Verilog International (OVI) (now known as Accellera)
organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-
1995, commonly referred to as Verilog-95. In the same time frame Cadence initiated
the creation of Verilog-A to put standards support behind its analog simulator Spectre.
Verilog-A was never intended to be a standalone language and is a subset of Verilog-
AMS which encompassed Verilog-95.
Verilog 2001

Extensions to Verilog-95 were submitted back to IEEE to cover the

deficiencies that users had found in the original Verilog standard. These extensions
became IEEE Standard 1364-2001 known as Verilog-2001. Verilog-2001 is a
significant upgrade from Verilog-95. First, it adds explicit support for (2's
complement) signed nets and variables. Previously, code authors had to perform
signed operations using awkward bit-level manipulations (for example, the carry-out
bit of a simple 8-bit addition required an explicit description of the Boolean algebra to
determine its correct value). The same function under Verilog-2001 can be more
succinctly described by one of the built-in operators: +, -, /, *, >>>. A
generate/endgenerate construct (similar to VHDL's generate/endgenerate) allows
Verilog-2001 to control instance and statement instantiation through normal decision
operators (case/if/else). Using generate/endgenerate, Verilog-2001 can instantiate an
array of instances, with control over the connectivity of the individual instances. File
I/O has been improved by several new system tasks. And finally, a few syntax
additions were introduced to improve code readability (e.g. always @*, named
parameter override, C-style function/task/module header declaration).
Verilog-2001 is the dominant flavor of Verilog supported by the majority of

commercial EDA software packages.
Verilog 2005
Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364-

2005) consists of minor corrections, spec clarifications, and a few new language
features (such as the uwire keyword). A separate part of the Verilog standard,
Verilog-AMS, attempts to integrate analog and mixed signal modeling with
traditional Verilog.
System Verilog
System Verilog is a superset of Verilog-2005, with many new features and
capabilities to aid design verification and design modeling. As of 2009, the System
Verilog and Verilog language standards were merged into System Verilog 2009
(IEEE Standard 1800-2009). The advent of hardware verification languages such as
OpenVera, and Verisity's e language encouraged the development of Superlog by Co-
Design Automation Inc. Co-Design Automation Inc was later purchased by Synopsys.

The foundations of Superlog and Vera were donated to Accellera, which later became
the IEEE standard P1800-2005: System Verilog.
In the late 1990s, the Verilog Hardware Description Language (HDL) became
the most widely used language for describing hardware for simulation and synthesis.
However, the first two versions standardized by the IEEE (1364-1995 and 1364-2001)
had only simple constructs for creating tests. As design sizes outgrew the verification
capabilities of the language, commercial Hardware Verification Languages (HVL)
such as Open Vera and ewere created. Companies that did not want to pay for these
tools instead spent hundreds of man-years creating their own custom tools. This
productivity crisis (along with a similar one on the design side) led to the creation of
Accellera, a consortium of EDA companies and users who wanted to create the next
generation of Verilog. The donation of the Open-Vera language formed the basis for
the HVL features of System Verilog. Accellera’s goal was met in November 2005
with the adoption of the IEEE standard P1800-2005 for System Verilog, IEEE
(2005).The most valuable benefit of System Verilog is that it allows the user to
construct reliable, repeatable verification environments, in a consistent syntax, that
can be used across multiple projects
Some of the typical features of an HVL that distinguish it from a Hardware

Description Language such as Verilog or VHDL are
 Constrained-random stimulus generation

 Functional coverage
 Higher-level structures, especially Object Oriented Programming
 Multi-threading and interprocess communication
 Support for HDL types such as Verilog’s 4-state values
 Tight integration with event-simulator for control of the design
There are many other useful features, but these allow you to create test benches at a
higher level of abstraction than you are able to achieve with an HDL or a
programming language such as C.
System Verilog provides the best framework to achieve coverage-driven verification

(CDV). CDV combines automatic test generation, self-checking testbenches, and
coverage metrics to significantly reduce the time spent verifying a design. The
purpose of CDV is to:
 Eliminate the effort and time spent creating hundreds of tests.

 Ensure thorough verification using up-front goal setting.

 Receive early error notifications and deploy run-time checking and error
analysis to simplify debugging.
Examples
Ex1: A hello world program looks like this:
module main;
initial
begin
$display("Hello world!");
$finish;
end
endmodule
Ex2: A simple example of two flip-flops follows:

moduletoplevel(clock,reset);
input clock;
input reset;
reg flop1;
reg flop2;
always@(posedge reset orposedge clock)
if(reset)
begin
flop1 <=0;
flop2 <=1;
end

else
begin
flop1 <= flop2;
flop2 <= flop1;
end
endmodule
The "<=" operator in Verilog is another aspect of its being a hardware description
language as opposed to a normal procedural language. This is known as a "non-
blocking" assignment. Its action doesn't register until the next clock cycle. This means
that the order of the assignments are irrelevant and will produce the same result: flop1
and flop2 will swap values every clock.
The other assignment operator, "=", is referred to as a blocking assignment. When "="
assignment is used, for the purposes of logic, the target variable is updated
immediately. In the above example, had the statements used the "=" blocking operator
instead of "<=", flop1 and flop2 would not have been swapped. Instead, as in
traditional programming, the compiler would understand to simply set flop1 equal to
flop2 (and subsequently ignore the redundant logic to set flop2 equal to flop1.)
Ex3: An example counter circuit follows:
module Div20x (rst,clk,cet,cep, count,tc);
// TITLE 'Divide-by-20 Counter with enables'
// enable CEP is a clock enable only
// enable CET is a clock enable and
// enables the TC output
// a counter using the Verilog language
parameter size =5;
parameter length =20;
inputrst;// These inputs/outputs represent
inputclk;// connections to the module.

inputcet;
inputcep;
output[size-1:0] count;
outputtc;
reg[size-1:0] count;// Signals assigned
// within an always
// (or initial)block
// must be of type reg
wiretc;// Other signals are of type wire
// The always statement below is a parallel
// execution statement that
// executes any time the signals
// rst or clk transition from low to high
always@(posedgeclkorposedgerst)
if(rst)// This causes reset of the cntr
count<={size{1'b0}};
else
if(cet&&cep)// Enables both true
begin
if(count == length-1)
count<={size{1'b0}};
else

count<= count +1'b1;
end
// the value of tc is continuously assigned
// the value of the expression
assigntc=(cet&&(count == length-1));
endmodule
Ex4: An example of delays:
...
reg a, b, c, d;
wire e;
...
always@(b or e)
begin
a = b & e;
b = a | b;
#5 c = b;
d =#6 c ^ e;
end
The always clause above illustrates the other type of method of use, i.e. the always
clause executes any time any of the entities in the list change, i.e. the b or e change.
When one of these changes, immediately a is assigned a new value, and due to the
blocking assignment b is assigned a new value afterward (taking into account the new
value of a.) After a delay of 5 time units, c is assigned the value of b and the value of
c ^ e is tucked away in an invisible store. Then after 6 more time units, d is assigned
the value that was tucked away.

Signals that are driven from within a process (an initial or always block) must be of
type reg. Signals that are driven from outside a process must be of type wire. The
keyword reg does not necessarily imply a hardware register.
Constants
The definition of constants in Verilog supports the addition of a width parameter. The
basic syntax is:
<Width in bits>'<base letter><number>
Examples:
 12'h123 - Hexadecimal 123 (using 12 bits)
 20'd44 - Decimal 44 (using 20 bits - 0 extension is automatic)
 4'b1010 - Binary 1010 (using 4 bits)
 6'o77 - Octal 77 (using 6 bits)
6.7 Synthesizable Constructs

There are several statements in Verilog that have no analog in real hardware, e.g.
$display. Consequently, much of the language can not be used to describe hardware.
The examples presented here are the classic subset of the language that has a direct
mapping to real gates.
// Mux examples - Three ways to do the same thing.
// The first example uses continuous assignment
wire out;
assign out =sel?a : b;
// the second example uses a procedure
// to accomplish the same thing.
reg out;
always@(a or b orsel)
begin
case(sel)
1'b0: out = b;
1'b1: out = a;

endcase
end
// Finally - you can use if/else in a
// procedural structure.
reg out;
always@(a or b orsel)
if(sel)
out= a;
else
out= b;
The next interesting structure is a transparent latch; it will pass the input to the output
when the gate signal is set for "pass-through", and captures the input and stores it
upon transition of the gate signal to "hold". The output will remain stable regardless
of the input signal while the gate is set to "hold". In the example below the "pass-
through" level of the gate would be when the value of the if clause is true, i.e. gate =
1. This is read "if gate is true, the din is fed to latch_out continuously." Once the if
clause is false, the last value at latch_out will remain and is independent of the value
of din.
EX6: // Transparent latch example
reg out;
always@(gate or din)
if(gate)
out= din;// Pass through state
// Note that the else isn't required here. The variable
// out will follow the value of din while gate is high.
// When gate goes low, out will remain constant.
The flip-flop is the next significant template; in Verilog, the D-flop is the simplest,
and it can be modeled as:
reg q;
always@(posedgeclk)

q <= d;
The significant thing to notice in the example is the use of the non-blocking
assignment. A basic rule of thumb is to use <= when there is aposedge or negedge
statement within the always clause.
A variant of the D-flop is one with an asynchronous reset; there is a convention that
the reset state will be the first if clause within the statement.
reg q;
always@(posedgeclkorposedge reset)
if(reset)
q <=0;
else
q <= d;
The next variant is including both an asynchronous reset and asynchronous set
condition; again the convention comes into play, i.e. the reset term is followed by the
set term.
reg q;
always@(posedgeclkorposedge reset orposedge set)
if(reset)
q <=0;
else
if(set)
q <=1;
else
q <= d;
Note: If this model is used to model a Set/Reset flip flop then simulation errors can
result. Consider the following test sequence of events. 1) reset goes high 2) clk goes
high 3) set goes high 4) clk goes high again 5) reset goes low followed by 6) set going
low. Assume no setup and hold violations.
In this example the always @ statement would first execute when the rising
edge of reset occurs which would place q to a value of 0. The next time the always
block executes would be the rising edge of clk which again would keep q at a value of

0. The always block then executes when set goes high which because reset is high
forces q to remain at 0. This condition may or may not be correct depending on the
actual flip flop. However, this is not the main problem with this model. Notice that
when reset goes low, that set is still high. In a real flip flop this will cause the output
to go to a 1. However, in this model it will not occur because the always block is
triggered by rising edges of set and reset - not levels. A different approach may be
necessary for set/reset flip flops.
Note that there are no "initial" blocks mentioned in this description. There is a
split between FPGA and ASIC synthesis tools on this structure. FPGA tools allow
initial blocks where reg values are established instead of using a "reset" signal. ASIC
synthesis tools don't support such a statement. The reason is that an FPGA's initial
state is something that is downloaded into the memory tables of the FPGA. An ASIC
is an actual hardware implementation.
Initial Vs Always:
There are two separate ways of declaring a Verilog process. These are the
always and the initial keywords. The always keyword indicates a free-running
process. The initial keyword indicates a process executes exactly once. Both
constructs begin execution at simulator time 0, and both execute until the end of the
block. Once an always block has reached its end, it is rescheduled (again). It is a
common misconception to believe that an initial block will execute before an always
block. In fact, it is better to think of the initial-block as a special-case of the always-
block, one which terminates after it completes for the first time.
//Examples:
initial
begin
a =1;// Assign a value to reg a at time 0
#1;// Wait 1 time unit
b = a;// Assign the value of reg a to reg b
end
always@(a or b)// Any time a or b CHANGE, run the process
begin
if(a)
c = b;

else
d =~b;
end// Done with this block, now return to the top (i.e. the @ event-control)
always@(posedge a)// Run whenever reg a has a low to high change
a <= b;
These are the classic uses for these two keywords, but there are two significant
additional uses. The most common of these is an alwayskeyword without the @(...)
sensitivity list. It is possible to use always as shown below:
always
begin// Always begins executing at time 0 and NEVER stops
clk=0;// Set clk to 0
#1;// Wait for 1 time unit
clk=1;// Set clk to 1
#1;// Wait 1 time unit
end// Keeps executing - so continue back at the top of the begin
The always keyword acts similar to the "C" construct while(1) {..} in the sense that it
will execute forever.
The other interesting exception is the use of the initial keyword with the addition of
the forever keyword.
Race Condition
The order of execution isn't always guaranteed within Verilog. This can best be
illustrated by a classic example. Consider the code snippet below:
initial
a =0;
initial
b = a;
initial
begin

#1;
$display("Value a=%b Value of b=%b",a,b);
end
What will be printed out for the values of a and b? Depending on the order of
execution of the initial blocks, it could be zero and zero, or alternately zero and some
other arbitrary uninitialized value. The $display statement will always execute after
both assignment blocks have completed, due to the #1 delay.
Operators
Note: These operators are not shown in order of precedence.
Operator type Operator symbols Operation performed
Bitwise ~ Bitwise NOT (1's complement)
& Bitwise AND
| Bitwise OR
^ Bitwise XOR
~^ or ^~ Bitwise XNOR
Logical ! NOT
&& AND
|| OR
Reduction & Reduction AND
~& Reduction NAND
| Reduction OR
~| Reduction NOR
^ Reduction XOR
~^ or ^~ Reduction XNOR

Arithmetic + Addition
- Subtraction
- 2's complement
* Multiplication
/ Division
** Exponentiation (*Verilog-2001)
Relational > Greater than
< Less than
>= Greater than or equal to
<= Less than or equal to
== Logical equality (bit-value 1'bX is removed from comparison)
!= Logical inequality (bit-value 1'bX is removed from comparison)
=== 4-state logical equality (bit-value 1'bX is taken as literal)
!== 4-state logical inequality (bit-value 1'bX is taken as literal)
Shift >> Logical right shift
<< Logical left shift
>>> Arithmetic right shift (*Verilog-2001)
<<< Arithmetic left shift (*Verilog-2001)
Concatenation { , } Concatenation
Replication {n{m}} Replicate value m for n times
Conditional ?: Conditional
System Tasks
System tasks are available to handle simple I/O, and various design measurement
functions. All system tasks are prefixed with $ to distinguish them from user tasks and
functions. This section presents a short list of the most often used tasks. It is by no
means a comprehensive list.

 $display - Print to screen a line followed by an automatic newline.

 $write - Write to screen a line without the newline.
 $swrite - Print to variable a line without the newline.
 $sscanf - Read from variable a format-specified string. (*Verilog-2001)
 $fopen - Open a handle to a file (read or write)
 $fdisplay - Write to file a line followed by an automatic newline.
 $fwrite - Write to file a line without the newline.
 fscanf - Read from file a format-specified string. (*Verilog-2001)
 $fclose - Close and release an open file handle.
 $readmemh - Read hex file content into a memory array.
 $readmemb - Read binary file content into a memory array.
 $monitor - Print out all the listed variables when any change value.
 $time - Value of current simulation time.
 $dumpfile - Declare the VCD (Value Change Dump) format output file name.
 $dumpvars - Turn on and dump the variables.
 $dumpports - Turn on and dump the variables in Extended-VCD format.
 $random - Return a random value.

CHAPTER 7
RESULTS
ALU RTL OUTPUTS

ALU SIMULATION
MULTIPLIER 16X16 OUTPUT


VEDIC WALLACE MULTIPLIER 32x32 RTL OUTPUT

Design summary
Time summary


CHAPTER 8
ADVANTAGES
 This multipliers has very high speed of multiplication.

 This multipliers has very high speed of addition,
 It reduces the execution time and increases the speed of execution.
 It reduces the delay in system due to bulk execution.
 It increases the speed of execution.
 The system speed increases.
 It consumes the less power.

CHAPTER 9
APPLICATIONS
 The main application of this multipliers in the systems where the execution
time is very crucial.
 This multipliers are used in less power consuming systems.
 The main application of such system is in digital image processing as
convolution plays an important role in many algorithms in edge detection and
related processes.
 Speeding up convolution and de-convolution using a Hardware Description
Language for design entry not only increases (improves) the level of
abstraction, but also opens new possibilities for using programmable devices.
 Digital electronics control VCRs
 Transaction processing system, ATM
 Personal computers and Workstations
 Medical electronic systems.

CHAPTER 10
CONCLUSION & FUTURE SCOPE
This is effective method of multiplication, i.e. Urdhva- Tiryakbhyam Sutra

based on Vedic mathematics. With this method, the multiplier of any number of bits
can be designed, and show the computational benefits given by Vedic methods. It is a
method for hierarchical multiplier design which clearly indicates the computational
advantages offered by Vedic methods. Since the objective was to reduce the delay, the
computational path delay for the proposed 32x32 bit Vedic Wallace multiplier is
found to be 54.004ns. The Vedic Wallace multiplier is much more efficient than
Vedic multiplier and Array multiplier in terms of execution time (speed) and Area
Delay Product. So we can say Vedic mathematics can be included in the education
systems and help students learn mathematics fast and perform better in less time. In
future, all the research centres are to promote research works in Vedic mathematics.
Vedic Multiplier is understood to be efficient in speed, power and area in

digital plans with respect to further multipliers. Seeing all the designs of it debated
above, we can accomplish that the Vedic multiplier with Urdhva Tiryakbhyam sutra is
perceived as a auspicious technique in terms of speed and area. The work can be
additionalextended with the usage of such multiplier in arithmetic logical unit,
multiply accumulator unit projects and comparing the outcomes with existing designs
for the same.

REFERENCES
[1]. GarimaRawat, KhyatiRathore, SiddharthGoyal,Shefali Kala and Poornima Mittal,
(2015). “Design and Analysis of ALU: Vedic Mathematics”. IEEE Int. Conf. on
Computing, Communication and Automation (ICCCA2015), pp. 1372-1376.
[2]. Rahul Nimje and ShardaMungale, (2014). “Design of arithmetic unit for high-
speed performance using Vedic mathematics”. International Journal of Engineering
Research and Applications, pp. 26-31.
[3]. Poornima M, Shivaraj Kumar Patil, Shivukumar, Shridhar K P and Sanjay H,

(2013). “Implementation of multiplier using Vedic algorithm”.International Journal of
Innovative Technology and Exploring Engineering, Vol. 2, No. 6.
[4]. M. Sowmiya, R. Nirmal Kumar, S.Valarmathy and S. Karthick, (2013). “Design

of Efficient Vedic Multiplier by the analysis of Adders”. International Journal of
Emerging Technology and Advanced Engineering, Vol. 3, No.1.
[5]. PushpalataVerma and K. K. Mehta, (2012). “Implementation of an Efficient

Multiplier based on Vedic Mathematics Using EDA Tool”. International Journal of
Engineering and Advance Technology, Vol.1, No. 5.
[6]. Abhishek Gupta,UtsavMalviya and VinodKapse, (2012). “A novel approach to

design high-speed arithmetic logic unit based on ancient Vedic multiplication
technique”. International Journal of Modern Engineering Research, Vol. 2, No. 4.
[7]. SuchitaKamble and N. N. Mhala, (2012). “VHDL implementation of 8-bit

ALU”.IOSR Journal of Electronics and Communication Engineering, Vol. 1, No. 1.
[8]. PushpalataVerma, (2012). “Design of 4x4 bit Vedic Multiplier using EDA Tool”.
International Journal of Computer Applications, Vol. 48, No. 20.
[9]. AniruddhaKanhe, Shishir Kumar Das and Ankit Kumar Singh, (2012). “Design
and Implementation of Low Power Multiplier Using Vedic Multiplication

Technique”.International Journal of Computer Science and Communication (IJCSC),

Vol. 3, No. 1, pp. 131-132.
[10]. UmeshAkare, T.V. More and R.S. Lonkar, (2012).“Performance Evaluation and
Synthesis of Vedic Multiplier ”. National Conference on Innovative Paradigms in
Engineering & Technology (NCIPET-2012), Proceedings published by International
Journal of Computer Applications (IJCA), pp. 20-23.
[11]. Anvesh Kumar and Ashish Raman, (2010). “Low Power ALU Design by
Ancient Mathematics”. IEEE, 978-1- 4244-5586-7/10
[12]. Parth Mehta and DhanashriGawali, (2009). “Conventional versus Vedic

mathematics method for hardware implementation of a multiplier”.International
Conference on Advances in Computing, Control, and Telecommunication
Technologies, pp. 640-642.
[13]. Ramalatha, M.Dayalan, K D Dharani, P Priya and S Deoborah, (2009). “High

speed energy efficient ALU Design using Vedic Multiplication Techniques”. IEEE
Int. Conf. on Advances in Computational Tools for Engineering Applications
(ACTEA-2009), pp. 600-603.
[14]. Honey DurgaTiwari, GanzorigGankhuyag, Chan Mo Kim and Yong BeomCho,

(2008). “Multiplier design based on Ancient Vedic Mathematics”.IEEE, 978-1-4244-
2599-0/08/$25.00 © 2008.
[15]. Jagadguru Swami Sri Bharati Krishna TirthjiMaharaja, (1986). Vedic

Mathematics.MotilalBanarsidas, Varanasi, India.

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Novel High speed Vedic Multiplier proposal incorporating Adder based on

Quaternary Signed Digit number system

Complex multiplication is of immense importance in Digital Signal Processing

1 Dept. of ECE, SDES

the ancient system of Indian mathematics which has a unique technique of

Multiplier implementation in the gate level (FPGA) using Vedic Mathematics

2 Dept. of ECE, SDES

(16,16)x(16,16) complex multiplier have propagation delay only 4 ns with 6.5 mW

Learning Mathematics is an unpleasant experience to some students mainly

3 Dept. of ECE, SDES

1.2 Vedic Mathematical Formulae

4 Dept. of ECE, SDES

12. Sesanyankena Caramena – The remainders by the last digit.

5 Dept. of ECE, SDES

The multipliers have been proven as an essential component, while designing

To obtain the performance, parallel processing and pipelining techniques are

Microprocessor, Microcontroller, and CPUs.The organization of the paper

6 Dept. of ECE, SDES

1.4 Multiplication of Two Decimal Numbers

To illustrate this scheme, let us consider the multiplication of two decimal

7 Dept. of ECE, SDES

1. Preyesh Dalmia et al (2018): One of the primary features that help us

8 Dept. of ECE, SDES

5. T. Amy Prasanna et al (2019): The rapid Vedic multiplier dependent

9 Dept. of ECE, SDES

use in the digital hardware system. The computation of partial products in

This sector discusses the effort done by researchers on submissions of Vedic

10 Dept. of ECE, SDES

11 Dept. of ECE, SDES

improvement as equated to Vedic multiplier. Animproved ‘Urdhva tiryakbhyam'

12 Dept. of ECE, SDES

and time. The work emphases on speed upgrading of multiplication operation of

13 Dept. of ECE, SDES

3.1 Vedic Wallace Multiplier

Figure 3.1 Multiplication of Two Decimal Numbers: 252x846

14 Dept. of ECE, SDES

Figure 3.2 4x4 Multiplier using Wallace Tree

15 Dept. of ECE, SDES

Figure 3.3 4x4 Multiplier using Vedic Reduction

3.2 Different Multiplier Architectures

16 Dept. of ECE, SDES

17 Dept. of ECE, SDES

Figure 3.4 Schematic Diagram of 4x4 bit Multiplier

18 Dept. of ECE, SDES

3.4.2 Vedic Wallace Multiplier for 16x16 Bit Module

19 Dept. of ECE, SDES

20 Dept. of ECE, SDES

21 Dept. of ECE, SDES

of a conversion module undermines the advantages gained in speed by using QSD. In

5.2. BASIC TERMINOLOGY

Urdhva Tiryagbhyam (UT) Sutra ,The UT sutra is an ancient Vedic

22 Dept. of ECE, SDES

Figure 5.1 2x2 UT multiplier

5.3 Quaternary Signed Digit (QSD number system)

23 Dept. of ECE, SDES

5.4 PROPOSED DESIGN

Block diagram of a 4x4 multiplier is shown in Fig.4.2 In this multiplier, four

Figure 5.2 proposed 4x4 multiplier

24 Dept. of ECE, SDES

5.5 32x32 multiplier

25 Dept. of ECE, SDES

Figure 5.3 proposed 32x32 multiplier

5.6 Proposed adder design based on QSD