88E6218 Datasheet (1 of 3)

MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
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October 7, 2003
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Datasheet
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Doc. No. MV-S101300-01, Rev. A

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ID * SOHO Gateway SOC with
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ARM9E CPU, 10/100 Switch and PHYs
Link Street™ 88E6208/88E6218
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Part 1 of 3: Overview, Pinout, & Electrical Specifications
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12qru965pi-fg1e32yu * IJW Software New Zealand Ltd. * UNDER NDA# 12109742

Document Status
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Advanced This document contains design specifications for initial product development. Specifications may
Information change without notice. Contact Marvell Field Application Engineers for more information.
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Preliminary This document contains preliminary data, and a revision of this document will be published at a
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Information later date. Specifications may change without notice. Contact Marvell Field Application Engi-
neers for more information.
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Final This document contains specifications on a product that is in final release. Specifications may
Information change without notice. Contact Marvell Field Application Engineers for more information.
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Revision Code: Rev. A
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Advanced Technical Publication: 0.83
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Disclaimer
This document provides preliminary information about the products described, and such information should not be used for purpose of final design. Visit the Marvell® web
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Copyright © 2003. Marvell. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, and GalNet are registered trademarks of Marvell. Discovery,
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Fastwriter, GalTis, Horizon, Libertas, Link Street, NetGX, PHY Advantage, Prestera, Raising The Technology Bar, UniMAC, Virtual Cable Tester, and Yukon are trademarks
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of Marvell. All other trademarks are the property of their respective owners.
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Doc. No. MV-S101300-01, Rev. A CONFIDENTIAL Copyright © 2003 Marvell

Page 2 Document Classification: Proprietary Information October 7, 2003, Advanced
SOHO Gateway SOC with ARM9E CPU, 10/100 Switch and PHYs
Part 1: Overview, Pinout, & Electrical Specifications
O VERVIEW F EATURES
The Marvell® Link Street™ 88E6208/88E6218 devices • Single-chip SOHO Gateway/Router CPU and
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are single-chip gateway routers, enabling the design Fast Ethernet QoS Switch with Patented Uni-
of highly integrated gateways for multiple PCs to share MAC™ Architecture
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a common broadband Internet connection with DSL or
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cable modem. Each Link Street device contains an
R OUTER /CPU F EATURES
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ARM9E CPU, 8 kB data cache, 8 kB instruction cache,
SDRAM/Flash memory controller, multi-port 10/100 • ARM9E 32-bit RISC CPU with DSP Instruction
Fast Ethernet switch and PHY transceivers. The Link
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Extensions, @ 133MHz/150MHz, including on-
Street 88E6218 also contains support for Quality of chip 8 kB Instruction Cache plus 8 kB Data Cache
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Service for prioritizing voice, video, and data traffic. and 8 kB Data RAM (88E6218 only)
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Two pin compatible devices exist in the product family: • Integrated SDRAM and Flash Memory Controller
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The 88E6208 is targeted at the low cost but high per- als including DSP
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formance market. Its pinout has been optimized to • SDRAM interface can be 16- or 32-bits (88E6218
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support a complete router on a 2 layer PCB using a only) wide, addressing up to 64 MB in 32-bit and
single SDRAM and Flash. 32 MB in 16-bit memory
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The 88E6218 has a higher CPU clock speed to

• FLASH interface can be 8-, 16- or 32-bits
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(88E6218 only) wide, addressing up to 64 MB

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enhance the performance of software security func-

memory
tions for Virtual Private Networks; an additional MII
• External Chip Select pins are supported (three in
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port for connecting to other networking devices such

as an external switch for port expansion; and features 88E6208, four in 88E6218)
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like QoS, Rate Limiting, and additional memory inter- • Internal IEEE 802.3 MAC, 200 Mbps full-duplex
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face options. (100 Mbps in 88E6208), with optional address fil-
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tering and priority queueing under DMA control

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(Features continued on next page)
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M_A[21:0] NDew SMI (88E6218)

M_A[23:22]
CPU's UniMAC w/ LED2[4:0]
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(88E6218) Dual DMA Switch & PHY Registers PHY LED

LED1[4:0]
M_D[15:0] Controller
LED0[4:0]
SDRAM/Flash 200 Mbit
M_D[31:16]
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Controller w/Qos
(88E6218) 88E6218
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BOOTCSn Port 6's MAC or PHY

100 Mbit Port 5's
MAC Mode
M_CSn[1:0] 88E6208 MAC
88E6218 MII/RMII/SNI
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M_CSn[2] Interface
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(88E6218)
DISABLE_P6
M_STATUS 8 KB Data SRAM
88E6218 10BASE-T
(88E6218) TX4
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Port 4's 100BASE-TX

High Speed Bus
XTAL_IN Look-up MAC Transceiver

8 KB I-Cache w/Auto Crossover RX4
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XTAL_OUT Engine
8 KB D-Cache
Time Slot Memory Controller
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10BASE-T
TX3
4 QoS Queue Controller - 88E6218
Port 3's 100BASE-TX

Queue Controller - 88E6208
MAC Transceiver
ARM-9E RX3
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w/Auto Crossover
JTAG 32-bit CPU 1 Mbit
with Cache Controller Embedded
Memory 10BASE-T
TX2
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88E6218 Port 2's 100BASE-TX

MAC Transceiver
w/Auto Crossover RX2
1/2 Mbit
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RESETn Timers & Interrupts

Embeded
Memory 10BASE-T
88E6208
TX1
Port 1's 100BASE-TX
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Internal DMA
MAC Transceiver
88E6218
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GPIO, LEDs, EEPROM Switch w/Auto Crossover RX1

GPIO[15:0] & Watch Dog Fabric
&
10BASE-T
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Address TX0
Port 0's 100BASE-TX/FX
UART_TX Database
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UART MAC Transceiver

UART_RX w/Auto Crossover RX0
Port 0 Fiber
Enable &
Controls
88E6208/88E6218 Block Diagram
Copyright © 2003 Marvell CONFIDENTIAL Doc. No. MV-S101300-01, Rev. A

October 7, 2003, Advanced Document Classification: Proprietary Information Page 3
• MDC/MDIO master controller for Switch (external • Integrated Voice/Video/Data networking: full
device register access available in 88E6218 only) IEEE 802.1p, IPv4 DiffServ and IPv6 Traffic Class
• Internal DMA controller (88E6218 only) support with four (4) QoS priority queues per port,
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typically supporting Management, Voice, Video,
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• Watchdog timer
and Data streams (88E6218 only)
• UART Serial Port Interface for PC or POTS
• Port-Based VLANs, configurable in any combina-
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Modem & system debug
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• JTAG interface for in-circuit testing and real-time tion
in-circuit emulation, including setting breakpoints • Per port Ingress Rate Limiting and Egress Rate
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& watchpoints Shaping (88E6218 only)
• On-chip packet buffer SRAM
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• Supports up to 2K MAC addresses in multiple
E THERNET S WITCH F EATURES
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address databases
• 7-Port QoS Fast Ethernet Switch with wirespeed • Spanning Tree support: prevents bridge loops for
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non-blocking QoS switch core (6-Port non-QoS
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switch in 88E6208) • Marvell PHYAdvantage™ DSP-based PHYs pro-
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• 5 PHY Ports: Can be used as: vide automatic MDI/MDIX detection and interface,
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– 1 WAN Port: Copper TX or Fiber FX enabling end-user connection of either Straight or

– 4 LAN Copper TX Ports Crossover RJ-45 cables
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• 1 RMII/MII/SNI Port with up to 200 Mbps full- • Four MIB statistics counters per port for remote-
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office network management: TX Frame Count,

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duplex operation, directly connects at full-speed

to another network, such as another switch or RX Frame Count, # Collisions, # CRC Errors
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Wireless LAN (88E6218 only) • Low-power CMOS IC

• 1 internal UniMAC™ double-speed MII port, con- • 216-Pin LQFP
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nects the switch to the CPU’s MAC at 200 Mbps
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full-duplex (in 88E6218, 100 Mbps in 88E6208)
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The following table summarizes the feature differences between the pin compatible 88E6208 and 88E6218
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devices.
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Fe ature 88E62 08 88E62 18

CPU
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Maximum CPU Speed 133 MHz 150 MHz
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8K Data Tightly-Coupled Memory No Yes

SRAM
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Internal DMA No Yes

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External Memory Width 16-bits 32-bits

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Maximum Flash Size 8 MB 64 MB

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External Chip Selects 3 - BootCSn, 4 - BootCSn,

M_CSn[1:0] M_CSn[2:0]
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M_STATUS pin for Flash Memory No1 Yes

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Address Bus pins M_A[21:0] M_A[23:0]

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UniMAC™ QoS No Yes - 4 Queues

UniMAC DA Filter No Yes
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SWITCH
# of Switch Ports 6 7
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External MII No Yes

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Switch QoS No Yes - 4 Queues

Ingress Rate Limiting No Yes
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Egress Rate Shaping No Yes

Max. UniMAC Speed 100 Mbps FD 200 Mbps FD
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Embedded Memory 0.5 Mb 1 Mb

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1. A GPIO pin can be used instead.

Table of Contents
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Preface ................................................................................................................................ 11
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About this Document .............................................................................................................. 11
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Related Documentation ......................................................................................................... 11
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Document Conventions ..........................................................................................................12
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SECTION 1. SIGNAL DESCRIPTION ........................................................................... 13
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1.1 Pin Description..........................................................................................................................15

1.1.1 Pin Type Definitions ..................................................................................................................15
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1.1.2 88E6208 216-Pin LQFP Pin Assignment List - Alphabetical by Signal Name ..........................33
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1.1.3 88E6218 216-Pin LQFP Pin Assignment List - Alphabetical by Signal Name ..........................37
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SECTION 2. RESET AND INITIALIZATION .................................................................... 41

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SECTION 3. FUNCTIONAL DESCRIPTION.................................................................... 45
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3.1 UniMAC Interface Options .......................................................................................................46

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3.1.1 UniMAC Speeds........................................................................................................................46
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3.1.2 Marvell Header Mode ................................................................................................................46
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SECTION 4. ELECTRICAL SPECIFICATIONS................................................................ 48

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4.1 Absolute Maximum Ratings .....................................................................................................48
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4.2 Recommended Operating Conditions ....................................................................................49

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4.3 Notes on Powering Up and Powering Down ..........................................................................49

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4.4 Package Thermal Data..............................................................................................................50

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4.4.1 Thermal Conditions for 216-pin LQFP Package........................................................................50

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4.5 DC Electrical Characteristics ...................................................................................................51

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4.5.1 DC Power Characteristics .........................................................................................................51

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4.5.2 Digital Operating Conditions......................................................................................................52

4.5.3 IEEE DC Transceiver Parameters.............................................................................................54
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4.6 AC Electrical Specifications ....................................................................................................55

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4.6.1 Asynchronous Signals...............................................................................................................55

4.6.2 Reset and Configuration Timing................................................................................................55
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4.6.3 Clock Timing when using a 25 MHz Oscillator ..........................................................................56

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4.6.4 Serial Management Interface Timing ........................................................................................57

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4.6.5 SDRAM/Device Interface Timing...............................................................................................58

4.6.6 GPIO Timing..............................................................................................................................60
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4.6.7 Switch Port 6 MII Rx Timing (PHY Mode) - 88E6218 Only .......................................................61

4.6.8 Switch Port 6 MII Tx Timing (PHY Mode) - 88E6218 Only....................................................... 62
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4.6.9 Switch Port 6 Clock Timing (MAC Mode) - 88E6218 Only ....................................................... 63
4.6.10 Switch Port 6 MII Rx Timing (MAC Mode) - 88E6218 Only...................................................... 64
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4.6.11 Switch Port 6 MII Tx Timing (MAC Mode) - 88E6218 Only ...................................................... 65
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4.6.12 Switch Port 6 Clock Timing - 200 Mbps (MAC Mode) - 88E6218 Only .................................... 66
4.6.13 Switch Port 6 MII Rx Timing (PHY Mode) - 200 Mbps - 88E6218 Only ................................... 67
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4.6.14 Switch Port 6 MII Tx Timing (PHY Mode) - 200 Mbps - 88E6218 Only.................................... 68
4.6.15 Switch Port 6 MII Rx Timing (MAC Mode) - 200 Mbps - 88E6218 Only.................................. 69
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4.6.16 Switch Port 6 MII Tx Timing (MAC Mode) - 200 Mbps - 88E6218 Only ................................... 70
4.6.17 Switch Port 6 SNI Falling Edge Rx Timing - 88E6218 Only ..................................................... 71
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4.6.18 Switch Port 6 SNI Falling Edge Tx Timing - 88E6218 Only...................................................... 72
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4.6.19 Switch Port 6 SNI Rising Edge Rx Timing - 88E6218 Only...................................................... 73
4.6.20 Switch Port 6 SNI Rising Edge Tx Timing - 88E6218 Only ...................................................... 74
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4.6.21 Switch Port 6 RMII Rx Timing - 88E6218 Only......................................................................... 75
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4.6.22 Switch Port 6 RMII Tx Timing - 88E6218 Only ......................................................................... 76

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4.6.23 Two-Wire Serial Interface (TWSI) Timing................................................................................. 77

4.6.24 JTAG Timing............................................................................................................................. 78
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4.7 IEEE AC Parameters................................................................................................................. 79

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SECTION 5. PACKAGE MECHANICAL DIMENSIONS ..................................................... 80

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SECTION 6. ORDER INFORMATION ............................................................................ 82
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6.1 Ordering Part Numbers and Package Markings ................................................................... 82

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List of Tables
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Table 1: Document Conventions ..................................................................................................................... 12
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Table 2: Switch Network Interface................................................................................................................... 16
Table 3: Switch PHY Configuration ................................................................................................................. 17
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Table 4: Switch PHY Status LEDs .................................................................................................................. 18
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Table 5: Regulator, Reference & Clock ........................................................................................................... 19
Table 6: General Purpose I/O - JTAG & Debug .............................................................................................. 20
Table 7:
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SDRAM, FLASH & Device Interface.................................................................................................. 22
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Table 8: Switch Port 6’s Input MII - 88E6218 Only.......................................................................................... 26
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Table 9: Switch Port 6’s Output MII - 88E6218 Only ....................................................................................... 27

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Table 10: External SMI Register Access Interface - 88E6218 Only .................................................................. 29
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Table 11: Power & Ground ................................................................................................................................ 30

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Table 12: CPU Configuration Pins .................................................................................................................... 41

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Table 13: Switch/CPU Interface Configuration Pins .......................................................................................... 42

Table 14: Switch Configuration Pins ................................................................................................................. 42
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Table 15: PHY Configuration Pins..................................................................................................................... 44

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Table 16: Marvell UniMAC Header Options ...................................................................................................... 47
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Table 17: Absolute Maximum Ratings............................................................................................................... 48
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Table 18: Recommended Operating Conditions ............................................................................................... 49

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Table 19: Thermal Conditions for 216-pin LQFP Package................................................................................ 50
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Table 20: DC Power Characteristics ................................................................................................................. 51
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Table 21: Digital Operating Conditions.............................................................................................................. 52
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Table 22: Internal Resistor Description ............................................................................................................. 53

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Table 23: IEEE DC Transceiver Parameters..................................................................................................... 54
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Table 24: Reset and Configuration Timing ........................................................................................................ 55

Table 25: Clock Timing when using a 25 MHz Oscillator .................................................................................. 56
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Table 26: Serial Management Interface Timing................................................................................................. 57

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Table 27: SDRAM/Device Interface Timing....................................................................................................... 58

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Table 28: GPIO Timing...................................................................................................................................... 60

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Table 29: Switch Port 6 MII Receive Timing (PHY Mode) - 88E6218 Only....................................................... 61
Table 30: Switch Port 6 MII Transmit Timing (PHY Mode) - 88E6218 Only...................................................... 62
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Table 31: Switch Port 6 Clock Timing (MAC Mode) - 88E6218 Only ................................................................ 63
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Table 32: Switch Port 6 MII Receive Timing (MAC Mode) - 88E6218 Only ...................................................... 64
Table 33: Switch Port 6 MII Transmit Timing (MAC Mode) - 88E6218 Only ..................................................... 65
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Table 34: Switch Port 6 Clock Timing - 200 Mbps (MAC Mode) - 88E6218 Only ............................................. 66
Table 35: Switch Port 6 MII Receive Timing (PHY Mode) - 200 Mbps - 88E6218 Only.................................... 67
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Table 36: Switch Port 6 MII Transmit Timing (PHY Mode) - 200 Mbps - 88E6218 Only................................... 68
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Table 37: Switch Port 6 MII Receive Timing (MAC Mode) - 200 Mbps - 88E6218 Only ................................... 69
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Table 38: Switch Port 6 MII Transmit Timing (MAC Mode) - 200 Mbps - 88E6218 Only .................................. 70
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Table 39: Switch Port 6 SNI Falling Edge Receive Timing - 88E6218 Only...................................................... 71
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Table 40: Switch Port 6 SNI Falling Edge Transmit Timing - 88E6218 Only..................................................... 72
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Copyright © 2003 Marvell CONFIDENTIAL Doc. No. MV-S101300-01 Rev. A

Table 41: Switch Port 6 SNI Rising Edge Receive Timing - 88E6218 Only ...................................................... 73
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Table 42: Switch Port 6 SNI Rising Edge Transmit Timing - 88E6218 Only ..................................................... 74
Table 43: Switch Port 6 RMII Receive Timing - 88E6218 Only ......................................................................... 75
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Table 44: Switch Port 6 RMII Transmit Timing - 88E6218 Only ........................................................................ 76
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Table 45: Two-Wire Serial Interface (TWSI) Timing .......................................................................................... 77
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Table 46: JTAG Timing...................................................................................................................................... 78
Table 47: IEEE AC Parameters ......................................................................................................................... 79
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Doc. No. MV-S101300-01 Rev. A CONFIDENTIAL Copyright © 2003 Marvell

List of Figures
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Figure 1: 88E6208 216-Pin LQFP Package .................................................................................................. 13
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Figure 2: 88E6218 216-Pin LQFP Package .................................................................................................. 14
Figure 3: CPU & Switch Interconnect ............................................................................................................ 45
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Figure 4: Reset and Configuration Timing ..................................................................................................... 55
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Figure 5: Oscillator Clock Timing................................................................................................................... 56
Figure 6: Serial Management Interface Timing.............................................................................................. 57
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Figure 7: Flash/ROM Read Access ............................................................................................................... 59
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Figure 8: Flash/ROM Write Access ............................................................................................................... 59
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Figure 9: PHY Mode MII Receive Timing ...................................................................................................... 61

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Figure 10: PHY Mode MII Transmit Timing ..................................................................................................... 62

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Figure 11: MAC Clock Timing.......................................................................................................................... 63

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Figure 12: MAC Mode MII Receive Timing...................................................................................................... 64

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Figure 13: MAC Mode MII Transmit Timing..................................................................................................... 65

Figure 14: MAC Clock Timing - 200 Mbps....................................................................................................... 66
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Figure 15: PHY Mode MII Receive Timing - 200 Mbps ................................................................................... 67
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Figure 16: PHY Mode MII Transmit Timing - 200 Mbps .................................................................................. 68
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Figure 17: MAC Mode MII Receive Timing - 200 Mbps................................................................................... 69
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Figure 18: MAC Mode MII Transmit Timing - 200 Mbps.................................................................................. 70

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Figure 19: SNI Falling Edge Receive Timing.................................................................................................. 71
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Figure 20: SNI Falling Edge Transmit Timing.................................................................................................. 72
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Figure 21: SNI Rising Edge Receive Timing ................................................................................................... 73
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Figure 22: SNI Rising Edge Transmit Timing .................................................................................................. 74

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Figure 23: PHY Mode RMII Receive Timing.................................................................................................... 75
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Figure 24: PHY Mode RMII Transmit Timing................................................................................................... 76

Figure 25: Two-Wire Serial Interface Timing ................................................................................................... 77
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Figure 26: JTAG Timing .................................................................................................................................. 78

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Figure 27: Link Street™ 88E6208/88E6218 216-pin LQFP Package with Exposed Die Pad ........................ 80
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Figure 28: Sample Ordering Part Number ....................................................................................................... 82

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Figure 29: 88E6218 Package Marking and Pin 1 Location ............................................................................. 83

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Page 10
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Doc. No. MV-S101300-01 Rev. A

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CONFIDENTIAL
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Document Classification: Proprietary Information

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October 7, 2003, Advanced

Copyright © 2003 Marvell
Preface
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About this Document
Part 1: Overview, Pinout, and Electrical Specifications provides a features list and overview describing the fea-
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tures in the 88E6208/88E6218. It also provides the pin description, pin map, and the electrical specifications. This
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volume is part of a three-volume set that describes the hardware features, the ARM9E CPU and peripheral inter-
faces and the switch core and PHYs of the 88E6208/88E6218.
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The other two manuals in this set are:
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• Part 2: CPU & Peripherals which provides a description of the CPU and each of the peripheral interfaces of
the 88E6208/88E6218 and includes the related register tables.
EN IJ
• Part 3 Switch Core and PHYs which provides a description of the switch core and PHYs of the 88E6208/
ID *
88E6218 and includes the related register tables.

NF 2yu
In addition, Part 1 provides an overview to the complete three-volume set.

CO 1e3
LL -fg
42 .
97 Ltd
Related Documentation
VE 5pi
The following 88E6208/88E6218 documents relate to this manual.

AR 6
10 d
M ru9
12 lan
• 88E6208/88E6218 Part 2: CPU Core and Peripherals, Document Number MV-S101300-02
q
A# Zea
• 88E6208/88E6218 Part 3: Switch Core and PHYs, Document Number MV-S101300-03
12
NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

Document Conventions
42 .
97 Ltd
Table 1: Document Conventions
10 d

12 lan
Document Conventions
The following name and usage conventions are used in this document:
A# Zea
Signal Range A signal name followed by a range enclosed in brackets represents a range of logi-
cally related signals. The first number in the range indicates the most significant bit
NDew
(MSb) and the last number indicates the least significant bit (LSb).
ER e N
Example: DB_Addr[12:0]
ND ar
Active Low Signals n A lower-case n symbol at the end of a signal name indicates that the signal’s active
state occurs when voltage is low.
, U ftw
Example: INTn
AL o
TI W S
State Names State names are indicated in italic font.

Example: linkfail
EN IJ
Register Naming Register field names are indicated in courier blue font.
ID *
Conventions Example: RegInit

NF 2yu
OR
Example: Global_Control<DevEn>,
CO 1e3
Where Global Control represents the register name, and <DevEn> represents the
LL -fg
register field name.
42 .
97 Ltd
Register field bits are enclosed in brackets.
VE 5pi
Example: Field [1:0]

AR 6
10 d
Register addresses are represented in hexadecimal format
M ru9
12 lan
Example: 0x0
q
A# Zea
Reserved: The contents of the register are reserved for internal use only or for future
12
use.
NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

12
q
M ru9
XTAL_OUT
P4_LED2
P4_LED1
P4_LED0
P3_LED2
P3_LED1
P3_LED0
P2_LED2
P2_LED1
P2_LED0
P1_LED2
P1_LED1
P1_LED0
P0_LED2
P0_LED1
P0_LED0
P0_CONFIG
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
VDDO
VDD
VDDO
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDDO
NC
VDD
NC
NC
NC
NC
VDDO
VDD
VDDO
XTAL_IN
VSS
VSS
VSS
RTCK
VSS
AR 6
VE 5pi
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
VSS 1 162 VSS
LL -fg
CONFIG_A 2 161 GPIO[7]
CONFIG_B 3 160 GPIO[8]
CO 1e3
VDD 4 159 GPIO[9]
Copyright © 2003 Marvell

CONTROL_15 5 158 GPIO[10]
October 7, 2003, Advanced

CONTROL_25 6 157 GPIO[11]
NF 2yu
RSET 7 156 GPIO[12]
P0_SDET 8
ID * 155 GPIO[13]
VDDAH 9 154 VSS
P0_RXP 10 153 GPIO[14]
EN IJ
P0_RXN 11 152 GPIO[15]
VDDAL 12 151 VDDO
TI W S
VSS 13 150 NC
P0_TXP 14 149 NC
AL o
P0_TXN 15 148 VDD
P1_TXN 16 147 NC
, U ftw
P1_TXP 17 146 NC
(Exposed Die Pad)

VSS 18 145 VSS
ND ar
VDDAL 19 144 NC
12
q P1_RXN 20 143 NC
ER e N
P1_RXP 21 142 VDDO
VDDAH 22 141 NC
M ru9
P2_RXP 23 140 NC
Figure 1: 88E6208 216-Pin LQFP Package
NDew
P2_RXN 24 139 M_A[17]
AR 6
VDDAL 25 138 M_A[16]
VSS 26 137 VSS
VE 5pi A# Zea
VSS 27 136 NC
P2_TXP 28 135 VDD
LL -fg 12 lan
P2_TXN 29 134 NC
P3_TXN 30 133 VDDO
10 d
(Top View)
P3_TXP 31 132 VDDO
CO 1e3
VSS 32 131 NC
Section 1. Signal Description
97 Ltd
VDDAL 33 130 NC
P3_RXN 34 129 NC
NF 2yu 42 .
88E6208
CONFIDENTIAL
P3_RXP 35 128 NC
216 LQFP
ID *
VDDAH 36 127 VSS
®
®
P4_RXP 37 126 NC
EN IJ
P4_RXN 38 125 NC
VDDAL 39 124 VDDO
VSS 40 123 M_D[8]
TI W S
P4_TXP 41 122 M_D[9]
AL o
Document Classification: Proprietary Information

P4_TXN 42 121 M_D[10]
VDD 43 120 VDD
, U ftw
TRSTn 44 119 M_D[11]
TMS_ARM 45 118 VSS
TDI 46 117 M_D[12]
ND ar
TCK 47 116 M_D[13]
TMS 48 115 VDDO
ER e N
TDO 49 114 M_D[14]
VDDO 50 113 M_D[15]
RESETn 51 112 DQMn[1]/M_A[15]
NDew
UART_RX 52 111 VDDO
UART_TX 53 110 M_CLK_OUT
A# Zea
VSS 54 109 VSS
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
12 lan
10 d
NC
NC
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
WEn
CASn
RASn
97 Ltd
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
M_A[0]
M_A[1]
M_A[2]
M_A[3]
M_A[4]
M_A[5]
M_A[6]
M_A[7]
M_A[8]
M_A[9]
M_D[0]
M_D[1]
M_D[2]
M_D[3]
M_D[4]
M_D[5]
M_D[6]
M_D[7]
M_A[21]
M_A[20]
M_A[19]
M_A[18]
M_A[10]
M_A[11]
M_A[12]
DQMn[0]
M_CSn[1]
M_CSn[0]
42 .
BOOTCSn
M_CLK_IN
CLKSEL[0]
CLKSEL[1]
BA[0]/M_A[13]
BA[1]/M_A[14]
Signal Description
Page 13
Doc. No. MV-S101300-01, Rev. A
42 .
97 Ltd
Figure 2: 88E6218 216-Pin LQFP Package
10 d

12 lan
M_DQMn[3]/M_A[17]
M_DQMn[2]/M_A[16]
DQMn[1]/M_A[15]
A# Zea
M_CLK_OUT
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
M_D[27]
M_D[26]
M_D[25]
M_D[24]
M_D[11]
M_D[12]
M_D[13]
M_D[14]
M_D[31]
M_D[30]
M_D[29]
M_D[28]
M_D[23]
M_D[22]
M_D[21]
M_D[20]
M_D[19]
M_D[18]
M_D[17]
M_D[16]
M_D[10]
M_D[15]
GPIO[7]
GPIO[8]
GPIO[9]
M_D[8]
M_D[9]
NDew
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ER e N
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
ND ar
VSS 163 108 VSS
XTAL_IN 164 107 M_CLK_IN
XTAL_OUT 165, U ftw 106 M_A[12]
VDDO 166 105 M_A[11]
VDD 167 104 M_A[9]
GPIO[6] 168 103 VDDO
AL o
VDDO 169 102 M_A[8]

TI W S
GPIO[5] 170 101 M_A[7]

GPIO[4] 171 100 VDD
GPIO[3] 172 99 M_A[6]
GPIO[2] 173 98 M_A[5]
EN IJ
GPIO[1] 174 97 M_A[4]

GPIO[0] 175 96 M_A[3]
RTCK 176 95 VDDO
ID *
P6_CRS 177 94 M_A[2]

NF 2yu
P6_COL 178 93 M_A[1]

P6_OUTD[3]/P6_MODE[3] 179 92 VSS
P6_OUTD[2]/P6_MODE[2] 180
® 91 M_A[0]
VDD 181 90 M_A[10]
(Exposed Die Pad)
CO 1e3
P6_OUTD[1]/P6_MODE[1] 182 89 VDD

VDDO 183 88 BA[1]/M_A[14]
P6_OUTD[0]/P6_MODE[0] 184 87 BA[0]/M_A[13]
LL -fg
VSS 185 86 VDDO

P6_OUTDV/DISABLE_P6 186 85 M_CSn[0]
42 .
97 Ltd
P6_OUTCLK 187 84 RASn
VE 5pi
P6_INCLK 188 ® 83 CASn

P6_IND[3] 189 82 VSS
P6_IND[2] 190 81 WEn
AR 6
P6_IND[1]
10 d
191 80 VDDO
P6_IND[0] 192
88E6218 79 DQMn[0]
M ru9
12 lan
P6_INDV 193 78 M_D[7]
MDIO 194 77 VDDO
MDC 195 76 M_D[6]
q
A# Zea
P0_CONFIG 196 75 M_D[5]
216 LQFP
12
VSS 197 74 M_D[4]

P0_LED0 198 73 M_D[3]
P0_LED1 199 72 VDD
P0_LED2
P1_LED0
200 (Top View)
NDew 71 M_D[2]
201 70 VSS
VDDO 202 69 M_D[1]
ER e N
P1_LED1 203 68 VDDO

P1_LED2 204 67 M_D[0]
P2_LED0 205 66 M_STATUS
P2_LED1 206 65 BOOTCSn
ND ar
P2_LED2 207 64 M_A[18]

VDD 208 63 M_A[19]
, U ftw
P3_LED0 209 62 M_A[20]

P3_LED1 210 61 M_A[21]
P3_LED2 211 60 VDDO
AL o
VDDO 212 59 M_A[22]

TI W S
P4_LED0 213 58 M_A[23]

P4_LED1 214 57 M_CSn[1]
P4_LED2 215 56 M_CSn[2]
VSS 216 55 VSS
EN IJ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
1
2
3
4
5
6
7
8
9
ID *
TMS
TMS_ARM
P0_RXP
P0_TXP
P1_TXP
P1_RXP
P2_RXP
P2_TXP
P3_TXP
P3_RXP
P4_RXP
P4_TXP
TCK
VDDAH
P0_RXN
P0_TXN
P1_RXN
VDDAH
P2_RXN
P2_TXN
P3_TXN
P3_RXN
VDDAH
P4_RXN
P4_TXN
VDDAL
VDDAL
VDDAL
VDDAL
VDDAL
RESETn
VSS
CONFIG_A
CONFIG_B
VSS
VSS
VSS
VSS
VSS
VSS
VSS
UART_RX
VDD
P1_TXN
VDD
CONTROL_15
CONTROL_25
TRSTn
TDI
TDO
VDDO
RSET
P0_SDET
UART_TX
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

Signal Description
Pin Description
1.1 Pin Description
42 .
97 Ltd
10 d

1.1.1 Pin Type Definitions
12 lan
A# Zea
P in Typ e D ef i ni t i on
H Input with hysteresis
NDew
I/O Input and output
ER e N
I Input only
ND ar
O Output only
, U ftw
PU Internal pull-up
AL o
PD Internal pull-down
TI W S
D Open drain output

EN IJ
Z Tri-state output
ID *
mA DC sink capability
NF 2yu
CO 1e3
LL -fg
42 .
97 Ltd
VE 5pi
AR 6
10 d
M ru9
12 lan
q
A# Zea
12
NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

42 .
97 Ltd
Table 2: Switch Network Interface
10 d

21 6- Pin Name Pin D escr ip tio n
12 lan
L QF P Ty pe
A# Zea
Package
Pin #
NDew
37 P[4:0]_RXP Typically Receiver input − Positive. P[4:0]_RXP connects directly to the receiver
35 Input magnetics. If the port is configured for 100BASE-FX mode (Port 0
ER e N
23 only), RXP connects directly to the fiber-optic receiver’s positive output.
ND ar
21 For lowest power, all unused port RXP pins should be tied to VSS.
10 , U ftw These pins can become outputs if Auto MDI/MDIX is enabled (See
Part 3 of the 3 part 88E6208/88E6218 datasheet for details).
AL o
TI W S
38 P[4:0]_RXN Typically Receiver input − Negative. P[4:0]_RXN connects directly to the

34 Input receiver magnetics. If the port is configured for 100BASE-FX mode
EN IJ
24 (Port 0 only), RXN connects directly to the fiber-optic receiver’s nega-

ID *
20 tive output. For lowest power, all unused port RXN pins should be tied
NF 2yu
11 to VSS. These pins can become outputs if Auto MDI/MDIX is enabled

(See Part 3 of the 3 part 88E6208/88E6218 datasheet for details).
CO 1e3
41 P[4:0]_TXP Typically Transmitter output − Positive. P[4:0]_TXP connects directly to the

LL -fg
42 .
31 Output transmitter magnetics. If the port is configured for 100BASE-FX mode
97 Ltd
VE 5pi
28 (Port 0 only), P0_TXP connects directly to the fiber-optic transmitter’s

17 positive input. For lowest power, all unused port TXP pins should be
AR 6
10 d
14 tied to VSS. These pins can become inputs if Auto MDI/MDIX is
M ru9
12 lan
enabled (See Part 3 of the 3 part 88E6208/88E6218 datasheet for
q
A# Zea
details).
12
Transmitter output − Negative. P[4:0]_TXN connects directly to the

42 P[4:0]_TXN Typically
NDew
30 Output transmitter magnetics. If the port is configured for 100BASE-FX mode
ER e N
29 (Port 0 only) P0_TXN connects directly to the fiber-optic transmitter’s

16 negative input. For lowest power, all unused port TXN pins should be
ND ar
15 tied to VSS. These pins can become inputs if Auto MDI/MDIX is

, U ftw
enabled (See Part 3 of the 3 part 88E6208/88E6218 datasheet for

details).
AL o
TI W S
8 P0_SDET Input Signal Detect input. If Port 0 is configured for 100BASE-FX mode,
EN IJ
P0_SDET indicates whether a signal is detected by the fiber-optic

transceiver. A positive level indicates that a signal is detected.
ID *
NF 2yu
If Port 0 is configured for 10/100BASE-T mode, P0_SDET is not used

but it cannot be left floating since this pin does not contain internal
CO 1e3
resistors. An unused P0_SDET pin can be tied to VSS.

LL -fg
VE 5pi
AR 6
M ru9
q
12

Signal Description
Pin Description
42 .
97 Ltd
Table 3: Switch PHY Configuration
10 d

21 6- Pin Name Pin De scrip tio n
12 lan
LQ F P Typ e
A# Zea
Package
Pin #
NDew
196 P0_CONFIG Input Port 0 Configuration. The P0_CONFIG pin is used to set the default
configuration for Port 0 by connecting the pin to other device pins as
ER e N
defined in Table 15, “PHY Configuration Pins,” on page 44.
ND ar
Ports 1, 2, 3 and 4 default configuration is Auto-Negotiation enabled.
, U ftw Any port’s default configuration can be modified by accessing the PHY
registers by a CPU. Fiber mode vs. copper mode cannot be configured
AL o
in this way, however. Fiber vs. copper must be selected at Reset by

TI W S
using the P0_CONFIG pins.

EN IJ
The P0_CONFIG pin is configured after Reset and contains an internal

pull down resistor so it can be left floating to select Auto-Negotiation.
ID *
NF 2yu
2 CONFIG_A Input Global Configuration A. This global configuration pin is used to set the
CO 1e3
default LED mode and Far End Fault Indication (FEFI) mode by con-
necting these pins to other device pins as defined in Table 15, “PHY
LL -fg
Configuration Pins,” on page 44.
42 .
97 Ltd
The LED modes are defined in Part 3 of the 3 part 88E6208/88E6218
VE 5pi
datasheet.
AR 6
10 d
M ru9
12 lan
The CONFIG_A pin is configured after Reset. It contains an internal
pull-up resistor so it can be left floating to select the VDDO options.
q
A# Zea
12
3 CONFIG_B Input Global Configuration B. This global configuration pin is used to set the
NDew
default mode for Auto-Crossover, the PHY driver type and Energy
ER e N
Detect by connecting these pins to other device pins as defined in

Table 15, “PHY Configuration Pins,” on page 44.
ND ar
Auto crossover and Energy Detect are defined in Part 3 of the 3 part
, U ftw
88E6208/88E6218 datasheet.
AL o
The CONFIG_B pin is configured after Reset. It contains an internal

TI W S
pull-up resistor so it can be left floating to select the VDDO options.

EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

42 .
97 Ltd
Table 4: Switch PHY Status LEDs
10 d

216- Pin Name Pin Des cription
12 lan
LQ FP Typ e
A# Zea
Package
Pin #
NDew
215 P[4:0]_LED2 Output Parallel LED outputs − one for each port. This active low LED pin
211 directly drives an LED in Parallel LED mode. It can be configured to
ER e N
207 display many options.
ND ar
204
200 , U ftw P[1:0]_LED2 can be used to configure certain parameters in the PHY.
P[4:0]_LED2 are driven active low whenever RESETn is active low.
AL o
TI W S
See Part 3 of the 3 part 88E6208/88E6218 datasheet for LED display

and configuration options.
EN IJ
ID *
214 P[4:0]_LED1 Output Parallel LED outputs − one for each port. This active low LED pin
NF 2yu

206 display many options.
CO 1e3
203
199 P[1:0]_LED1 can be used to configure certain parameters in the PHY.
LL -fg
42 .
97 Ltd
VE 5pi

AR 6
10 d
M ru9
12 lan
Parallel LED outputs − one for each port. This active low LED pin
q
A# Zea
213 P[4:0]_LED0 Output
12

205 display many options. NDew
201
ER e N
198 P[1:0]_LED0 can be used to configure certain parameters in the PHY.

ND ar
, U ftw

AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

Signal Description
Pin Description
42 .
97 Ltd
Table 5: Regulator, Reference & Clock
10 d

216 - Pi n Na me Pin De scr ip tio n
12 lan
LQ FP Ty pe
A# Zea
Package
Pin #
NDew
7 RSET Analog Resistor reference. A 2.0 kΩ 1% resistor is placed between the RSET
and VSS. This resistor is used to set an internal bias reference current.
ER e N
ND ar
5 CONTROL_
, U ftw Analog Voltage control to external 1.5V regulator. This signal controls an exter-
15 nal PNP transistor to generate the 1.5V power supply for the VDD and
VDDAL pins.
AL o
TI W S
6 CONTROL_ Analog Voltage control to external 2.5V regulator. This signal controls an exter-
EN IJ
25 nal PNP transistor to generate the 2.5V power supply for the VDDO
and VDDAH pins.
ID *
NF 2yu
164 XTAL_IN Input 25 MHz system reference clock input provided from the board. The
CO 1e3
clock source can come from an external crystal or an external oscilla-

tor. This is the only clock required as it is used for the Switch, the
LL -fg
PHYs, and the CPU. Refer to section 4.6.3 for XTAL_IN timing require-
42 .
97 Ltd
ments.
VE 5pi
AR 6
10 d
165 XTAL_OUT Output System reference clock output provided to the board. This output can
M ru9
12 lan
only be used to drive an external crystal. It cannot be used to drive
external logic. If an external oscillator is used this pin should be left
q
A# Zea
12
unconnected.
NDew
51 RESETn Input Hardware reset. Active low. The 88E6208/88E6218 is configured dur-
ER e N
ing reset. When RESETn is low all configuration pins become inputs
and the value seen on these pins is latched on the rising edge of
ND ar
RESETn or some time after. Refer to section 4.6.2 of the AC Electrical

, U ftw
Specifications for Reset and Configuration Timing details.

AL o
TI W S
59 CLKSEL[1:0] Typically CPU clock speed selection (for Rev. A and Rev. B of the 88E6208
58 Output only).
EN IJ
(88E6208 only)
Input Only During normal operation these pins are outputs driving undefined data.
ID *
NF 2yu
During During reset these pins become inputs and the value seen on these
RESETn pins is latched on the rising edge of RESETn or some time after. See
Table 13, “Switch/CPU Interface Configuration Pins,” on page 42 for
CO 1e3
configuration information.
LL -fg
These pins become no connect (NC) on future revisions of the

VE 5pi
88E6208, and the CPU clock speed selection will move to M_A[17:16].
To maintain compatibility of the 88E6208, board designs should sup-
AR 6
port CPU clock speed selection on both the CLKSEL[1:0] and

M ru9
M_A[17:16] pins.
q
12

42 .
97 Ltd
Table 6: General Purpose I/O − JTAG & Debug
10 d

12 lan
LQ FP Typ e
A# Zea
Package
Pin #
NDew
152 GPIO[15:0] I/O General Purpose I/O. These pins can be programmed to perform many
153 functions besides I/O pins under software control. These include Serial
ER e N
155 EEPROM interface, Software controlled LEDs, LEDs for switch Port 5,
ND ar
156 Interrupt inputs to the CPU, and Watch Dog Reset output. Not all func-
157 , U ftw tions can be supported at one time. Refer to "Section 5 GPIO Inter-
158 face", in Part 2 of the 3 part 88E6208/88E6218 datasheet for more
AL o
159 information on which GPIO pins can perform a particular function.

TI W S
160
GPIO[15:0] are tri-stated during RESETn and are internally pulled high
EN IJ
161 so they can be left unconnected if not used.

168
ID *
NF 2yu
170
171
172
CO 1e3
173
174
LL -fg
42 .
175
97 Ltd
VE 5pi
AR 6
10 d
52 UART_RX Input UART Receive Input. This is the input to the device’s general purpose
M ru9
12 lan
UART. UART_RX is internally pulled high so it can be left unconnected
if not used.
q
A# Zea
12
53 UART_TX Output UART Transmit Output. This is the output from the device’s general
NDew
purpose UART.
ER e N
47 TCK Input JTAG test clock. TCK is internally pulled high so it can be left uncon-
ND ar
nected if not used.

, U ftw
AL o
46 TDI Input JTAG test data input. TDI is internally pulled high so it can be left
TI W S
unconnected if not used.

EN IJ
49 TDO Output JTAG test data output.

ID *
NF 2yu
48 TMS Input JTAG test mode select for the device’s pins and for the PHY. TMS is
internally pulled high so it can be left unconnected if not used.
CO 1e3
LL -fg
45 TMS_ARM Input JTAG test mode select for the ARM Event Trace Manager. TMS_ARM
is internally pulled high so it can be left unconnected if not used.
VE 5pi
AR 6
M ru9
q
12

Signal Description
Pin Description
Table 6: General Purpose I/O − JTAG & Debug (Continued)
42 .
97 Ltd
216 - Pi n Na me Pi n Des cription
LQ FP Typ e
10 d

12 lan
Package
Pin #
A# Zea
44 TRSTn Input Active low JTAG Test Interface and ARM Event Trace Manager reset.
TRSTn is internally pulled high.
NDew
ER e N
If the JTAG Test Interface is not being used, TRSTn must be low:
ND ar
- If the JTAG Test Interface will never be used, TRSTn can be tied to
, U ftw VSS.
AL o
- If the JTAG Test Interface will be used periodically (like for manufac-
TI W S
turing testing or software debug), TRSTn can be pulled low to VSS

using a 10 kΩ resistor.
EN IJ
ID *
176 RTCK Output Return Clock. When using the ARM’s JTAG controller (for the ARM’s
NF 2yu
Event Trace Manager), this output provides the return clock synchroni-
zation signal for off-chip debug device (for example Multi-ICE). The
CO 1e3
debug device issues a TCK signal that cannot not progress to next
TCK until RTCK is received.
LL -fg
42 .
97 Ltd
VE 5pi
AR 6
10 d
M ru9
12 lan
q
A# Zea
12
NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

42 .
97 Ltd
Table 7: SDRAM, FLASH & Device Interface
10 d

21 6- Pin Name Pin Desc rip t ion
12 lan
L QF P Type
A# Zea
Package
Pin #
NDew
110 M_CLK_OUT Output Memory clock output. Connect this pin to the CLK (clock) pin on
SDRAM memories and to the M_CLK_IN pin described below. The fre-
ER e N
quency of this pin is the frequency of the CPU core and they run syn-
ND ar
chronously.
, U ftw
107 M_CLK_IN Input Memory clock input. Connect this pin to the M_CLK_OUT pin
AL o
described above. It is used to adjust the read timing when reading the
TI W S
data from the SDRAM memories.

EN IJ
65 BOOTCSn Output Boot chip select (typically FLASH), active low. Connect this pin to the
ID *
boot FLASH memory CEn (chip enabled) pin.

NF 2yu
CO 1e3
56 M_CSn[2] Output SDRAM or device chip select, active low. Each chip select can be pro-
grammed by software to be an SDRAM type using multiplexed
LL -fg
(88E6218 only) addresses or a non-multiplexed device like FLASH or some other
42 .
97 Ltd
device. Each chip select has its own address space and can have inde-
VE 5pi
57 M_CSn[1:0] Output
pendent timing.
85
AR 6
10 d
M ru9
12 lan
66 M_STATUS Input Memory Status. This pin accepts Ready/Busy# status indication for
FLASH memory devices so software can determine when the FLASH
q
A# Zea
12
(88E6218 only) device is ready for the next write operation. The value on this pin is
readable in the memory controller’s Control and Status register.
NDew
88E6208 does not support the M_STATUS pin. A GPIO pin can be
ER e N
used instead.
ND ar
M_STATUS contains a internal pull-up resistor so the pin can be left

, U ftw
unconnected if not used.

AL o
TI W S
84 RASn/ Output Row address strobe, active low. Connect this pin to RASn (row address
OEn strobe) on SDRAM memories and to OEn (output enable) on device
EN IJ
(FLASH) memories.
ID *
NF 2yu
83 CASn/ Output Column address strobe, active low. Connect this pin to CASn (column
WPn address strobe) on SDRAM memories and to WPn (write protect) on
CO 1e3
device (FLASH) memories.

LL -fg
81 WEn Output Write enable, active low. Connect this pin to WEn (write enable) on
VE 5pi
SDRAM and device (FLASH) memories.

AR 6
M ru9
q
12

Signal Description
Pin Description
Table 7: SDRAM, FLASH & Device Interface (Continued)
42 .
97 Ltd
2 16- Pin Name Pin Desc ription
L QF P Typ e
10 d

12 lan
Package
Pin #
A# Zea
106 M_A[12:0] Typically Memory Address. Connect these pin to the multiplexed address pins
105 Output on SDRAM memories and to address 12:0 on device (FLASH) memo-
NDew
90 ries.
ER e N
104 Input only
102 during M_A[12:0] contain internal resistors (most are internal pull-ups, but
ND ar
RESETn some are internal pull-downs) that are used to configure the 88E6208/
101
, U ftw 88E6218 during a hardware reset. When RESETn is asserted, these
99 pins become inputs and the desired configuration value is latched at
AL o
98 the rising edge of RESETn. See Table 12, “CPU Configuration Pins,”
TI W S
97 on page 41 and Table 14, “Switch Configuration Pins,” on page 42 for

96 configuration information.
EN IJ
94
93
ID *
NF 2yu
91
88 BA[1:0]/ Typically Bank Select. Connect these pin to the bank select pins on SDRAM
CO 1e3
87 M_A[14:13] Output memories and to address 14:13 on device (FLASH) memories.

LL -fg
Input only BA[1:0] contain internal resistors that are used to configure the
42 .
97 Ltd
VE 5pi
during 88E6208/88E6218 during a hardware reset. When RESETn is

RESETn asserted, these pins become inputs and the desired configuration
AR 6
10 d
value is latched at the rising edge of RESETn. See Table 14, “Switch
M ru9
12 lan
Configuration Pins,” on page 42 for configuration information.
q
A# Zea
139 DQMn[3:2]/ Typically Date byte enables, active low. Connect these pins to DQMn[3:2] (byte
12
138 M_A[17:16], Output enables) on SDRAM memories and to address 17:16 on device
(FLASH) memories. NDew
(DQMn[3:2] Input only
ER e N
88E6218 only) during For 88E6208, DQMn[3] becomes M_A[17], and DQMn[2] becomes
RESETn M_A[16].
ND ar
, U ftw
See Table 12, “CPU Configuration Pins,” on page 41 for M_A[17] and
M_A[16] details.
AL o
TI W S
112 DQMn[1:0]/ Typically Date byte enables, active low. Connect these pins to DQMn[1:0] (byte
79 M_A[15], Output enables) on SDRAM memories and to address 15 on device (FLASH)
BYTEn memories.
EN IJ
ID *
For 88E6208/88E6218, DQMn[1] becomes M_A[15]. DQMn[0]

NF 2yu
becomes BYTEn which can be used to configure the (FLASH) device

to word or byte mode.
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

42 .
97 Ltd
21 6- Pin Name Pin Desc rip t ion
L QF P Type
10 d

12 lan
Package
Pin #
A# Zea
58 M_A[23:22] Typically Memory address bits 23:22.
59 Output
NDew
(88E6218 only) For 88E6218, connect M_A[23:22] to address 23:22 on device
ER e N
Input only (FLASH) memories (these pins are not used for SDRAMs).
during
ND ar
RESETn M_A[23:22] contain internal resistors that are used to configure the
, U ftw 88E6218 during a hardware reset. When RESETn is asserted, these
pins become inputs and the desired configuration value is latched at
AL o
the rising edge of RESETn. See Table 12, “CPU Configuration Pins,”
TI W S
on page 41 for configuration information.

61 M_A[21:18] Typically Memory address bits 21:18.
EN IJ
62 Output
ID *
63 For 88E6208/88E6218, connect M_A[21:18] to address 21:18 on

NF 2yu
64 Input only device (FLASH) memories (these pins are not used for SDRAMs).
during
CO 1e3
RESETn M_A[21:18] contain internal resistors that are used to configure the
88E6208/88E6218 during a hardware reset. When RESETn is
LL -fg
asserted, these pins become inputs and the desired configuration
42 .
97 Ltd
VE 5pi
value is latched at the rising edge of RESETn. See Table 13, “Switch/
CPU Interface Configuration Pins,” on page 42 for configuration infor-
AR 6
10 d
mation.
M ru9
12 lan
150 M_D[31:16] I/O Memory data. For the 88E6218, these pins form the upper 16-bits of a
q
A# Zea
149 32-bit wide memory data bus used to connect the ARM CPU to exter-
12
147 (88E6218 only) nal SDRAM, FLASH and/or other devices.

146 NDew
144 M_D[31:0] is used for 32-bit wide SDRAM or devices. Make sure the
ER e N
143 device width used is correctly configured in the memory controller’s

141 registers.
ND ar
140
, U ftw
136
AL o
134
TI W S
131
130
EN IJ
129
ID *
128
NF 2yu
126
125
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

Signal Description
Pin Description
42 .
97 Ltd
2 16- Pin Name Pin Desc ription
L QF P Typ e
10 d

12 lan
Package
Pin #
A# Zea
113 M_D[15:0] I/O Memory data. For the 88E6218, these pins form the lower 16 bits of a
114 32-bit wide memory data bus used to connect the ARM CPU to exter-
NDew
116 nal SDRAM, FLASH and/or other devices.
ER e N
117
119 For the 88E6208, these pins form the complete 16-bit wide memory
ND ar
121 data bus used to connect the ARM CPU to external SDRAM, FLASH
122
, U ftw and/or other devices.
123
AL o
If the device (FLASH or other device) is 8-bits wide, connect it to

TI W S
78 M_D[7:0]. If the SDRAM or device is 16-bits wide, connect it to

76 M_D[15:0].
EN IJ
75
74
ID *
NF 2yu
73
71
CO 1e3
69
67
LL -fg
42 .
97 Ltd
VE 5pi
AR 6
10 d
M ru9
12 lan
q
A# Zea
12
NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

42 .
97 Ltd
Table 8: Switch Port 6’s Input MII - 88E6218 Only
10 d

216 - Pin Name Pi n Des cription
12 lan
LQ FP Typ e
A# Zea
Package
Pin #
NDew
188 P6_INCLK I/O Input Clock. P6_INCLK is a reference for P6_INDV and P6_IND[3:0].
The direction and speed of P6_INCLK is determined by P6_MODE[3:0]
ER e N
at the end of RESETn.
ND ar
, U ftw If the port is in PHY Mode, P6_INCLK is an output. In this mode the fre-
quency of the clock will be 25 MHz if the port is in 100BASE-X mode,
AL o
and 2.5 MHz if the port is in 10BASE-T mode and 50 MHz for
TI W S
200BASE mode. P6_INCLK is not used in RMII mode.

EN IJ
If the port is in MAC Mode, P6_INCLK is an input. In this mode the fre-
quency of the clock can be anywhere from DC to 25 MHz or 50 MHz
ID *
NF 2yu
although it should be 25 MHz for 100BASE-X mode and 2.5 MHz for
10BASE-T mode. 50 MHz is needed for 200BASE mode. P6_INCLK is
not used in RMII mode.
CO 1e3
P6_INCLK is tri-stated during RESETn and it is internally pulled high so

LL -fg
42 .
the pin can be left unconnected if not used.
97 Ltd
VE 5pi
AR 6
10 d
189 P6_IND[3:0] Input Input Data. P6_IND[3:0] receives the data nibble to be transmitted into
M ru9
12 lan
190 the switch in 100BASE-X and 10BASE-T modes. P6_IND[3:0] is syn-
191 chronous to P6_INCLK (or P6_OUTCLK in RMII mode). These pins
q
A# Zea
192 are inputs regardless of the port’s mode (i.e., PHY mode or MAC
12
mode). Only P6_IND0 is used when SNI mode is selected.

NDew
P6_IND[1:0] are used when RMII mode is selected.
ER e N
P6_IND[3:0] are internally pulled high via resistor so the pins can be
left unconnected when they are not used.
ND ar
, U ftw
193 P6_INDV Input Input Data Valid. When P6_INDV is asserted high, data on P6_IND[3:0]
AL o
is encoded and transmitted into the switch. P6_INDV must be synchro-

TI W S
nous to P6_INCLK (or P6_OUTCLK in RMII mode).

EN IJ
P6_INDV is internally pulled low via resistor so the pin can be left
unconnected when it is not used.
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

Signal Description
Pin Description
Table 9: Switch Port 6’s Output MII - 88E6218 Only
42 .
97 Ltd
216 - Pi n Na me Pi n Des cription
LQ FP Typ e
10 d

12 lan
Package
Pin #
A# Zea
187 P6_OUTCLK I/O Output Clock. P6_OUTCLK is a reference for P6_OUTDV,
P6_OUTD[3:0], and P6_INDV and P6_IND[1:0] in RMII mode. The
NDew
direction and speed of P6_OUTCLK is determined by P6_MODE[3:0]
at the end of RESETn.
ER e N
ND ar
If the port is in PHY Mode, P6_OUTCLK is an output. In this mode the
, U ftw frequency of the clock will be 25 MHz if the port is in 100BASE-X
mode, and 2.5 MHz if the port is in 10BASE-T mode and 50 MHz for
AL o
200BASE mode and RMII mode.

TI W S
If the port is in MAC Mode, P6_OUTCLK is an input. In this mode the

EN IJ
frequency of the clock can be anywhere from DC to 25MHz or 50 MHz

although it should be 25 MHz for 100BASE-X mode and 2.5 MHz for
ID *
10BASE-T mode and 50 MHz for 200BASE mode. MAC mode RMII
NF 2yu
mode is not supported.

CO 1e3
P6_OUTCLK is tri-stated during RESETn and it is internally pulled high

so the pin can be left unconnected if not used.
LL -fg
42 .
97 Ltd
VE 5pi
179 P6_OUTD[3:0]/ Normally Output Data. Data transmitted from the switch is decoded and pre-
AR 6
10 d
180 P6_MODE[3:0] Output sented on P6_OUTD[3:0] pins synchronous to P6_OUTCLK. These
M ru9
12 lan
182 pins are outputs regardless of the port’s mode (i.e., PHY or MAC
184 Input only mode). Only P6_OUTD0 contains meaningful data when SNI mode is
q
A# Zea
when selected. P6_OUTD[1:0] are used when RMII mode is selected.
12
RESETn
is low
NDew
During RESETn these internally pulled high pins are tri-stated and
used to latch in the desired operating mode for the port as described in
ER e N
Table 14.
ND ar
186 P6_OUTDV/ Output Output Data Valid. When P6_OUTDV is asserted high, data transmitted
, U ftw
DISABLE_P6 from the switch is decoded and presented on P6_OUTD[3:0].

AL o
P6_OUTDV is synchronous to P6_OUTCLK.

TI W S
During RESETn this internally pulled high pin is tri-stated and used to
EN IJ
latch in the enable value for switch Port 6. If this pin is high or left
unconnected during RESETn Port 6 will be disabled. Use a 4.7 kΩ
ID *
NF 2yu
resistor to VSS to enable Port 6.

CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

Table 9: Switch Port 6’s Output MII - 88E6218 Only (Continued)
42 .
97 Ltd
LQ FP Typ e
10 d

12 lan
Package
Pin #
A# Zea
177 P6_CRS I/O Carrier Sense. After RESETn, P6_CRS becomes an output if PHY
Mode is selected for this port. It remains an input if MAC Mode is
NDew
selected. P6_CRS asserts (or is expected to be asserted) when the
ER e N
receive data path is non-idle. In half-duplex mode P6_CRS is also
asserted (or is expected to be asserted) during transmission. P6_CRS
ND ar
is asynchronous to P6_OUTCLK and P6_INCLK.
, U ftw
P6_CRS is tri-stated during RESETn and it is internally pulled low so
AL o

TI W S
178 P6_COL I/O Collision. After RESETn, P6_COL becomes an output if PHY Mode is
EN IJ
selected for this port. It remains an input if MAC Mode is selected.

ID *
P6_COL asserts (or is expected to be asserted) only in half-duplex

NF 2yu
mode when both the transmit and receive paths are non-idle. In full-
duplex mode, P6_COL is always low (or it is ignored). P6_COL is asyn-
CO 1e3
chronous to P6_OUTCLK and P6_INCLK.

LL -fg
P6_COL is tri-stated during RESETn and it is internally pulled low so
42 .
97 Ltd
VE 5pi

AR 6
10 d
M ru9
12 lan
q
A# Zea
12
NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

Signal Description
Pin Description
42 .
97 Ltd
Table 10: External SMI Register Access Interface - 88E6218 Only
10 d

216 - Pin Name Pin De scrip tio n
12 lan
LQ FP Typ e
A# Zea
Package
Pin #
NDew
195 MDC Output MDC is the management data clock reference for the serial manage-
ment interface (SMI). A continuous clock stream is not generated.
ER e N
MDC occurs only when an SMI operation is taking place. MDC’s fre-
ND ar
quency is the CPU’s core clock frequency divided by 64 (2.08 MHz @
, U ftw 133 MHz CPU speed).
AL o
The SMI is used to access the registers in external devices like PHYs
TI W S
that could be connected to Port 6’s MII.

EN IJ
MDC is internally pulled high via a resistor so it can be left floating

when unused.
ID *
NF 2yu
194 MDIO I/O MDIO is the management data. MDIO is used to transfer management
CO 1e3
data in and out of the device synchronously to MDC. This pin requires
an external pull-up resistor in the range of 1.5 kΩ to 10 kΩ.
LL -fg
42 .
97 Ltd
The 88E6218 internal switch uses 16 of the 32 possible SMI port
VE 5pi
addresses. The 16 that are used are selectable using the M_A[3] con-
AR 6
10 d
figuration pin (see Table 14 for details).
M ru9
12 lan
MDIO is internally pulled high via a resistor so it can be left floating
q
A# Zea
when unused.
12
NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

42 .
97 Ltd
Table 11: Power & Ground
10 d

12 lan
216- Pin Name Pi n Des cription
LQ FP Typ e
A# Zea
Package
Pin #
NDew
50 VDDO Power 3.3 volt Power to digital I/O.
ER e N
60
68
ND ar
77 , U ftw
80
86
AL o
95
TI W S
103
111
EN IJ
115
ID *
124
NF 2yu
132
133
CO 1e3
142
151
LL -fg
166
42 .
97 Ltd
169
VE 5pi
183
202
AR 6
10 d
M ru9
12 lan
212
q
A# Zea
12
9 VDDAH Power 2.5 volt Power to analog core.

22 NDew
36
ER e N
12 VDDAL Power 1.5 volt Power to analog core.

ND ar
19
, U ftw
25
33
AL o
39
TI W S
EN IJ
4 VDD Power 1.5 volt Power to digital core.

43
ID *
72
NF 2yu
89
100
CO 1e3
120
135
LL -fg
148
VE 5pi
167
181
AR 6
208
M ru9
q
12

Signal Description
Pin Description
Table 11: Power & Ground (Continued)
42 .
97 Ltd
216 - Pin Name Pin De scrip tio n
LQ FP Typ e
10 d

12 lan
Package
Pin #
A# Zea
1 VSS Ground Ground to digital I/O and core.
13
NDew
18
ER e N
26
27
ND ar
32
40
, U ftw
54
AL o
55
TI W S
70
82
EN IJ
92
108
ID *
NF 2yu
109
118
CO 1e3
127
137
LL -fg
145
42 .
154
97 Ltd
VE 5pi
162
163
AR 6
10 d
M ru9
12 lan
185
197
q
A# Zea
216
12
Exposed VSS Ground

NDew
Solder the exposed die pad to the PCB for best thermal and electrical
Die Pad performance. Contact Marvell FAEs for information on PCB layout rec-
ER e N
ommendations.
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

Table 11: Power & Ground (Continued)
42 .
97 Ltd
216- Pin Name Pi n Des cription
LQ FP Typ e
10 d

12 lan
Package
Pin #
A# Zea
56 NC No 88E6208 Only. Do not connect these pins to anything. These pins are
58 Connect not to be connected.
NDew
59
ER e N
66
125
ND ar
126
128
, U ftw
129
AL o
130
TI W S
131
134
EN IJ
136
140
ID *
NF 2yu
141
143
CO 1e3
144
146
LL -fg
147
42 .
149
97 Ltd
VE 5pi
150
177
AR 6
10 d
M ru9
12 lan
178
179
q
A# Zea
180
12
182
184 NDew
186
ER e N
187
188
ND ar
189
, U ftw
190
191
AL o
192
TI W S
193
194
EN IJ
195
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

Signal Description
Pin Description
1.1.2 88E6208 216-Pin LQFP Pin Assignment List - Alphabetical by

Signal Name
42 .
97 Ltd
Pin # Pin Name Pin # Pin Name
10 d

87 BA[0]/M_A[13] 97 M_A[4]
12 lan
88 BA[1]/M_A[14] 98 M_A[5]
A# Zea
65 BOOTCSn 99 M_A[6]
NDew
83 CASn/WPn 101 M_A[7]
58 CLKSEL[0] 102 M_A[8]
ER e N
59 CLKSEL[1] 104 M_A[9]
ND ar
2 CONFIG_A
, U ftw 90 M_A[10]
3 CONFIG_B 105 M_A[11]
AL o
TI W S
5 CONTROL_15 106 M_A[12]

6 CONTROL_25 138 M_A[16]
EN IJ
79 DQMn[0]/BYTEn 139 M_A[17]

ID *
NF 2yu
112 DQMn[1]/M_A[15] 64 M_A[18]

-- Exposed Die Pad 63 M_A[19]
CO 1e3
175 GPIO[0] 62 M_A[20]

LL -fg
174 GPIO[1] 61 M_A[21]
42 .
97 Ltd
VE 5pi
173 GPIO[2] 107 M_CLK_IN

AR 6
10 d
172 GPIO[3] 110 M_CLK_OUT
M ru9
12 lan
171 GPIO[4] 85 M_CSn[0]
q
A# Zea
12
170 GPIO[5] 57 M_CSn[1]

168 GPIO[6] 67 M_D[0]
NDew
161 GPIO[7] 69 M_D[1]
ER e N
160 GPIO[8] 71 M_D[2]

ND ar
159 GPIO[9] 73 M_D[3]

, U ftw
158 GPIO[10] 74 M_D[4]

AL o
TI W S
157 GPIO[11] 75 M_D[5]

156 GPIO[12] 76 M_D[6]
EN IJ
155 GPIO[13] 78 M_D[7]

ID *
NF 2yu
153 GPIO[14] 123 M_D[8]

152 GPIO[15] 122 M_D[9]
CO 1e3
91 M_A[0] 121 M_D[10]

LL -fg
93 M_A[1] 119 M_D[11]

VE 5pi
94 M_A[2] 117 M_D[12]

AR 6
96 M_A[3] 116 M_D[13]

M ru9
q
12


114 M_D[14] 194 NC
42 .
97 Ltd
113 M_D[15] 195 NC
10 d

56 NC 198 P0_LED0
12 lan
66 NC 199 P0_LED1
A# Zea
125 NC 200 P0_LED2
126 NC 11 P0_RXN
NDew
128 NC 10 P0_RXP
ER e N
129 NC 15 P0_TXN
ND ar
130 NC , U ftw 14 P0_TXP
131 NC 201 P1_LED0
AL o
TI W S
134 NC 203 P1_LED1

136 NC 204 P1_LED2
EN IJ
140 NC 20 P1_RXN
ID *
NF 2yu
141 NC 21 P1_RXP
143 NC 16 P1_TXN
CO 1e3
144 NC 17 P1_TXP
LL -fg
146 NC 205 P2_LED0
42 .
97 Ltd
VE 5pi
147 NC 206 P2_LED1

AR 6
10 d
149 NC 207 P2_LED2
M ru9
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150 NC 24 P2_RXN
q
A# Zea
177 NC 23 P2_RXP
12
178 NC 29 P2_TXN
NDew
179 NC 28 P2_TXP
ER e N
180 NC 209 P3_LED0

ND ar
182 NC 210 P3_LED1

, U ftw
184 NC 211 P3_LED2

AL o
186 NC 34 P3_RXN
TI W S
187 NC 35 P3_RXP
EN IJ
188 NC 30 P3_TXN
ID *
189 NC 31 P3_TXP
NF 2yu
190 NC 213 P4_LED0

CO 1e3
191 NC 214 P4_LED1

LL -fg
192 NC 215 P4_LED2

VE 5pi
193 NC 38 P4_RXN
AR 6
M ru9
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12

Signal Description
Pin Description
42 .
97 Ltd
10 d

12 lan
37 P4_RXP 19 VDDAL
42 P4_TXN 25 VDDAL
A# Zea
41 P4_TXP 33 VDDAL
NDew
196 P0_CONFIG 39 VDDAL
ER e N
8 P0_SDET 50 VDDO
84 RASn/OEn 60 VDDO
ND ar
51 RESETn
, U ftw 68 VDDO
AL o
7 RSET 77 VDDO
TI W S
176 RTCK 80 VDDO

47 TCK 86 VDDO
EN IJ
ID *
46 TDI 95 VDDO
NF 2yu
49 TDO 103 VDDO

CO 1e3
48 TMS 111 VDDO

45 TMS_ARM 115 VDDO
LL -fg
42 .
44 TRSTn 124 VDDO
97 Ltd
VE 5pi
52 UART_RX 132 VDDO

AR 6
10 d
M ru9
53 UART_TX 133 VDDO
12 lan
4 VDD 142 VDDO
q
A# Zea
12
43 VDD 151 VDDO

72 VDD 166
NDew
VDDO
ER e N
89 VDD 169 VDDO

100 VDD 183 VDDO
ND ar
, U ftw
120 VDD 202 VDDO

135 VDD 212 VDDO
AL o
TI W S
148 VDD 1 VSS

167 VDD 13 VSS
EN IJ
181 VDD 18 VSS

ID *
NF 2yu
208 VDD 26 VSS

9 VDDAH 27 VSS
CO 1e3
22 VDDAH 32 VSS
LL -fg
36 VDDAH 40 VSS
VE 5pi
AR 6
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12

42 .
97 Ltd
54 VSS 154 VSS
10 d

55 VSS 162 VSS
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70 VSS 163 VSS
A# Zea
82 VSS 185 VSS
NDew
92 VSS 197 VSS
ER e N
109 VSS 216 VSS
118 VSS 81 WEn
127 VSS
ND ar 164 XTAL_IN
, U ftw
137 VSS 165 XTAL_OUT
AL o
TI W S
145 VSS -- --
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
42 .
97 Ltd
VE 5pi
AR 6
10 d
M ru9
12 lan
q
A# Zea
12
NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

Signal Description
Pin Description
1.1.3 88E6218 216-Pin LQFP Pin Assignment List - Alphabetical by
42 .
97 Ltd
Signal Name
10 d

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A# Zea
87 BA[0]/M_A[13] 97 M_A[4]
88 BA[1]/M_A[14] 98 M_A[5]
NDew
65 BOOTCSn 99 M_A[6]
ER e N
83 CASn/WPn 101 M_A[7]
ND ar
2 CONFIG_A
, U ftw 102 M_A[8]
3 CONFIG_B 104 M_A[9]
AL o
5 CONTROL_15 90 M_A[10]
TI W S
6 CONTROL_25 105 M_A[11]

EN IJ
79 DQMn[0]/BYTEn 106 M_A[12]

ID *
NF 2yu
112 DQMn[1]/M_A[15] 64 M_A[18]

138 DQMn[2]/M_A[16] 63 M_A[19]
CO 1e3
139 DQMn[3]/M_A[17] 62 M_A[20]

LL -fg
-- Exposed Die Pad 61 M_A[21]
42 .
97 Ltd
VE 5pi
175 GPIO[0] 59 M_A[22]

AR 6
174 GPIO[1] 58 M_A[23]
10 d
M ru9
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173 GPIO[2] 107 M_CLK_IN
q
A# Zea
172 GPIO[3] 110 M_CLK_OUT
12
171 GPIO[4] 85 M_CSn[0]

NDew
170 GPIO[5] 57 M_CSn[1]
ER e N
168 GPIO[6] 56 M_CSn[2]

ND ar
161 GPIO[7] 67 M_D[0]

, U ftw
160 GPIO[8] 69 M_D[1]

AL o
159 GPIO[9] 71 M_D[2]

TI W S
158 GPIO[10] 73 M_D[3]

EN IJ
157 GPIO[11] 74 M_D[4]

ID *
156 GPIO[12] 75 M_D[5]

NF 2yu
155 GPIO[13] 76 M_D[6]

CO 1e3
153 GPIO[14] 78 M_D[7]

LL -fg
152 GPIO[15] 123 M_D[8]

VE 5pi
91 M_A[0] 122 M_D[9]

93 M_A[1] 121 M_D[10]
AR 6
M ru9
94 M_A[2] 119 M_D[11]

q
96 M_A[3] 117 M_D[12]

12

42 .
97 Ltd
10 d

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116 M_D[13] 20 P1_RXN
A# Zea
114 M_D[14] 21 P1_RXP
113 M_D[15] 16 P1_TXN
NDew
125 M_D[16] 17 P1_TXP
ER e N
126 M_D[17] 205 P2_LED0
ND ar
128 M_D[18] 206 P2_LED1
, U ftw
129 M_D[19] 207 P2_LED2
AL o
130 M_D[20] 24 P2_RXN

TI W S
131 M_D[21] 23 P2_RXP

EN IJ
134 M_D[22] 29 P2_TXN

ID *
136 M_D[23] 28 P2_TXP

NF 2yu
140 M_D[24] 209 P3_LED0

CO 1e3
141 M_D[25] 210 P3_LED1

143 M_D[26] 211 P3_LED2
LL -fg
42 .
97 Ltd
144 M_D[27] 34 P3_RXN
VE 5pi
146 M_D[28] 35 P3_RXP

AR 6
10 d
M ru9
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147 M_D[29] 30 P3_TXN
149 M_D[30] 31 P3_TXP
q
A# Zea
12
150 M_D[31] 213 P4_LED0

66 M_STATUS 214
NDew
P4_LED1
ER e N
195 MDC 215 P4_LED2

194 MDIO 38 P4_RXN
ND ar
, U ftw
198 P0_LED0 37 P4_RXP

199 P0_LED1 42 P4_TXN
AL o
TI W S
200 P0_LED2 41 P4_TXP

11 P0_RXN 196 P0_CONFIG
EN IJ
ID *
10 P0_RXP 8 P0_SDET
NF 2yu
15 P0_TXN 178 P6_COL

CO 1e3
14 P0_TXP 177 P6_CRS

201 P1_LED0 188 P6_INCLK
LL -fg
203 P1_LED1 192 P6_IND[0]

VE 5pi
204 P1_LED2 191 P6_IND[1]

AR 6
M ru9
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12

Signal Description
Pin Description
42 .
97 Ltd
10 d

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190 P6_IND[2] 9 VDDAH
189 P6_IND[3] 22 VDDAH
A# Zea
193 P6_INDV 36 VDDAH
NDew
187 P6_OUTCLK 12 VDDAL
ER e N
184 P6_OUTD[0]/P6_MODE[0] 19 VDDAL
ND ar
180
, U ftw
P6_OUTD[2]/P6_MODE[2] 33 VDDAL
AL o

TI W S
186 P6_OUTDV/DISABLE_P6 50 VDDO

84 RASn/OEn 60 VDDO
EN IJ
ID *
51 RESETn 68 VDDO
NF 2yu
7 RSET 77 VDDO
CO 1e3
176 RTCK 80 VDDO

47 TCK 86 VDDO
LL -fg
42 .
46 TDI 95 VDDO
97 Ltd
VE 5pi
49 TDO 103 VDDO

AR 6
10 d
M ru9
48 TMS 111 VDDO
12 lan
45 TMS_ARM 115 VDDO
q
A# Zea
12
44 TRSTn 124 VDDO

52 UART_RX 132
NDew
VDDO
ER e N
53 UART_TX 133 VDDO

4 VDD 142 VDDO
ND ar
, U ftw
43 VDD 151 VDDO

72 VDD 166 VDDO
AL o
TI W S
89 VDD 169 VDDO

100 VDD 183 VDDO
EN IJ
120 VDD 202 VDDO

ID *
NF 2yu
135 VDD 212 VDDO

148 VDD 1 VSS
CO 1e3
167 VDD 13 VSS

LL -fg
181 VDD 18 VSS

VE 5pi
208 VDD 27 VSS

AR 6
M ru9
q
12

42 .
97 Ltd
10 d

12 lan
26 VSS 137 VSS
32 VSS 145 VSS
A# Zea
40 VSS 154 VSS
NDew
54 VSS 162 VSS
ER e N
55 VSS 163 VSS
70 VSS 185 VSS
ND ar
82 VSS
, U ftw 197 VSS
AL o
92 VSS 216 VSS

TI W S
108 VSS 81 WEn

109 VSS 164 XTAL_IN
EN IJ
ID *
118 VSS 165 XTAL_OUT

NF 2yu
127 VSS -- --
CO 1e3
LL -fg
42 .
97 Ltd
VE 5pi
AR 6
10 d
M ru9
12 lan
q
A# Zea
12
NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
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12

Reset and Initialization
Section 2. Reset and Initialization

42 .
97 Ltd
The 88E6208/88E6218 uses certain pins as configuration inputs to set parameters following a reset. The definition
10 d

of these configuration pins changes after reset to their normal function. The following tables list and define the pins
12 lan
that affect the CPU, Switch/CPU interface, Switch, and PHY configuration. These pins require a 4.7 kΩ connection
to VSS or VDDO to override the internal resistor’s default.
A# Zea
NDew
Table 12: CPU Configuration Pins
ER e N
P in Co nf i gu r at i on F un ct i on
ND ar
M_A[18] Flash Boot Device Width
, U ftw
1 = 8-bit boot device (default)
AL o
0 = 16-bit boot device

TI W S
NOTE: Internally pulled high to 1.

{M_A[10],M_A[22], Core Frequency Selector (88E6218 only)
EN IJ
M_A[23]}
ID *
000 = Reserved for Internal Use only.

NF 2yu
001 = 143 MHz (only if part is speed marked accordingly)

010 = 83 MHz
CO 1e3
011 = 100 MHz

100 = 125 MHz
LL -fg
101 = 133 MHz (default)
42 .
97 Ltd
110 = 150 MHz (only if part is speed marked accordingly)
VE 5pi
111 = Reserved for internal use only

NOTE: Internally pulled to 3’b101.
AR 6
10 d
M ru9
12 lan
{M_A[10],M_A[16], Core Frequency Selector (88E6208 only)
M_A[17]}
q
A# Zea
12
(In future revisions)

010 = 83 MHz
NDew
or
011 = 100 MHz
ER e N
100 = 125 MHz

{M_A[10],
101 = 133 MHz (default)
ND ar
CLKSEL[1],
CLKSEL[0]}
, U ftw

(In Rev A and Rev
NOTE: Internally pulled to 3’b101.
AL o
B)
TI W S
NOTE: In 88E6208 Rev A and Rev B, M_A[17:16] do not perform this function. Instead, this
function is performed by the CLKSEL[1:0] pins. Future versions of the 88E6208 will not
have the CLKSEL[1:0] pins. The M_A[17:16] pins will be used instead. Clock selection
EN IJ
options should be done on both the CLKSEL[1:0] and the M_A[17:16] pins (at least as
ID *
PCB stuffing options) to maintain compatibility with future revisions of the 88E6208.
NF 2yu
M_A[7:6] PCB Options

CO 1e3
User definable configuration bits that are readable as defined in Part 2 of the 3 part 88E6208/
88E6218 datasheet.
LL -fg

VE 5pi
AR 6
M ru9
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12

Table 13: Switch/CPU Interface Configuration Pins
42 .
97 Ltd
P in Con f ig ur at i on F un ct i on
10 d

M_A[20] Port 5 runs at 2.5 MHz MII
12 lan
1 = Switch Port 5 runs at the rate determined by M_A[21] (default)
A# Zea
0 = Switch Port 5 runs at 2.5 MHz MII 10 Mbps PHY Mode, driving clocks to CPU’s UniMAC
NOTE: Internally pulled high 1.
NDew
M_A[21] Port 5 200BASE Mode (88E6218 only)
ER e N
0 = Switch Port 5 runs in 25 MHz MII 100 Mbps PHY Mode, driving clocks to CPU’s UniMAC
(default)
ND ar
1 = Switch Port 5 runs in 50 MHz MII 200 Mbps PHY Mode, driving clocks to CPU’s UniMAC
, U ftw
(88E6218 only)
AL o
NOTE: Internally pulled low to 0.

TI W S
EN IJ
ID *
NF 2yu
Table 14: Switch Configuration Pins

CO 1e3
LL -fg
42 .
M_A[0] Switch Test Mode
97 Ltd
VE 5pi
1 = Switch ports come up in the disabled port state - Software must enable the switch ports
AR 6
10 d
only after software is done configuring the switch (like defining the port based VLANs for fire-
M ru9
12 lan
wall protection).
0 = Switch ports come up in the forwarding port state (for test purposes only)
q
A# Zea
12

M_A[3] SMI Address NDew
1 = Internal switch uses SMI Device addresses 0x10 to 0x1F (default)
ER e N
0 = Internal switch uses SMI Device addresses 0x00 to 0x0F

ND ar

, U ftw
BA[1]/M_A[14] Full-Duplex Flow Control Disable

AL o
1 = Disable full-duplex flow control as defined in the switch - This mode can be overridden on a
TI W S
port-by-port basis by using the port’s Force Flow Control bit.

0 = Enable full-duplex flow control on all full-duplex ports as defined in the switch
EN IJ

ID *
BA[0]/M_A[13] Half-Duplex Flow Control Disable

NF 2yu
1 = Disable half-duplex flow control on all half-duplex ports as defined in the switch - This mode
CO 1e3
can be overridden on a port-by-port basis by using the port’s Force Flow Control bit.
0 = Enable half-duplex flow control on all half-duplex ports as defined in the switch
LL -fg

VE 5pi
AR 6
M ru9
q
12

Reset and Initialization
Table 14: Switch Configuration Pins (Continued)
42 .
P in Co nf i gu r at i on F un ct i on
97 Ltd
P6_OUTD[3:0] Port 6 Configuration (88E6218 only)
10 d

0000 = PHY half-duplex SNI 10 Mbps Rising edge clock with collision active low
12 lan
0001 = PHY half-duplex SNI 10 Mbps Rising edge clock with collision active high
A# Zea
0010 = PHY full-duplex SNI 10 Mbps Rising edge clock (collision is don’t care)
0011 = MAC full-duplex MII 200 Mbps 50 MHz MII input clock mode
0100 = PHY half-duplex SNI 10 Mbps Falling edge clock with collision active low
NDew
0101 = PHY half-duplex SNI 10 Mbps Falling edge clock with collision active high
ER e N
0110 = PHY full-duplex SNI 10 Mbps Falling edge clock (collision is don’t care)
0111 = PHY full-duplex MII 200 Mbps 50 MHz MII output clock mode
ND ar
1000 = MAC half-duplex MII 0 -100 Mbps DC to 25 MHz MII input clock mode
, U ftw
1001 = PHY half-duplex RMII 100 Mbps 50 MHz Reduced MII output clock mode
1010 = MAC full-duplex MII 0 -100 Mbps DC to 25 MHz MII input clock mode
AL o
1011 = PHY full-duplex RMII 100 Mbps 50 MHz Reduced MII output clock mode
TI W S
1100 = PHY half-duplex MII 10 Mbps 2.5 MHz MII output clock mode
1101 = PHY half-duplex MII 100 Mbps 25 MHz MII output clock mode
EN IJ
1110 = PHY full-duplex MII 10 Mbps 2.5 MHz MII output clock mode
ID *
1111 = PHY full-duplex MII 100 Mbps 25 MHz MII output clock mode (default)
NF 2yu

P6_OUTDV Port 6 Disable (88E6218 only)
CO 1e3
1 = Disabled
LL -fg
0 = Enabled
42 .
97 Ltd
VE 5pi
AR 6
10 d
M ru9
12 lan
q
A# Zea
12
NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

42 .
97 Ltd
Table 15: PHY Configuration Pins
10 d

12 lan
CONFIG_A Global Configuration A
A# Zea
This global configuration pin is used to set the default LED mode and Far-End Fault Indication
NDew
(FEFI) mode by connecting these pins to other device pins as follows:
VSS = LED Mode 0, FEFI disabled
ER e N
P0_LED0 = LED Mode 0, FEFI enabled
P0_LED1 = LED Mode 1, FEFI disabled
ND ar
, U ftw
AL o

TI W S
VDDO = LED Mode 3, FEFI enabled (default)

The FEFI and the LED modes are explained in Part 3 of the 3 part 88E6208/88E6218
EN IJ
datasheet.
ID *

NF 2yu
CONFIG_B Global Configuration B

CO 1e3
This global configuration pin is used to set the default mode for Auto-Crossover, the PHY driver
type and Energy Detect by connecting these pins to other device pins as follows:
LL -fg
VSS = No Crossover, Backplane drivers, Energy Detect disabled
42 .
97 Ltd
VE 5pi
P0_LED0 = No Crossover, CAT 5 drivers, Energy Detect enabled

P0_LED1 = No Crossover, Backplane drivers, Energy Detect disabled
AR 6
10 d
P0_LED2 = No Crossover, CAT 5 drivers, Energy Detect enabled
M ru9
12 lan
P1_LED0 = Auto Crossover, Backplane drivers, Energy Detect disabled
P1_LED1 = Auto Crossover, CAT 5 drivers, Energy Detect enabled
q
A# Zea
12
P1_LED2 = Auto Crossover, Backplane drivers, Energy Detect disabled

VDDO = Auto Crossover, CAT 5 drivers, Energy Detect enabled (default)
NDew
Auto crossover, Back Plane vs. CAT 5 drivers, and Energy Detect are covered in Part 3 of the
3 part 88E6208/88E6218 datasheet.
ER e N

ND ar
P0_CONFIG Port 0 Configuration

, U ftw
The P0_CONFIG pin is used to set the default configuration for Port 0 by connecting these
AL o
pins to other device pins as follows:

TI W S
VSS = Auto-Negotiation enabled (default)

P0_LED1 = Forced 10BASE-T half-duplex
EN IJ
P0_LED2 = Forced 10BASE-T full-duplex

P1_LED0 = Forced 100BASE-TX half-duplex
ID *
P1_LED1 = Forced 100BASE-TX full-duplex

NF 2yu
P1_LED2 = Forced 100BASE-FX half-duplex

VDDO = Forced 100BASE-FX full-duplex
CO 1e3
Ports 1, 2, 3 and 4’s default configuration is Auto-Negotiation enabled.

Any port’s default configuration can be modified by accessing the PHY registers by a CPU.
LL -fg
However, fiber mode vs. copper mode cannot be configured in this way. Fiber vs. copper must
VE 5pi
be selected at Reset by using the P[0]_CONFIG pin.

NOTE: Internally pulled low to 0.
AR 6
M ru9
q
12

Functional Description
Section 3. Functional Description
42 .
97 Ltd
10 d

12 lan
A# Zea
The datasheet for the 88E6208/88E6218 has been separated along major functional block lines. This portion of
the datasheet (Part 1) contains the common information about the part; its pinout, pinlist, electrical data, etc. The
NDew
CPU along with its peripherals, including the CPU’s Unified Media Access Controller (UniMAC™), is covered in
Part 2 of this datasheet. The Switch along with its PHYs and it’s MAC to the CPU is covered in Part 3.
ER e N
The 88E6208/88E6218 devices contain two major functional blocks, the CPU and the Switch. These two blocks
ND ar
are connected internally via a standard IEEE Ethernet MII with Ethernet MACs on both sides of the interface. This
, U ftw
implementation is identical to previous ‘multiple-chip’ solutions, so the software architecture and programmer’s
AL o
interface are the same as earlier products, making the job of porting previous software easier.
TI W S
The I/O registers in the Switch and in the PHYs are accessed in the same way as before. The CPU’s UniMAC
EN IJ
contains a SMI (Serial Management Interface) master block connected to the Switch and PHYs. The 88E6218
ID *
device supports an external 10/100/200 Mbps MII connected to Switch Port 6. In this device, the CPU’s SMI mas-
NF 2yu
ter block not only connects to the internal Switch and PHYs, it also exits the 88E6218 device through the device’s
MDC/MDIO pins. An external SMI slave device can be connected to the 88E6218 device’s MDC/MDIO pins as
CO 1e3
long as it uses unique SMI device addresses from the internal Switch and PHYs. The Switch and PHY’s
LL -fg
addresses can be configured by a pin at reset (see Section Section 2. "Reset and Initialization" on page 41).
42 .
97 Ltd
VE 5pi
The Switch’s interrupt (which combines interrupts generated from the Switch and PHYs) is sent to the CPU’s inter-
AR 6
10 d
rupt register. The IRQ interrupt sources are described in Part 2 of the 3 part 88E6208/88E6218 datasheet.
M ru9
12 lan
The UniMAC architecture provides an efficient networking interface between the ARM9E CPU and the 88E6208/
q
A# Zea
12
88E6218 multi-port Ethernet switch fabric. The purpose of the UniMAC architecture is to enhance networking per-
formance in the SOHO gateway/router application. NDew
ER e N
The UniMAC is an Ethernet MAC compatible with the IEEE 802.3 standard and contains a superset of features
including extra speed and functionality. In the 88E6218, the UniMAC can operate up to double the standard clock
ND ar
rate, so the UniMAC runs up to 200 Mbps full-duplex (that is, 200 Mbps in both transmit and receive directions
, U ftw
simultaneously providing a total bandwidth of 400 Mbps). In addition, the UniMAC contains multiple receive
AL o
queues and multiple transmit queues (88E6218 only), which provides a higher level of routing performance by
TI W S
providing packet pre-queuing based upon its source and/or destination. In addition, the UniMAC accelerates Inter-
net Protocol routing by aligning the incoming Internet Protocol data packet along a 32-bit boundary, which enables
EN IJ
the CPU to handle packets more quickly and increases routing performance.
ID *
NF 2yu
Figure 3: CPU & Switch Interconnect

CO 1e3
CPU Switch
LL -fg
Part 2 of the Datasheet Part 3 of the Datasheet

VE 5pi
MII
WAN Port
AR 6
Rest of the Switch Rest of the

CPU's SMI
M ru9
Memory I/F ARM9E CPU

UniMAC
Port 5's Switch w/
& Peripherals INTn MAC PHYs LAN Ports
q
12

3.1 UniMAC Interface Options
42 .
97 Ltd
The UniMAC or MII between the CPU and the Switch works as any standard MII, but it also contains some
optional improvements that can be used to accelerate routing performance.
10 d

12 lan
3.1.1 UniMAC Speeds
A# Zea
The UniMAC interface can run at 10/100 Mbps or 200 Mbps (88E6218 only) full-duplex. The interface’s speed and
NDew
mode is set by Port 5’s configuration pins (see Table 13, “Switch/CPU Interface Configuration Pins,” on page 42).
ER e N
3.1.2 Marvell Header Mode
ND ar
, U ftw
Switch Port 5 can be set to prepend 2 bytes of data in front of each frame sent to the CPU and to remove these 2
AL o
bytes of data coming back from the CPU. This Marvell Header Mode is optional, but it can increase CPU routing
TI W S
performance greatly by aligning the IP data portion of the frames in the CPU’s memory on 32-bit boundaries. On
ingress to the CPU the Marvell Header contains information the CPU needs, like the switch’s source port of the
EN IJ
frame, its priority (88E6218 only), etc. On egress from the CPU, the CPU uses the Header to indicate the port
ID *
based VLAN information of the frame so that frames sent to the LAN ports only go out the LAN ports and not out
NF 2yu
the WAN port (the header information is directly written to switch Port 5’s Port Based VLAN Map register - Part 3).
The Marvell Header supports the following features:
CO 1e3
• Higher routing performance due to 32-bit IP data alignment

LL -fg
• The WAN port can be any port on the switch
42 .
97 Ltd
VE 5pi
• More than one WAN port can be used either as a hot backup or for link aggregation
• Any switch port can be a DMZ port or other port type
AR 6
10 d
M ru9
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Refer to Part 3 of the 3 part 88E6208/88E6218 datasheet for more information on the format of the Marvell Header
q
A# Zea
to and from the CPU.
12
The CPU’s UniMAC can independently be set to process the Marvell Header or ignore it. If Switch Port 5 does not
NDew
generate/use the Marvell Header then the CPU must not try to process it. If Switch Port 5 generates/uses Marvell
Headers, the CPU’s UniMAC can process it or ignore it.
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

Functional Description
UniMAC Interface Options
Table 16 shows the valid options of the Switch and/or the CPU when in Marvell Header mode. Refer to Part 2 of
42 .
97 Ltd
the 3 part 88E6208/88E6218 datasheet for more information on the Marvell UniMAC settings.
10 d

12 lan
Table 16: Marvell UniMAC Header Options
A# Zea
Switch Port 5’s CPU’s UniMAC Receive Result
Header Insertion/ Queue Steering Header
NDew
Removal (See Part 3) Mode (See Part 2)
ER e N
Off Disabled • Classic MAC interface.
ND ar
, U ftw • Frame IP data is not 32-bit aligned in CPU
memory.
• DA filtering supported (88E6218 only).
AL o
TI W S
• CPU Receive Queue QoS steering determined by

CPU’s MAC processing (88E6218 only).
EN IJ
• Switch’s Marvell Trailer mode must be used to

determine source port of the frame and I/O register
ID *
NF 2yu
writes to Port 5’s Port Based VLAN Map register is

required when switching from WAN to LAN traffic.
CO 1e3
Off Any Mode Enabled • Do not use this option. Undefined results will occur.
LL -fg
42 .
On Disabled Frame IP data becomes 32-bit aligned in CPU
97 Ltd
VE 5pi
memory.
• DA filtering not supported.
AR 6
10 d
M ru9
12 lan
• CPU Receive Queue QoS steering cannot be
used.
q
A# Zea
•
12
CPU can use the Marvell Header to determine

source port of the frame and also use it to update
NDew
Port 5’s Port Based VLAN Map register on the fly
without the need of I/O register writes.
ER e N
On Any Mode Enabled • Frame IP data becomes 32-bit aligned in the CPU
ND ar
memory.
, U ftw
• DA filtering is supported (88E6218 only).

AL o
• CPU Receive Queue QoS steering determined by

TI W S
various bits in the Marvell Header.

• Which Header bits utilized are selectable by regis-
EN IJ
ters in the CPU’s UniMAC.

ID *
• CPU can use the Marvell Header to determine

NF 2yu
source port of the frame and also use it to update

Port 5’s Port Based VLAN Map register on the fly
CO 1e3
without the need of I/O register writes.

LL -fg
VE 5pi
AR 6
M ru9
q
12

Section 4. Electrical Specifications
42 .
97 Ltd
10 d

12 lan
A# Zea
4.1 Absolute Maximum Ratings
NDew
Table 17: Absolute Maximum Ratings
ER e N
NOTE: Stresses above those listed in Absolute Maximum Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect
ND ar
device reliability. , U ftw
Symbol Parameter M in Typ M ax Units
AL o
TI W S
VDD(3.3) Power Supply Voltage on VDDO with respect to -0.5 3.3 +3.6 V
VSS
EN IJ
VDD(2.5) Power Supply Voltage on VDDAH with respect to -0.5 2.5 +3.6 or V
ID *
VSS VDD(3.3)
NF 2yu
+0.51
whichever
CO 1e3
is less
LL -fg
VDD(1.5) Power Supply Voltage on VDD, or VDDAL with -0.5 1.5 +3.6 or V
42 .
respect to VSS VDD(2.5)
97 Ltd
VE 5pi
+0.52
whichever
AR 6
10 d
M ru9
is less
12 lan
VPIN Voltage applied to any input pin with respect to -0.5 +3.6 or V
q
A# Zea
VSS VDDO
12
NDew +0.53
whichever
is less
ER e N
TSTORAGE Storage temperature -55 +1254 °C

ND ar
1. VDD(2.5) must never be more than 0.5V greater than VDD(3.3) or damage will result. This implies that power must be applied
, U ftw
to VDD(3.3) before or at the same time as VDD(2.5).

AL o
2. VDD(1.5) must never be more than 0.5V greater than VDD(2.5) or damage will result. This implies that power must be applied
TI W S
to VDD(2.5) before or at the same time as VDD(1.5).

3. VPIN must never be more than 0.5V greater than VDDO or damage will result.
EN IJ
4. 125°C is the re-bake temperature. For extended storage time greater than 24 hours, +85°C should be the maximum.
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

Electrical Specifications
Recommended Operating Conditions
4.2 Recommended Operating Conditions
42 .
97 Ltd
10 d

Table 18: Recommended Operating Conditions
12 lan
S ym bo l P ar am et e r Co nd i t io n Min Ty p M ax U ni ts
A# Zea
VDD(3.3) 3.3V power supply For pins VDDO 3.135 3.3 3.465 V
NDew
VDD(2.5) 2.5V power supply For pins VDDAH 2.375 2.5 2.625 V
VDD(1.5) 1.5V power supply For pins 1.425 1.5 1.575 V
ER e N
VDD, VDDAL
ND ar
TA Ambient operating
, U ftw 0 70 °C
temperature
1251 °C
AL o
TJ Maximum junction
TI W S
temperature
RSET Internal bias reference Resistor value placed 1980 2000 2020 Ω
EN IJ
between RSET- and RSET+

ID *
pins
NF 2yu
1. Refer to the white paper on TJ Thermal Calculations for more Information.

CO 1e3
LL -fg
42 .
97 Ltd
4.3 Notes on Powering Up and Powering Down
VE 5pi
When turning on power, turn on the voltage power in the following sequence: The highest voltage power VDDO
AR 6
10 d
M ru9
12 lan
must be turned on first; then, turn on the next higher voltage power for the 88E6208/88E6218, etc.
This power-up sequence must be used due to a protection diode between the two power rails. These diodes leak
q
A# Zea
12
current if the tie-high terminal becomes tie low by an improper turn-on sequence.
NDew
When powering down, first turn off the lowest voltage and then turn off the higher voltage.
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.4 Package Thermal Data
42 .
97 Ltd
4.4.1 Thermal Conditions for 216-pin LQFP Package
10 d

12 lan
Table 19: Thermal Conditions for 216-pin LQFP Package
A# Zea
Symb ol Param eter Con di ti on Min Typ Max Un its
NDew
θJA 1
Thermal resistance - junc- JEDEC 3 in. x 4.5 in. 4- 20.5 °C/W
ER e N
tion to ambient of the 216-Pin layer PCB with no air flow
LQFP package
JEDEC 3 in. x 4.5 in. 4- 17.6 °C/W
ND ar
layer PCB with 1 meter/sec
θJA = (TJ - TA)/ P
, U ftw
air flow
P = Total Power Dissipation
AL o
JEDEC 3 in. x 4.5 in. 4- 16.6 °C/W

TI W S

air flow
EN IJ
JEDEC 3 in. x 4.5 in. 4- 16.1 °C/W

ID *

NF 2yu
air flow
ψJT °C/W
CO 1e3
Thermal characteristic JEDEC 3 in. x 4.5 in. 4- 0.39

parameter1 - junction to top layer PCB with no air flow
LL -fg
center of the 216-Pin LQFP

JEDEC 3 in. x 4.5 in. 4- -- °C/W
42 .
package
97 Ltd
VE 5pi

air flow
ψJT = (TJ - TTOP)/P.
AR 6
10 d
°C/W
M ru9
JEDEC 3 in. x 4.5 in. 4- --
12 lan
Ttop = Temperature on the
top center of the package layer PCB with 2 meter/sec
q
A# Zea
air flow
12
JEDEC 3 in. x 4.5 in. 4- NDew -- °C/W

air flow
ER e N
θJC Thermal resistance1 - junc- JEDEC with no air flow 7.8 °C/W
ND ar
tion to case of the 216-Pin

, U ftw
LQFP package
AL o
θJC = (TJ - TC)/ PTop

TI W S
PTop = Power Dissipation

from the top of the package
EN IJ
θJB Thermal resistance1 - junc- JEDEC with no air flow 12.7 °C/W
ID *
tion to board of the 216-Pin

NF 2yu
LQFP package
CO 1e3
θJB = (TJ - TB)/ Pbottom

Pbottom = power dissipation
LL -fg
from the bottom of the pack-

VE 5pi
age to the PCB surface.
1. Refer to white paper on TJ Thermal Calculations for more information.

AR 6
M ru9
q
12

DC Electrical Characteristics
4.5 DC Electrical Characteristics
42 .
97 Ltd
4.5.1 DC Power Characteristics
10 d

12 lan
Table 20: DC Power Characteristics
A# Zea
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
NDew
Sy mb ol Parameter Pi ns Co n di t io n Min Typ 1 Max U n i ts
ER e N
IDD(3.3) 3.3 volt Power to VDDO CPU @ 133 MHz 180 mA
outputs
CPU @ 150 MHz 185 mA
ND ar
2
, U ftw
IDD(2.5) 2.5 volt Power to VDDAH No link on any port 135 mA
analog core
AL o
TI W S
All ports 10 Mbps linked but 135 mA

idle
EN IJ
All ports 10 Mbps and 425 mA

active
ID *
NF 2yu
All ports 100 Mbps 220 mA

CO 1e3
IDD(1.5) 1.5 volt Power to VDDAL No link on any port 0 mA

analog core
LL -fg
42 .
97 Ltd
VE 5pi
1.5 volt Power to VDD No link on any port 100 mA

AR 6
10 d
digital core w/CPU
M ru9
12 lan
@ 133 MHz
All ports 10 Mbps linked but 190 mA
q
A# Zea
idle
Add 15 mA w/CPU
12
@ 150 MHz All ports 10 Mbps and 195 mA

active
NDew
ER e N
All ports 100 Mbps linked 240 mA

but idle
ND ar
All ports 100 Mbps and 260 mA

, U ftw
active
AL o
1. The values listed are typical values with LED mode 3, 3 LEDs per port, and Auto-Negotiation on.
TI W S
2. The 2.5V power source must supply an additional 100 mA (Typical) current from the center tap on the magnetics. (This number
is not included in this table.)
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.5.2 Digital Operating Conditions
42 .
97 Ltd
Table 21: Digital Operating Conditions
10 d

12 lan
Symbol Parameter Pin s Con di ti on Mi n Typ Max Un its
A# Zea
VIH High level All pins 2.0 VDDO V
input voltage +0.5
NDew
XTAL_IN 1.4 V
ER e N
VIL Low level All pins -0.5 0.8 V
ND ar
input voltage
, U ftw XTAL_IN 0.6
1
VOH High level LED pins IOH = -8 mA 2.4 V
AL o
output VDDO = Min

TI W S
voltage VIH(XTAL_IN)
XTAL_OUT IOH = -1 mA V
+0.2
EN IJ
All others IOH = -4 mA 2.4 V

ID *
NF 2yu
VDDO = Min
VOL Low level LED pins1 IOL= 8 mA 0.4 V
CO 1e3
output VIL(XTAL_IN)
XTAL_OUT IOL = 1 mA V
voltage
LL -fg
-0.2
42 .
97 Ltd
All others IOL= 4 mA 0.4 V
VE 5pi
IILK Input leakage With pull-up 0<VIN<VDD + 10 µA

AR 6
10 d
current resistor - 50
M ru9
12 lan
With pull-down 0<VIN<VDD + 50 µA
q
A# Zea
resistor - 10
12
All others 0<VIN<VDD NDew ±10v µA

CIN Input All pins 5 pF
ER e N
capacitance
ND ar
1. The LED pins are as follows: P4_LED2[2:0], P3_LED1[2:0], P2_LED2[2:0], P1_LED1[2:0], P0_LED1[2:0]
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

DC Electrical Characteristics
Table 22: Internal Resistor Description
42 .
97 Ltd
Pin # Pin Name Re sistor Pin # Pin Name Res is t or
10 d

12 lan
2 CONFIG_A Internal pull-up 66 M_STATUS Internal pull-up
A# Zea
3 CONFIG_B Internal pull-up 88, 87 BA[1:0]/ Internal pull-up
M_A[14:13]
NDew
44 TRSTn Internal pull-up 106, 105, 90, M_A[12:0] Internal pull-up
104, 102, 101,
ER e N
99, 98, 97, 96,
94, 93, 91
45
ND ar
TMS_ARM Internal pull-up 139, 138, 112, DQMn[3:0]/ Internal pull-up1
, U ftw
79 M_A[17:15],
AL o
BYTEn
TI W S
46 TDI Internal pull-up 152, 153, 155, GPIO[15:0] Internal pull-up

156, 157, 158,
EN IJ
159, 160, 161,

ID *
168, 170, 171,

NF 2yu
172, 173, 174,

175
CO 1e3
47 TCK Internal pull-up 177 P6_CRS Internal pull-down

LL -fg
48 TMS Internal pull-up 178 P6_COL Internal pull-down
42 .
97 Ltd
VE 5pi
49 TDO None 179, 180, 182, P6_OUTD[3:0]/ Internal pull-up

184 P6_MODE[3:0]
AR 6
10 d
M ru9
12 lan
51 RESETn None 186 P6_OUTDV/ Internal pull-up
DISABLE_P6
q
A# Zea
12
52 UART_RX Internal pull-up 187 P6_OUTCLK Internal pull-up

53 UART_TX None 188
NDew P6_INCLK Internal pull-up
58 (88E6218) M_A[23] Internal pull-up 189, 190,191, P6_IND[3:0] Internal pull-up
ER e N
192
ND ar
58 (88E6208) CLKSEL[0] Internal pull-up 193 P6_INDV Internal pull-down

, U ftw
59 (88E6218) M_A[22] Internal pull-down 194 MDIO Internal pull-up

AL o
59 (88E6208) CLKSEL[1] Internal pull-down 195 MDC Internal pull-up

TI W S
61 M_A[21] Internal pull-down 196 P0_CONFIG Internal pull-down

EN IJ
62, 63, 64 M_A[20:18] Internal pull-up

ID *
1. In future revisions, MA_[16] will have an internal pull-down. See Table 12, “CPU Configuration Pins,” on
NF 2yu
page 41 for M_A[16] details.

CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.5.3 IEEE DC Transceiver Parameters
42 .
97 Ltd
Table 23: IEEE DC Transceiver Parameters
10 d

IEEE tests are typically based on templates and cannot simply be specified by a number. For an exact description of the
12 lan
template and the test conditions, refer to the IEEE specifications:
-10BASE-T IEEE 802.3 Clause 14
A# Zea
-100BASE-TX ANSI X3.263-1995
NDew
Symbol P a r a m e te r Pins Conditio n M in Typ M ax U nits
ER e N
VODIFF Absolute TXP/N[1:0] 10BASE-T no cable 2.2 2.5 2.8 V
ND ar
peak , U ftw
differential
TXP/N[1:0] 10BASE-T cable model 5851 mV
output
AL o
voltage
TI W S
TXP/N[0] 100BASE-FX mode 0.4 0.8 1.2 V

EN IJ
TXP/N[1:0] 100BASE-TX mode 0.950 1.0 1.05 V

ID *
NF 2yu
Overshoot2 TXP/N[4:0] 100BASE-TX mode 0 5% V

CO 1e3
Amplitude TXP/N[1:0] 100BASE-TX mode 0.98x 1.02x V+/V-

LL -fg
Symmetry
42 .
97 Ltd
VE 5pi
(positive/
negative)
AR 6
10 d
5853
M ru9
12 lan
VIDIFF Peak RXP/N[1:0] 10BASE-T mode mV
Differential
q
A# Zea
Input Voltage
12
RXP/N[0] 100BASE-FX mode 200 mV

accept level
P[1:0]_SDET NDew
P/N
ER e N
Signal Detect RXP/N[1:0] 100BASE-TX mode 1000 4604 mV

Assertion peak-
ND ar
peak
, U ftw
Signal Detect RXP/N[1:0] 100BASE-TX mode 200 3605 mV

De-assertion peak-
AL o
TI W S
peak
1. IEEE 802.3 Clause 14, Figure 14.9 shows the template for the “far end” wave form. This template allows as little as 495 mV
EN IJ
peak differential voltage at the far end receiver.

ID *
2. ANSI X3.263-1995 Figure 9-1.

NF 2yu
3. The input test is actually a template test. IEEE 802.3 Clause 14, Figure 14.17 shows the template for the receive wave form.
4. The ANSI TP-PMD specification requires that any received signal with peak-to-peak differential amplitude greater than 1000 mV
CO 1e3
should turn on signal detect (internal signal in 100BASE-TX mode). The 88E6208/88E6218 will accept signals typically with 460
mV peak-to-peak differential amplitude.
LL -fg
5. The ANSI TP-PMD specification requires that any received signal with peak-to-peak differential amplitude less than 200 mV
VE 5pi
should be de-assert signal detect (internal signal in 100BASE-TX mode). The 88E6208/88E6218 will reject signals typically with
peak-to-peak differential amplitude less than 360 mV.
AR 6
M ru9
q
12

AC Electrical Specifications
4.6 AC Electrical Specifications
42 .
4.6.1 Asynchronous Signals
97 Ltd
10 d
The following are asynchronous signals:

12 lan
• UART interface pins
• GPIO interface pins
A# Zea
4.6.2 Reset and Configuration Timing
NDew
Table 24: Reset and Configuration Timing
ER e N
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified.)
ND ar
Symb ol Par ame te r
, U ftw Condition Mi n Ty p Ma x U ni ts No te s
Valid power to RESETn
AL o
TPU_RESET de-asserted 10 ms
TI W S
Number of valid clock

EN IJ
TSU_CLK cycles prior to RESETn 10 Clks

de-asserted
ID *
NF 2yu
Configuration data valid

TSU prior to RESETn 200 ns 1
CO 1e3
de-asserted
Configuration data valid
LL -fg
THD after RESETn 0 ns
42 .
97 Ltd
de-asserted
VE 5pi
Configuration output
AR 6
10 d
TCO driven after RESETn 40 ns 2
M ru9
12 lan
de-asserted
q
A# Zea
1. When RESETn is low all configuration pins become inputs, and the value seen on these pins is latched on the rising edge of RESETn.
12
2. P6_OUTD[3:0]/P6_MODE[3:0], and P6_OUTDV are normally outputs that are also used to configure the 88E6208/88E6218 during hard-
NDew
ware reset. When reset is asserted, these pins become inputs and the desired device configuration is latched at the rising edge of
RESETn.
ER e N
Figure 4: Reset and Configuration Timing

ND ar
, U ftw
TPU_RESET
AL o
Power TSU_CLK
TI W S
EN IJ
CLK
ID *
NF 2yu
RESETn
CO 1e3
Config Data
LL -fg
VE 5pi
TSU TH
TCO
AR 6
M ru9
Config Pins Output

q
12

4.6.3 Clock Timing when using a 25 MHz Oscillator
42 .
97 Ltd
Table 25: Clock Timing when using a 25 MHz Oscillator
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified.)
10 d

12 lan
Symb ol Par amete r Con di ti on Mi n Ty p Ma x Un its Notes
A# Zea
40 40 40 ns 25 MHz
TP XTAL_IN period -50 ppm +50 ppm
NDew
ER e N
TH XTAL_IN high time 16 ns
ND ar
, U ftw
TL XTAL_IN low time 16 ns
AL o
TI W S
EN IJ
TR XTAL_IN rise 3 ns
ID *
NF 2yu
TF XTAL_IN fall 3 ns
CO 1e3
LL -fg
42 .
97 Ltd
VE 5pi
Figure 5: Oscillator Clock Timing

AR 6
10 d
M ru9
12 lan
TP
q
A# Zea
12
TH TL
2.0 V
NDew
XTAL_IN
ER e N
0.8V
ND ar
TR TF
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.6.4 Serial Management Interface Timing

Table 26: Serial Management Interface Timing

42 .
97 Ltd
Sy mbol Para meter Condition M in Typ M ax Units N otes
10 d

TDLY_MDIO MDC to MDIO (Output) 0 20 ns
12 lan
delay time
A# Zea
TSU MDIO (Input) to MDC 10 ns
setup time
NDew
THD MDIO (Input) to MDC 10 ns
ER e N
hold time
ND ar
Figure 6: Serial Management Interface Timing
, U ftw
AL o
TI W S
MDC
EN IJ
ID *
NF 2yu
MDIO (Output)
CO 1e3
TDLY_MDIO
LL -fg
42 .
97 Ltd
VE 5pi
MDC
AR 6
10 d
M ru9
12 lan
THD
TSU
q
A# Zea
12
Valid
MDIO (Input) Data NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.6.5 SDRAM/Device Interface Timing

42 .
97 Ltd
Note
Proper design of the memory controller interface to SDRAM and Flash is required for high frequencies.
10 d

Please contact Marvell® for design and layout guidelines.
12 lan
A# Zea
Table 27: SDRAM/Device Interface Timing
NDew
ER e N
S ym bo l P ar am et er Co nd it i o n Mi n Typ M ax Uni ts N o t es
ND ar
TCYC M_SDCLK_OUT
, U ftw SDRAM clock 6.7 ns
output
AL o
TCYC M_SDCLK_IN SDRAM clock 6.7 ns

TI W S
input
1,2
TVAL All SDRAM outputs All SDRAM 2 5.4 - X ns
EN IJ
outputs time to
ID *
Signal valid
NF 2yu
delay.
3
TSU All SDRAM inputs All SDRAM 0.5 ns
CO 1e3
inputs – input
setup time.
LL -fg
42 .
4
97 Ltd
TH All SDRAM inputs All SDRAM 1 ns
VE 5pi
inputs – input
hold time.
AR 6
10 d
M ru9
12 lan
1. Relative to M_SDCLK_OUT
q
A# Zea
2. X = 0.5*(7.5 - TCYC)
12
3. Relative to M_SDCLK_IN
4. Relative to M_ SDCLK_IN
NDew
ER e N
ND ar
Note
, U ftw
All timings assume internal M_SDCLK_OUT delay line programmed to 2 (refer to 88E6208/88E6218
AL o
RevB0 Release Notes).

TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

Figure 7: Flash/ROM Read Access
42 .
97 Ltd
ADDR
10 d

t t
12 lan
e e
text text
x VALID x
t t
CE#
A# Zea
CEn
OE#
NDew
OEn
ER e N
ND ar
DATA
, U ftw t t
e e
HIGH-Z x VALID x HIGH-Z
AL o
t t
TI W S
tOD
tAA
EN IJ
ID *
Figure 8: Flash/ROM Write Access

NF 2yu
ADDR
CO 1e3
t t t t
e e e e
text text
text text
x VALID x x VALID x
LL -fg
t t t t
CE#
CEn
42 .
97 Ltd
VE 5pi
AR 6
WE#
10 d
WEn
M ru9
12 lan
q
A# Zea
OE#
12
OEn
tWH NDew tWH

DATA
ER e N
t t t
e e e
HIGH-Z x VALID x HIGH-Z x VALID HIGH-Z
ND ar
t t t
tWB for last

, U ftw
tWP tWPH write

AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.6.6 GPIO Timing
42 .
97 Ltd
10 d

Table 28: GPIO Timing
12 lan
A# Zea
1
, 2
NDew
IOH Switching current high VCC - 0.4 10 mA
IOL Switching current low 0.4 16 mA
ER e N
TSLEW_RISE Output rise slew 0.3VCC- 1.5 V/ns
ND ar
, U ftw 0.6VCC
TSLEW_FALL Output fall slew rate 0.6VCC- 1.0 V/ns
AL o
0.3VCC
TI W S
TPLH Output mode low to high 50%~50%. 1.0 3.0 ns

delay 10 pF load
EN IJ
TPHL Output mode high to low 50%~50%. 1.0 3.0 ns

ID *
delay 10 pF load
NF 2yu
1. GPIO are operating in fast slew rate mode.

CO 1e3
2. The rise/fall time of the input signal is 0.5 ns.

LL -fg
42 .
97 Ltd
VE 5pi
AR 6
10 d
M ru9
12 lan
q
A# Zea
12
NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.6.7 Switch Port 6 MII Rx Timing (PHY Mode) - 88E6218 Only
42 .
97 Ltd
Table 29: Switch Port 6 MII Receive Timing (PHY Mode) - 88E6218 Only
In PHY mode, the P6_INCLK pins are outputs.
10 d

12 lan
Symbol Parameter Condition Mi n Typ Max Units Notes
A# Zea
1
NDew
10BASE mode 400 ns
TP_TX_CLK P6_INCLK period
ER e N
ND ar
100BASE mode 40 ns 1
, U ftw
AL o
10BASE mode 160 200 240 ns

TI W S
TH_TX_CLK P6_INCLK high

EN IJ
100BASE mode 16 20 24 ns
ID *
NF 2yu
CO 1e3
10BASE mode 160 200 240 ns

TL_TX_CLK P6_INCLK low
LL -fg
42 .
97 Ltd
VE 5pi
100BASE mode 16 20 24 ns
AR 6
10 d
M ru9
12 lan
MII inputs (P6_IND[3:0],
TSU_TX P6_INDV) valid prior to 15 ns
q
A# Zea
P6_INCLK going high.
12
MII inputs (P6_IND[3:0], NDew

THD_TX P6_INDV) valid after 0 ns
ER e N
1. 2.5 MHz for 10 Mbps or 25 MHz for 100 Mbps.

ND ar
, U ftw
Figure 9: PHY Mode MII Receive Timing

AL o
TI W S
TH_TX_CLK
EN IJ
INCLK TL_TX_CLK
ID *
NF 2yu
TP_TX_CLK
CO 1e3
INPUTS
LL -fg
THD_TX
VE 5pi
TSU_TX
AR 6
M ru9
NOTE: INCLK is the clock used to clock the input data.

q
It is an output in this mode.

12

4.6.8 Switch Port 6 MII Tx Timing (PHY Mode) - 88E6218 Only

Table 30: Switch Port 6 MII Transmit Timing (PHY Mode) - 88E6218 Only
42 .
In PHY mode, the P6_OUTCLK pin is an output.
97 Ltd
10 d

Symb ol Par amete r Con di tion Min Typ Max Units Notes
12 lan
A# Zea
1
10BASE mode 400 ns
TP_RX_CLK P6_OUTCLK period
NDew
100BASE 40 ns 1
ER e N
mode
ND ar
, U ftw
10BASE mode 160 200 240 ns
AL o
TH_RX_CLK P6_OUTCLK high

TI W S
EN IJ
100BASE 16 20 24 ns
mode
ID *
NF 2yu
CO 1e3
10BASE mode 160 200 240 ns

TL_RX_CLK P6_OUTCLK low
LL -fg
42 .
97 Ltd
VE 5pi
100BASE 16 20 24 ns
mode
AR 6
10 d
M ru9
12 lan
P6_OUTCLK to outputs
q
A# Zea
TCQ_MAX (P6_OUTD[3:0], 25 ns
12
P6_OUTDV) valid
NDew
TCQ_MIN P6_OUTD[3:0], 10 ns
ER e N
P6_OUTDV) invalid
ND ar

, U ftw
AL o
TI W S
Figure 10: PHY Mode MII Transmit Timing

EN IJ
TH_RX_CLK
ID *
TL_RX_CLK
NF 2yu
OUTCLK
CO 1e3
TP_RX_CLK
LL -fg
OUTPUTS
VE 5pi
AR 6
TCQ_MAX TCQ_MIN
M ru9
NOTE: OUTCLK is the clock used to clock the output data.

q

12

4.6.9 Switch Port 6 Clock Timing (MAC Mode) - 88E6218 Only
42 .
97 Ltd
Table 31: Switch Port 6 Clock Timing (MAC Mode) - 88E6218 Only
In MAC mode, INCLK and OUTCLK are inputs.
10 d

12 lan
A# Zea
0 4 40 ns DC to
NDew
TP P6_INCLK period or +50 25 MHz
40 ppm
ER e N
ND ar
TH P6_INCLKhigh time 16 ns
, U ftw
AL o
TL P6_INCLK low time 16 ns

TI W S
EN IJ
TR P6_INCLK rise 3 ns
ID *
NF 2yu
CO 1e3
TF P6_INCLK fall 3 ns
LL -fg
42 .
97 Ltd
VE 5pi
AR 6
10 d
Figure 11: MAC Clock Timing
M ru9
12 lan
q
A# Zea
TP
12
TH TL
NDew
2.0 V
ER e N
P6_CLK
0.8V
ND ar
TR TF
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.6.10 Switch Port 6 MII Rx Timing (MAC Mode) - 88E6218 Only

Table 32: Switch Port 6 MII Receive Timing (MAC Mode) - 88E6218 Only
42 .
97 Ltd
In MAC mode, the P6_INCLK pin is an input.
10 d

Symb ol Para meter Con di ti on Mi n Ty p Ma x Un i ts Note s
12 lan
A# Zea
TSU_RX P6_INDV) valid prior to With 10 pF load 10 ns
P6_INCLK going high
NDew
ER e N
THD_RX P6_INDV) valid after With 10 pF load 10 ns
P6_INCLK going high
ND ar
, U ftw
AL o
TI W S
Figure 12: MAC Mode MII Receive Timing

EN IJ
INCLK
ID *
NF 2yu
THD_RX
CO 1e3
INPUTS
LL -fg
42 .
97 Ltd
VE 5pi
TSU_RX
AR 6
10 d
M ru9
12 lan
It is an input in this mode.
q
A# Zea
12
NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.6.11 Switch Port 6 MII Tx Timing (MAC Mode) - 88E6218 Only
42 .
97 Ltd
Table 33: Switch Port 6 MII Transmit Timing (MAC Mode) - 88E6218 Only
In MAC mode, the P6_OUTCLK pin is an input.
10 d

12 lan
Symbol Parameter Conditi on Min Typ Max Units Notes
A# Zea
NDew
TCQ_MAX (P6_OUTD[3:0], With 10 pF load 25 ns
P6_OUTDV) valid
ER e N
ND ar
TCQ_MIN (P6_OUTD[3:0], With 1 0pF load 0 ns
P6_OUTDV) invalid
, U ftw
AL o
TI W S
Figure 13: MAC Mode MII Transmit Timing

EN IJ
ID *
NF 2yu
OUTCLK
CO 1e3
LL -fg
42 .
97 Ltd
VE 5pi
OUTPUTS
AR 6
10 d
M ru9
TCQ_MAX TCQ_MIN
12 lan
q
A# Zea
12
NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.6.12 Switch Port 6 Clock Timing - 200 Mbps (MAC Mode) - 88E6218
42 .
97 Ltd
Only
10 d

Table 34: Switch Port 6 Clock Timing - 200 Mbps (MAC Mode) - 88E6218 Only
12 lan
In MAC mode, INCLK and OUTCLK are inputs.
A# Zea
Symbol Parameter Condition Min Typ Max Units Notes
NDew
20 20 ns DC to
ER e N
TP P6_INCLK period -50ppm 20 +50 ppm 25 MHz
ND ar
, U ftw
TH P6_INCLK high time 8 ns
AL o
TI W S
TL P6_INCLK low time 8 ns

EN IJ
ID *
NF 2yu
TR P6_INCLK rise 3 ns
CO 1e3
LL -fg
TF P6_INCLK fall 3 ns
42 .
97 Ltd
VE 5pi
AR 6
10 d
M ru9
12 lan
Figure 14: MAC Clock Timing - 200 Mbps
q
A# Zea
12
TP
NDew
ER e N
TH TL
2.0 V
ND ar
P6_CLK
, U ftw
0.8V
AL o
TR TF
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.6.13 Switch Port 6 MII Rx Timing (PHY Mode) - 200 Mbps - 88E6218
42 .
97 Ltd
Only
10 d

Table 35: Switch Port 6 MII Receive Timing (PHY Mode) - 200 Mbps - 88E6218 Only
12 lan
In PHY mode, the P6_INCLK pin is output.
A# Zea
NDew
ER e N
TP_TX_CLK P6_INCLK period 200BASE 20 ns
mode
ND ar
, U ftw
200BASE 8 10 12 ns
AL o
TH_TX_CLK P6_INCLK high mode

TI W S
200BASE 8 10 12 ns
EN IJ
TL_TX_CLK P6_INCLK low mode

ID *
NF 2yu
TSU_TX MII inputs (P6_IND[3:0], 13 ns

P6_INDV) valid prior to
CO 1e3

LL -fg
THD_TX MII inputs (P6_IND[3:0], 0 ns
42 .
97 Ltd
P6_INDV) valid after
VE 5pi

AR 6
10 d
M ru9
12 lan
q
A# Zea
Figure 15: PHY Mode MII Receive Timing - 200 Mbps
12
NDew
TH_TX_CLK
ER e N
INCLK TL_TX_CLK
ND ar
, U ftw
TP_TX_CLK
AL o
TI W S
INPUTS
EN IJ
THD_TX
ID *
TSU_TX
NF 2yu

CO 1e3

LL -fg
VE 5pi
AR 6
M ru9
q
12

4.6.14 Switch Port 6 MII Tx Timing (PHY Mode) - 200 Mbps - 88E6218
42 .
97 Ltd
Only
10 d

Table 36: Switch Port 6 MII Transmit Timing (PHY Mode) - 200 Mbps - 88E6218 Only
12 lan
In PHY mode, the P6P[x]_OUTCLK pin is are outputs.
A# Zea
Symbol Pa rame te r C ondition Min Typ Max Units Notes
NDew
TP_RX_CLK P6_OUTCLK period 200BASE 20 ns
ER e N
mode
ND ar
TH_RX_CLK P6_OUTCLK high 200BASE 8 10 12 ns
, U ftw mode
TL_RX_CLK P6_OUTCLK low 200BASE 8 10 12 ns
AL o
mode
TI W S
TCQ_MAX P6_OUTCLK to outputs 15 ns

EN IJ
(P6_OUTD[3:0],
P6_OUTDV) valid
ID *
NF 2yu
TCQ_MIN P6_OUTCLK to outputs 3 ns

P6_OUTD[3:0],
CO 1e3
P6_OUTDV) invalid
LL -fg
42 .
97 Ltd
VE 5pi
Figure 16: PHY Mode MII Transmit Timing - 200 Mbps

AR 6
10 d
M ru9
12 lan
TH_RX_CLK
q
A# Zea
12
OUTCLK TL_RX_CLK
NDew
ER e N
TP_RX_CLK
ND ar
, U ftw
OUTPUTS
AL o
TCQ_MAX TCQ_MIN
TI W S

EN IJ

ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.6.15 Switch Port 6 MII Rx Timing (MAC Mode) - 200 Mbps -
42 .
97 Ltd
88E6218 Only
10 d

Table 37: Switch Port 6 MII Receive Timing (MAC Mode) - 200 Mbps - 88E6218 Only
12 lan
In MAC mode, the P6P[x]_INCLK pin is are inputs.
A# Zea
NDew
TSU_RX MII inputs (P6_IND[3:0], With 10 pF load 5 ns
ER e N
P6_INCLK going high
THD_RX
ND ar
MII inputs (P6_IND[3:0], With 10 pF load 3 ns
, U ftw
AL o
P6_INCLK going high

TI W S
EN IJ
Figure 17: MAC Mode MII Receive Timing - 200 Mbps

ID *
NF 2yu
CO 1e3
INCLK
LL -fg
42 .
97 Ltd
VE 5pi
THD_RX
AR 6
10 d
INPUTS
M ru9
12 lan
TSU_RX
q
A# Zea
12

It is an input in this mode. NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.6.16 Switch Port 6 MII Tx Timing (MAC Mode) - 200 Mbps - 88E6218
Only
42 .
97 Ltd
Table 38: Switch Port 6 MII Transmit Timing (MAC Mode) - 200 Mbps - 88E6218 Only
In MAC mode, the P6_OUTCLK pin is an input.
10 d

12 lan
A# Zea
Sy mbol Para meter Condition Min Typ Ma x U nits Note s
TCQ_MAX P6_OUTCLK to outputs With 10 pF 7 ns
NDew
(P6_OUTD[3:0], load
P6_OUTDV valid
ER e N
TCQ_MIN P6_OUTCLK to outputs With 10pF load 0 ns
ND ar
(P6_OUTD[3:0],
, U ftw
P6_OUTDV invalid
AL o
TI W S
Figure 18: MAC Mode MII Transmit Timing - 200 Mbps

EN IJ
ID *
OUTCLK
NF 2yu
CO 1e3
LL -fg
OUTPUTS
42 .
97 Ltd
VE 5pi
TCQ_MAX TCQ_MIN
AR 6
10 d
M ru9
12 lan
q
A# Zea
12
NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.6.17 Switch Port 6 SNI Falling Edge Rx Timing - 88E6218 Only

Table 39: Switch Port 6 SNI Falling Edge Receive Timing - 88E6218 Only
42 .
97 Ltd
Symbol Pa rame te r Conditi on Min Ty p Ma x Un i ts No te s
10 d

12 lan
TP_FRX_CLK SNI falling edge INCLK 100 ns
period
A# Zea
TH_FRX_CLK SNI falling edge INCLK 35 50 65 ns
high
NDew
10BASE-T
TL_FRX_CLK SNI falling edge INCLK Mode 35 50 65 ns
ER e N
low
ND ar
TSU_FRX SNI receive data valid
, U ftw 20 ns
prior to INCLK going low
AL o
THD_FRX SNI receive data valid 10 ns

TI W S
after INCLK going low

EN IJ
Figure 19: SNI Falling Edge Receive Timing

ID *
NF 2yu
TH_FRX_CLK
CO 1e3
INCLK TL_FRX_CLK
LL -fg
42 .
97 Ltd
VE 5pi
TP_FRX_CLK
AR 6
10 d
M ru9
12 lan
INPUTS
q
A# Zea
12
THD_FRX
TSU_FRX
NDew
ER e N

ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.6.18 Switch Port 6 SNI Falling Edge Tx Timing - 88E6218 Only
42 .
Table 40: Switch Port 6 SNI Falling Edge Transmit Timing - 88E6218 Only
97 Ltd
10 d

12 lan
TP_FTX_CLK SNI falling edge OUTCLK 100 ns
A# Zea
period
TH_FTX_CLK SNI falling edge OUTCLK 35 50 65 ns
NDew
high
10BASE-T
ER e N
TL_FTX_CLK SNI falling edge OUTCLK Mode 35 50 65 ns
low
ND ar
TCQ_MXFTX
, U ftw
SNI falling edge OUTCLK 20 ns
to output valid
AL o
TI W S
TCQ_MNFTX SNI falling edge OUTCLK 10 ns

to output invalid
EN IJ
ID *
Figure 20: SNI Falling Edge Transmit Timing

NF 2yu
CO 1e3
TL_FTX_CLK
LL -fg
OUTCLK
42 .
TH_FTX_CLK
97 Ltd
VE 5pi
TP_FTX_CLK
AR 6
10 d
M ru9
12 lan
OUTPUTS
q
A# Zea
12
TCQ_MXFTX TCQ_MNFTX
NDew
ER e N

ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.6.19 Switch Port 6 SNI Rising Edge Rx Timing - 88E6218 Only
42 .
97 Ltd
Table 41: Switch Port 6 SNI Rising Edge Receive Timing - 88E6218 Only
10 d

12 lan
A# Zea
TP_RRX_CLK SNI rising edge INCLK 100 ns
period
NDew
TH_RRX_CLK SNI rising edge INCLK 35 50 65 ns
10BASE-T
high
ER e N
Mode
TL_RRX_CLK SNI rising edge INCLK 35 50 65 ns
ND ar
low , U ftw
TSU_RRX SNI receive data valid 20 ns
AL o
prior to INCLK going high

TI W S
THD_RRX SNI receive data valid 10 ns

after INCLK going high
EN IJ
ID *
NF 2yu
Figure 21: SNI Rising Edge Receive Timing

CO 1e3
TH_RRX_CLK
LL -fg
42 .
TL_RRX_CLK
97 Ltd
INCLK
VE 5pi
AR 6
10 d
TP_RRX_CLK
M ru9
12 lan
q
A# Zea
INPUTS
12
NDew
THD_RRX
TSU_RRX
ER e N

ND ar

, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.6.20 Switch Port 6 SNI Rising Edge Tx Timing - 88E6218 Only
42 .
97 Ltd
Table 42: Switch Port 6 SNI Rising Edge Transmit Timing - 88E6218 Only
10 d

12 lan
A# Zea
TP_RTX_CLK SNI rising edge OUTCLK 100 ns
period
NDew
TH_RTX_CLK SNI rising edge OUTCLK 35 50 65 ns
high
ER e N
10BASE-T
TL_RTX_CLK SNI rising edge OUTCLK Mode 35 50 65 ns
ND ar
low , U ftw
TCQ_MXRTX OUTCLK to output valid 20 ns
AL o
TCQ_MNRTX OUTCLK to output invalid 10 ns

TI W S
EN IJ
Figure 22: SNI Rising Edge Transmit Timing

ID *
NF 2yu
TL_RTX_CLK
CO 1e3
OUTCLK TH_RTX_CLK
LL -fg
42 .
97 Ltd
TP_RTX_CLK
VE 5pi
AR 6
10 d
M ru9
12 lan
OUTPUTS
q
A# Zea
TCQ_MXRTX TCQ_MNRTX
12

NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.6.21 Switch Port 6 RMII Rx Timing - 88E6218 Only

Table 43: Switch Port 6 RMII Receive Timing - 88E6218 Only
42 .
97 Ltd
10 d

12 lan
10BASE mode ns 1
A# Zea
TP_TX_CLK P[x]_INCLK period
NDew
100BASE 20 ns 1
ER e N
mode
ND ar
, U ftw
10BASE mode ns
AL o
TH_TX_CLK P[x]_INCLK high

TI W S
100BASE 8 10 12 ns
EN IJ
mode
ID *
NF 2yu
10BASE mode ns
CO 1e3
TL_TX_CLK P[x]_INCLK low

LL -fg
42 .
97 Ltd
100BASE 8 10 12 ns
VE 5pi
mode
AR 6
10 d
M ru9
12 lan
TSU_TX MII inputs (P6_IND[1:0], 7.5 ns
q
A# Zea
12

THD_TX MII inputs (P6_IND[1:0], 0 NDew ns
ER e N

ND ar

, U ftw
AL o
Figure 23: PHY Mode RMII Receive Timing

TI W S
TH_TX_CLK
EN IJ
ID *
INCLK TL_TX_CLK
NF 2yu
TP_TX_CLK
CO 1e3
LL -fg
INPUTS
VE 5pi
THD_TX
AR 6
M ru9
TSU_TX
q

12

4.6.22 Switch Port 6 RMII Tx Timing - 88E6218 Only

Table 44: Switch Port 6 RMII Transmit Timing - 88E6218 Only
42 .
97 Ltd
Sy mbol Para meter C ondition Min Typ Max Units Notes
10 d

12 lan
10BASE mode ns 1
A# Zea
TP_RX_CLK P[x]_OUTCLK period
NDew
100BASE 20 ns 1
ER e N
mode
ND ar
, U ftw
10BASE mode ns
TH_RX_CLK P[x]_OUTCLK high
AL o
TI W S
100BASE 8 10 12 ns
EN IJ
mode
ID *
NF 2yu
10BASE mode ns
CO 1e3
TL_RX_CLK P[x]_OUTCLK low

LL -fg
42 .
100BASE 8 10 12 ns
97 Ltd
VE 5pi
mode
AR 6
10 d
M ru9
12 lan
TCQ_MAX P6_OUTCLK to outputs 12.5 ns
(P6_OUTD[1:0],
q
A# Zea
P6_OUTDV) valid
12
TCQ_MIN P6_OUTCLK to outputs 0 NDew ns

P6_OUTD[1:0],
ER e N
P6_OUTDV) invalid
ND ar
, U ftw
Figure 24: PHY Mode RMII Transmit Timing

AL o
TI W S
TH_RX_CLK
EN IJ
TL_RX_CLK
ID *
OUTCLK
NF 2yu
TP_RX_CLK
CO 1e3
LL -fg
OUTPUTS
VE 5pi
TCQ_MAX TCQ_MIN
AR 6
M ru9

q
12

4.6.23 Two-Wire Serial Interface (TWSI) Timing

Table 45: Two-Wire Serial Interface (TWSI) Timing
42 .
97 Ltd
SDA setup, hold, and output delay times are referenced to SCL rising edge.
10 d

Symbol Pa r a m e te r C on d it io n M in Ty p Max U n i ts
12 lan
TFREQ SCL - TWSI Clock Frequency 400 kHz
A# Zea
TCYC SCL - TWSI Clock Clock Cycle 2.5 µs
TSU SDA - TWSI Data Setup 10 ns
NDew
TH SDA - TWSI Data Hold 5 ns
ER e N
TVAL SDA - TWSI Data Output Delay 1 15 ns
ND ar
, U ftw
Note
AL o
TI W S
The Two-Wire Serial Interface features a programmable clock. The driver (or SW application) must set the
clock speed for 100/400 kHz.
EN IJ
ID *
Figure 25: Two-Wire Serial Interface Timing

NF 2yu
CO 1e3
TCYC
LL -fg
42 .
97 Ltd
SCL
VE 5pi
THD TSU
AR 6
10 d
M ru9
12 lan
SDA
q
A# Zea
IN
12
TVAL NDew
SDA
ER e N
OUT
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

4.6.24 JTAG Timing
42 .
97 Ltd
Table 46: JTAG Timing
10 d

12 lan
Sy m b o l P a r a m e te r C o nd i tio n Min Typ Max U n i ts
A# Zea
TP_TCK TCK Period 100 ns
TH_TCK TCK High 40 ns
NDew
TL_TCK TCK Low 40 ns
ER e N
TSU_TDI TDI, TMS to TCK Setup 5 ns
Time
ND ar
THD_TDI
, U ftw
TDI, TMS to TCK Hold 20 ns
Time
AL o
TI W S
TDLY_TDO TCK to TDO Delay 1 15 ns

EN IJ
ID *
Figure 26: JTAG Timing

NF 2yu
CO 1e3
TP_TCK
TL_TCK TH_TCK
LL -fg
42 .
97 Ltd
VE 5pi
TCK
TSU_TDI THD_TDI
AR 6
10 d
M ru9
12 lan
TDI
TMS
q
A# Zea
12
TDLY_TDO
TDO
NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

IEEE AC Parameters
4.7 IEEE AC Parameters
42 .
97 Ltd
Table 47: IEEE AC Parameters
IEEE tests are typically based on templates and cannot simply be specified by number. For an exact description of the
10 d

12 lan
templates and the test conditions, refer to the IEEE specifications:
-10BASE-T IEEE 802.3 Clause 14-2000
A# Zea
-100BASE-TX ANSI X3.263-1995
-1000BASE-T IEEE 802.3ab Clause 40 Section 40.6.1.2 Figure 40-26 shows the template waveforms for transmitter
electrical specifications.
NDew
ER e N
ND ar
Symbol Parameter
, U ftw Pins Condition Min Typ Max Units
TRISE Rise time TXP/N[4:0] 100BASE-TX 3.0 4.0 5.0 ns
AL o
TFALL Fall time TXP/N[4:0] 100BASE-TX 3.0 4.0 5.0 ns

TI W S
TRISE/ TXP/N[4:0] 100BASE-TX 0 0.5 ns

TFALL
EN IJ
Symmetry
ID *
0.51
NF 2yu
DCD Duty cycle distortion TXP/N[4:0] 100BASE-TX 0 ns,

peak-
CO 1e3
peak
Transmit TXP/N[4:0] 100BASE-TX 0 1.4 ns,
LL -fg
Jitter peak-
42 .
97 Ltd
VE 5pi
peak
1. ANSI X3.263-1995 Figure 9-3.
AR 6
10 d
M ru9
12 lan
q
A# Zea
12
NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

Section 5. Package Mechanical Dimensions
42 .
97 Ltd
10 d

12 lan
Figure 27: Link Street™ 88E6208/88E6218 216-pin LQFP Package with Exposed Die Pad
A# Zea
D 1
NDew
D1 2
ER e N
4
109
ND ar
162
, U ftw
163 108
AL o
TI W S
P1 291.6750
EN IJ
ID *
NF 2yu
E1
P2
CO 1e3
E
2
291.6000
1
LL -fg
42 .
97 Ltd
VE 5pi
A A
AR 6
10 d
M ru9
12 lan
q
A# Zea
12
216 55
PIN 1 NDew
IDENTIFIER 1 54
ER e N
A A2
ND ar
-C-
A1 6 e
, U ftw
b 0.08 C
AL o
TI W S
O2
O1
EN IJ
R1
b 5 3
ID *
WITH PLATING
R2
NF 2yu
B
c c1
GAGE PLANE
CO 1e3
5 5
.25
O
BASE b1 5
LL -fg
METAL B
S
VE 5pi
SECTION B-B L
O3 L1
AR 6
M ru9
SECTION A-A
q
12

Package Mechanical Dimensions
42 .
97 Ltd
D ime nsi o n in mm
10 d

Symbol
12 lan
Min Nom M ax
A -- -- 1.60
A# Zea
A1 0.05 -- 0.15
NDew
A2 1.35 1.40 1.45
ER e N
b 0.13 0.18 0.23
b1 0.13 0.16 0.19
ND ar
, U ftw c 0.09 0.14 0.20
c1 0.09 0.12 0.16
AL o
TI W S
D 25.60 26.00 26.40

D1 -- 24.00 --
EN IJ
ID *
E 25.60 26.00 26.40

NF 2yu
E1 -- 24.00 --
CO 1e3
e 0.40 BSC
L 0.45 0.60 0.75
LL -fg
42 .
L1 1.00 REF
97 Ltd
VE 5pi
R1 0.08 -- --
AR 6
10 d
M ru9
R2 0.08 -- --
12 lan
S 0.20 -- --
q
A# Zea
12
P1 8.64 BSC
P2 8.64 BSC
NDew
θ 0° 3.5° 7°
ER e N
θ1 0° -- --
ND ar
θ2 11° 12° 13°

, U ftw
θ3 11° 12° 13°

AL o
TI W S
Note
EN IJ
ID *
NF 2yu
1. TO BE DETERMINED AT SEATING PLANE -C-.

CO 1e3
2. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE
DIMENSIONS INCLUDING MOLD MISMATCH.
LL -fg
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR CAN NOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
VE 5pi
4. EXACT SHAPE OF EACH CORNER IS OPTIONAL

AR 6
5. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 mm AND 0.25 mm FROM THE
M ru9
LEAD TIP.
6. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY.
q
12
7. CONTROLLING DIMENSION: MILLIMETER.

Section 6. Order Information
42 .
97 Ltd
10 d

12 lan
A# Zea
6.1 Ordering Part Numbers and Package Markings
Figure 28 shows the ordering part numbering scheme for the 88E6208/88E6218 devices. Contact Marvell FAEs or
NDew
sales representatives for complete ordering information.
ER e N
Figure 28: Sample Ordering Part Number
ND ar
, U ftw
88E62XX- XX - XXX - CXXX - T123
AL o
TI W S
Part Number Custom

EN IJ
88E6208 (optional)
ID *
88E6218
NF 2yu
Speed Code
133
CO 1e3
150
Temperature Range
LL -fg
C = Commercial, I = Industrial
42 .
97 Ltd
VE 5pi
Die Revision Package Code

AR 6
10 d
e.g., A0 = 1st Revision LGO - 216-pin LQFP
M ru9
12 lan
q
A# Zea
The standard ordering part numbers for the respective solutions are as follows:
12
• 88E6208-XX-LGO-C133 NDew
• 88E6218-XX-LGO-C133
ER e N
• 88E6218-XX-LGO-C150
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

Order Information
Ordering Part Numbers and Package Markings
Figure 29 shows a typical package marking and pin 1 location for the 88E6218 part. Markings for the other vari-
42 .
97 Ltd
ants are similar.
10 d

Figure 29: 88E6218 Package Marking and Pin 1 Location
12 lan
A# Zea
Logo
NDew
ER e N
88E6218-LGO Part number and package code
ND ar
Lot Number Date code, die revision, assembly plant code
, U ftw
YYWW xx@ Date code = YYWW
Die revision = xx
Country of origin Country
AL o
Assembly plant code = @

TI W S
(contained in the mold ID or C000

marked as the last line on Temperature Range and CPU speed
the package)
EN IJ
Pin 1 location
ID *
NF 2yu
CO 1e3
LL -fg
42 .
97 Ltd
VE 5pi
AR 6
10 d
M ru9
12 lan
q
A# Zea
12
NDew
ER e N
ND ar
, U ftw
AL o
TI W S
EN IJ
ID *
NF 2yu
CO 1e3
LL -fg
VE 5pi
AR 6
M ru9
q
12

42 .
97 Ltd
Marvell Semiconductor, Inc.
700 First Avenue
10 d

Sunnyvale, CA 94089
12 lan
Phone 408.222.2500
Fax 408.752.9028
A# Zea
www.marvell.com
NDew
ER e N
US and Worldwide Offices Worldwide Sales Offices Israel Sales Office
ND ar
Marvell
Marvell Semiconductor, Inc.
, U ftw Western US Sales Office
Ofek Center Bldg. 2, Floor 2
700 First Avenue Marvell
Northern Industrial Zone
Sunnyvale, CA 94089 700 First Avenue
AL o
LOD 71293
Tel: 1.408.222.2500 Sunnyvale, CA 94089
TI W S
Israel
Fax: 1.408.752.9028 Tel: 1.408.222.2500
Tel: 972.8.924.7555
Fax: 1.408.752.9028
Marvell Asia Pte, Ltd. Fax: 972.8.924.7554
Sales Fax: 1.408.752.9029
EN IJ
151 Lorong Chuan, #02-05

China Sales Office
New Tech Park Central US Sales Office
Marvell
ID *
Singapore 556741 Marvell

5J, 1800 Zhong Shan West Road
NF 2yu
Tel: 65.6756.1600 11709 Boulder Lane, Ste. #220

Shanghai, China 200233
Fax: 65.6756.7600 Austin, TX 78726
Tel: 86.21.6440.1350
Tel: 1.512.336.1551
CO 1e3
Marvell Japan K.K. Fax: 86.21.6440.0799

Fax: 1.512.336.1552
Shinjuku Center Bldg. 50F
Japan Sales Office
1-25-1, Nishi-Shinjuku, Shinjuku-ku Eastern US/Canada Sales Office
LL -fg
Marvell
Tokyo 163-0650 Marvell
42 .
Helios Kannai Bldg. 12F
97 Ltd
Tel: 81.(0).3.5324.0355 Parlee Office Park
VE 5pi
3-21-2 Motohama-cho, Naka-ku

Fax: 81.(0).3.5324.0354 1 Meeting House Road, Suite 1
Yokohama, Kanagawa
Chelmsford, MA 01824
Japan 231-0004
AR 6
10 d
Marvell Semiconductor Israel, Ltd.
Tel: 978 250-0588
M ru9
Tel: 81.45.222.8811
12 lan
Moshav Manof
Fax: 978 250-0589
D.N. Misgav 20184 Fax: 81.45.222.8812
Israel
q
A# Zea
Taiwan Sales Office
Tel: 972.4.999.9555 Europe Sales Office
12
Marvell
Fax: 972.4.999.9574 Marvell 2Fl., No. 1, Alley 20, Lane 407
3 Clifton CourtNDew Ti-Ding Blvd., Nei Hu District
Corner Hall
Taipei, Taiwan 114, R. O. C
Hemel Hempstead
ER e N
Tel: (886-2).7720.5700
Hertfordshire, HP3 9XY
United Kingdom FAX: (886-2).7720.5707
ND ar
Tel: 44.(0).1442.211668
Fax: 44.(0).1442.211543
, U ftw
Marvell
Fagerstagatan 4
AL o
163 08 Spanga
TI W S
Stockholm, Sweden
Tel: 46.16.146348
Fax: 46.16.482425
EN IJ
Marvell
ID *
5 Rue Poincare
NF 2yu
56400 Le Bono
France
CO 1e3
Tel: 33.297.579697
Fax: 33.297.578933
LL -fg
VE 5pi
AR 6
M ru9
q
For more information, visit our website at:

12
www.marvell.com
Copyright © 2003 Marvell. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, and GalNet are registered trademarks of Marvell.
Discovery, Fastwriter, GalTis, Horizon, Libertas, Link Street, NetGX, PHY Advantage, Prestera, Raise The Technology Bar, UniMAC, Virtual Cable Tester,
and Yukon are trademarks of Marvell. All other trademarks are the property of their respective owners.

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MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Doc. No. MV-S101300-01, Rev. A

12qru965pi-fg1e32yu * IJW Software New Zealand Ltd. * UNDER NDA# 12109742

12qru965pi-fg1e32yu * IJW Software New Zealand Ltd. * UNDER NDA# 12109742

site at www.marvell.com for the latest information on Marvell products.

Doc. No. MV-S101300-01, Rev. A CONFIDENTIAL Copyright © 2003 Marvell

12qru965pi-fg1e32yu * IJW Software New Zealand Ltd. * UNDER NDA# 12109742

The 88E6218 has a higher CPU clock speed to

(88E6218 only) wide, addressing up to 64 MB

enhance the performance of software security func-

port for connecting to other networking devices such

tering and priority queueing under DMA control

M_A[21:0] NDew SMI (88E6218)

(88E6218) Dual DMA Switch & PHY Registers PHY LED

BOOTCSn Port 6's MAC or PHY

Port 4's 100BASE-TX

XTAL_IN Look-up MAC Transceiver

Port 3's 100BASE-TX

88E6218 Port 2's 100BASE-TX

RESETn Timers & Interrupts

GPIO, LEDs, EEPROM Switch w/Auto Crossover RX1

UART MAC Transceiver

Copyright © 2003 Marvell CONFIDENTIAL Doc. No. MV-S101300-01, Rev. A

12qru965pi-fg1e32yu * IJW Software New Zealand Ltd. * UNDER NDA# 12109742

– 1 WAN Port: Copper TX or Fiber FX enabling end-user connection of either Straight or

office network management: TX Frame Count,

duplex operation, directly connects at full-speed

Wireless LAN (88E6218 only) • Low-power CMOS IC

nects the switch to the CPU’s MAC at 200 Mbps

Fe ature 88E62 08 88E62 18

8K Data Tightly-Coupled Memory No Yes

Internal DMA No Yes

External Memory Width 16-bits 32-bits

Maximum Flash Size 8 MB 64 MB

External Chip Selects 3 - BootCSn, 4 - BootCSn,

M_STATUS pin for Flash Memory No1 Yes

Address Bus pins M_A[21:0] M_A[23:0]

UniMAC™ QoS No Yes - 4 Queues

External MII No Yes

Switch QoS No Yes - 4 Queues

Egress Rate Shaping No Yes

Embedded Memory 0.5 Mb 1 Mb

1. A GPIO pin can be used instead.

Doc. No. MV-S101300-01, Rev. A CONFIDENTIAL Copyright © 2003 Marvell

Page 4 Document Classification: Proprietary Information October 7, 2003, Advanced

12qru965pi-fg1e32yu * IJW Software New Zealand Ltd. * UNDER NDA# 12109742

1.1 Pin Description..........................................................................................................................15

SECTION 2. RESET AND INITIALIZATION .................................................................... 41

SECTION 3. FUNCTIONAL DESCRIPTION.................................................................... 45

3.1 UniMAC Interface Options .......................................................................................................46

SECTION 4. ELECTRICAL SPECIFICATIONS................................................................ 48

4.2 Recommended Operating Conditions ....................................................................................49

4.3 Notes on Powering Up and Powering Down ..........................................................................49

4.4 Package Thermal Data..............................................................................................................50

4.4.1 Thermal Conditions for 216-pin LQFP Package........................................................................50

4.5 DC Electrical Characteristics ...................................................................................................51

4.5.1 DC Power Characteristics .........................................................................................................51

4.5.2 Digital Operating Conditions......................................................................................................52

4.6 AC Electrical Specifications ....................................................................................................55

4.6.1 Asynchronous Signals...............................................................................................................55

4.6.3 Clock Timing when using a 25 MHz Oscillator ..........................................................................56

4.6.4 Serial Management Interface Timing ........................................................................................57

4.6.5 SDRAM/Device Interface Timing...............................................................................................58

Copyright © 2003 Marvell CONFIDENTIAL Doc. No. MV-S101300-01, Rev. A