for LABELID component ID [is]

[{block_config | comp_config}] [generic ( {ID : TYPEID [:= expr];} );]

end for; [port ({ID : in | out | inout TYPEID [:= expr];});]
comp_config::= end component [COMPID];
for all | LABELID : COMPID [impure | pure] function ID
(use entity [LIBID.]ENTITYID [( ARCHID )] [( {[constant | variable | signal | file] ID :
[[generic map ( {GENID => expr ,} )] [in]TYPEID [:= expr];})]
port map ({PORTID => SIGID | expr ,})]; return TYPEID [is
[for ARCHID begin
VHDL QUICK [{block_config | comp_config}]
end for;]
{sequential_statement}
end [function] ID];
REFERENCE CARD end for;) |
(use configuration [LIBID.]CONFID
procedure ID[({[constant | variable | signal] ID :
Revision 2.2 in | out | inout TYPEID [:= expr];})]
[[generic map ({GENID => expr ,})] [is begin
() Grouping [] Optional port map ({PORTID => SIGID | expr,})];)
{} Repeated | Alternative [{sequential_statement}]
end for; end [procedure] ID];
bold As is CAPS User Identifier
italic VHDL-1993 for LABELID | others | all : COMPID use
2. DECLARATIONS
(entity [LIBID.]ENTITYID [( ARCHID )]) |
1. LIBRARY UNITS 2.1. TYPE DECLARATIONS (configuration [LIBID.]CONFID)
[{use_clause}] type ID is ( {ID,} ); [[generic map ( {GENID => expr,} )]
entity ID is port map ( {PORTID => SIGID | expr,} )];
type ID is range number downto | to number;
[generic ({ID : TYPEID [:= expr];});]
[port ({ID : in | out | inout TYPEID [:= expr];});] type ID is array ( {range | TYPEID ,}) of TYPEID; 3. EXPRESSIONS
[{declaration}] type ID is record expression ::=
[begin {ID : TYPEID;} (relation and relation) | (relation nand relation) |
{parallel_statement}] end record; (relation or relation) | (relation nor relation) |
end [entity] ENTITYID; (relation xor relation) | (relation xnor relation)
type ID is access TYPEID;
[{use_clause}] relation ::= shexpr [relop shexpr]
type ID is file of TYPEID;
architecture ID of ENTITYID is
subtype ID is SCALARTYPID range range; shexpr ::= sexpr [shop sexpr]
[{declaration}]
begin subtype ID is ARRAYTYPID( {range,}); sexpr ::= [+|-] term {addop term}
[{parallel_statement}] term ::= factor {mulop factor}
subtype ID is RESOLVFCTID TYPEID;
end [architecture] ARCHID; factor ::=
range ::=
[{use_clause}] (prim [** prim]) | (abs prim) | (not prim)
(integer | ENUMID to | downto integer | ENUMID) |
package ID is prim ::=
(OBJID’[reverse_]range) | (TYPEID range <>)
[{declaration}] literal | OBJID | OBJID’ATTRID | OBJID({expr,})
end [package] PACKID; 2.2. OTHER DECLARATIONS | OBJID(range) | ({[choice [{| choice}] =>] expr,})
[{use_clause}] constant ID : TYPEID := expr; | FCTID({[PARID =>] expr,}) | TYPEID’(expr) |
package body ID is TYPEID(expr) | new TYPEID[‘(expr)] | ( expr )
[shared] variable ID : TYPEID [:= expr];
[{declaration}]
signal ID : TYPEID [:= expr]; choice ::= sexpr | range | RECFID | others
end [package body] PACKID;
[{use_clause}] file ID : TYPEID (is in | out string;) | 3.1. OPERATORS, INCREASING PRECEDENCE
configuration ID of ENTITYID is (open read_mode | write_mode | logop and | or | xor | nand | nor | xnor
for ARCHID append_mode is string;) relop = | /= | < | <= | > | >=
[{block_config | comp_config}] alias ID : TYPEID is OBJID; shop sll | srl | sla | sra | rol | ror
end for; addop +|-|&
attribute ID : TYPEID;
end [configuration] CONFID; mulop * | / | mod | rem
attribute ATTRID of OBJID | others | all : class is expr; miscop ** | abs | not
use_clause::=
library ID; class ::=
[{use LIBID.PKGID[. all | DECLID];}] entity | architecture | configuration |
procedure | function | package | type |
subtype | constant | signal | variable | 1995-2000 Qualis Design Corporation. Permission to
block_config::= component | label reproduce and distribute strictly verbatim copies of this
document in whole is hereby granted.

See reverse side for additional information.

© 1995-2000 Qualis Design Corporation © 1995-2000 Qualis Design Corporation
4. SEQUENTIAL STATEMENTS [LABEL:] [postponed] assert expr SIGID’event Event on signal ?
[report string] SIGID’active Activity on signal ?
wait [on {SIGID,}] [until expr] [for time];
[severity note | warning | error | failure]; SIGID’last_event Time since last event
assert expr SIGID’last_active Time since last active
[LABEL:] [postponed] SIGID <=
[report string] SIGID’last_value Value before last event
[transport] | [[reject TIME] inertial]
[severity note | warning | error | failure]; SIGID’driving Active driver predicate
[{{expr [after TIME,]} | unaffected when expr else}]
report string {expr [after TIME,]} | unaffected; SIGID’driving_value Value of driver
[severity note | warning | error | failure]; OBJID’simple_name Name of object
[LABEL:] [postponed] with expr select OBJID’instance_name Pathname of object
SIGID <= [transport] | [[reject TIME] inertial] SIGID <= [transport] | [[reject TIME] inertial] OBJID’path_name Pathname to object
{expr [after time],}; {{expr [after TIME,]} | unaffected
VARID := expr; when choice [{| choice}]}; 7. PREDEFINED TYPES
PROCEDUREID[({[PARID =>] expr,})]; LABEL: COMPID BOOLEAN True or false
[[generic map ( {GENID => expr,} )] INTEGER 32 or 64 bits
[LABEL:] if expr then
{sequential_statement} port map ( {[PORTID =>] SIGID | expr,} )]; NATURAL Integers >= 0
[{elsif expr then LABEL: entity [LIBID.]ENTITYID [(ARCHID)] POSITIVE Integers > 0
{sequential_statement}}] [[generic map ( {GENID => expr,} )] REAL Floating-point
[else port map ( {[PORTID =>] SIGID | expr,} )]; BIT ‘0’, ‘1’
{sequential_statement}] BIT_VECTOR(NATURAL) Array of bits
LABEL: configuration [LIBID.]CONFID
end if [LABEL]; CHARACTER 7-bit ASCII
[[generic map ( {GENID => expr,} )]
STRING(POSITIVE) Array of characters
[LABEL:] case expr is port map ( {[PORTID =>] SIGID | expr,} )];
TIME hr, min, sec, ms,
{when choice [{| choice}] => LABEL: if expr generate us, ns, ps, fs
{sequential_statement}} [{parallel_statement}] DELAY_LENGTH Time >= 0
end case [LABEL]; end generate [LABEL];
[LABEL:] [while expr] loop LABEL: for ID in range generate 8. PREDEFINED FUNCTIONS
{sequential_statement} [{parallel_statement}] NOW Returns current simulation time
end loop [LABEL]; end generate [LABEL]; DEALLOCATE(ACCESSTYPOBJ)
[LABEL:] for ID in range loop Deallocate dynamic object
{sequential_statement} 6. PREDEFINED ATTRIBUTES FILE_OPEN([status], FILEID, string, mode)
end loop [LABEL]; TYPID’base Base type Open file
next [LOOPLBL] [when expr]; TYPID’left Left bound value FILE_CLOSE(FILEID) Close file
exit [LOOPLBL] [when expr]; TYPID’right Right-bound value
TYPID’high Upper-bound value 9. LEXICAL ELEMENTS
return [expression]; TYPID’low Lower-bound value Identifier ::= letter { [underline] alphanumeric }
null; TYPID’pos(expr) Position within type decimal literal ::=integer [. integer] [E[+|-] integer]
TYPID’val(expr) Value at position
5. PARALLEL STATEMENTS TYPID’succ(expr) Next value in order based literal ::=
TYPID’pred(expr) Previous value in order integer # hexint [. hexint] # [E[+|-]
LABEL: block [is] integer]
[generic ( {ID : TYPEID;} ); TYPID’leftof(expr) Value to the left in order
[generic map ( {[GENID =>] expr,} );]] TYPID’rightof(expr) Value to the right in order bit string literal ::= B|O|X “ hexint “
[port ( {ID : in | out | inout TYPEID } ); TYPID’ascending Ascending type predicate comment ::= -- comment text
[port map ( {[PORTID =>] SIGID | expr,} )];] TYPID’image(expr) String image of value
[{declaration}] TYPID’value(string) Value of string image
begin ARYID’left[(expr)] Left-bound of [nth] index
[{parallel_statement}] ARYID’right[(expr)] Right-bound of [nth] index
end block [LABEL]; ARYID’high[(expr)] Upper-bound of [nth] index
© 1995-2000 Qualis Design Corporation. Permission to
ARYID’low[(expr)] Lower-bound of [nth] index
[LABEL:] [postponed] process [( {SIGID,} )] reproduce and distribute strictly verbatim copies of this
ARYID’range[(expr)] ‘left down/to ‘right
[{declaration}] document in whole is hereby granted.
ARYID’reverse_range[(expr)] ‘right down/to ‘left
begin ARYID’length[(expr)] Length of [nth] dimension
[{sequential_statement}]
Qualis Design Corporation
ARYID’ascending[(expr)] ‘right >= ‘left ?
end [postponed] process [LABEL]; Elite Training / Consulting in Reuse and Methodology
SIGID’delayed[(TIME)] Delayed copy of signal
[LBL:] [postponed] PROCID({[PARID =>] expr,}); SIGID’stable[(TIME)] Signals event on signal
Phone: +1-503-670-7200 FAX: +1-503-670-0809
SIGID’quiet[(TIME)] Signals activity on signal E-mail: info@qualis.com com Web:www.qualis.com
SIGID’transaction Toggles if signal active
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© 1995-2000 Qualis Design Corporation © 1995-2000 Qualis Design Corporation