9/21/2019 Memory Modeling Language Specification

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9/21/2019 Memory Modeling Language Specification

Memory Modeling Syntax in Backus-Naur Form (BNF)

This section describes the BNF memory modeling syntax, which is a restricted subset of the Verilog
language used for modeling of RAMs and ROMs. Constructs identical to the Verilog BNF definition are not
described. Refer to IEEE Std 1364-1995 for the syntax definitions of standard Verilog.

memory_definition ::= { contention_mode } module_declaration {

contention_defaults }
contention_mode ::= rr_contention | rw_contention | ww_contention
module_declaration ::= module module_identifier [ list_of_ports ] ; {
module_item } endmodule
contention_defaults ::= rr_undef | rw_undef | ww_undef
list_of_ports ::= (port_identifier {,port_identifier } )
module_item ::= module_item_declaration | read_port | write_port | set_port |
reset_port | memory_initialization | gate_instantiation | udp_instantiation
module_item_declaration ::= data_out_reg_declaration | memory_declaration |
parameter_declaration | input_declaration | output_declaration |
inout_declaration | net_declaration | reg_declaration | integer_declaration |
event_declaration
data_out_reg_declaration ::= reg data_range data_out_reg_identifier;
memory_declaration ::= reg data_range memory_name_identifier address_range ;
data_range ::= [ data_high_bit : data_low_bit ]
address_range ::= [ address_low : address_high ]
read_port ::= level_sensitive_read_port | edge_sensitive_read_port
write_port ::= level_sensitive_write_port | edge_sensitive_write_port
set_port ::= always @ set_control_net if ( [!] set_control_net ) 1_fill
reset_port ::= always @ reset_control_net if ( [!] reset_control_net ) 0_fill
level_sensitive_read_port ::= always @ ( read_sensitivity_list ) if ( [!]
control_net ) read_assign [ else data_out_reg = bus_constant ; ]
edge_sensitive_read_port ::= always @ ( edge read_control_net ) [ if ( [!]
control_net ) ] read_assign
level_sensitive_write_port ::= always @ ( write_sensitivity_list ) if ( [!]
control_net ) write_assign
edge_sensitive_write_port ::= always @ ( edge write_control_net ) [if ( [!]
control_net ) ] write_assign
read_assign ::= data_out_reg = memory_name [ address_net ] ;
write_assign ::= begin memory_name [ address_net ] = data_in_net ;#0; -
>event_identifier; end
read_sensitivity_list ::= read_control_net [ or address_net ] [
orevent_identifier ]
write_sensitivity_list ::= write_control_net or address_net or data_in_net
control_net ::= net_identifier
read_control_net ::= net_identifier
write_control_net ::= net_identifier
set_control_net ::= net_identifier
reset_control_net ::= net_identifier
address_net ::= bus_identifier
data_in_net ::= bus_identifier
memory_initialization ::= initial readmem_type ( filespec , memory_name ) ;
readmem_type ::= $readmemh | $readmemb
filespec ::= " filepath "
0_fill ::= for ( i=0; i < max_address ; i=i+1 ) memory_name [ i ] = 0_constant
;

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9/21/2019 Memory Modeling Language Specification
1_fill ::= for ( i=0; i < max_address ; i=i+1 ) memory_name [ i ] = 1_constant
;
edge ::= posedge | negedge
rr_contention ::= `define read_read rr_choices
rw_contention ::= `define read_write rw_choices
ww_contention ::= `define write_write ww_choices
rr_choices :: = normal | readx
rw_choices ::= mixed | new | readx | xfill| new_but_readx_across_ports
ww_choices ::= xbit | xword | xfill | dominance | forbidden
rr_undef ::= `undef read_read
rw_undef ::= `undef read_write
ww_undef ::= `undef write_write
data_high_bit ::= decimal_number
data_low_bit ::= decimal_number
address_low ::= decimal_number
address_high ::= decimal_number
max_address ::= decimal_number
bus_constant ::= 0_constant | 1_constant | x_constant | z_constant
0_constant :: = size base { 0 }+
1_constant :: = size base { 1 }+
x_constant :: = size base { x }+
z_constant :: = size base { z }+
size ::= decimal_digit { decimal_digit }
base ::= 'b | 'B | 'h | 'H
digit ::= dec_digit | hex_digit | sim_digit
decimal_digit ::= 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
decimal_number ::= { decimal_digit }+
hex_digit ::= decimal_digit | a | A | b | B | c | C | d | D | e | E | f | F
binary_digit ::= x | X | z | Z | 0 | 1
bus_identifier ::= net_identifier
net_identifier ::= <standard Verilog syntax>
module_identifier ::= <standard Verilog syntax>
port_identifier :: = <standard Verilog syntax>
parameter_declaration ::= <standard Verilog syntax>
input_declaration ::= <standard Verilog syntax>
output_declaration ::= <standard Verilog syntax>
inout_declaration ::= <standard Verilog syntax>
net_declaration ::= <standard Verilog syntax>
reg_declaration ::= <standard Verilog syntax>
integer_declaration ::= <standard Verilog syntax>
gate_instantiation ::= <standard Verilog syntax>
udp_instantiation ::= <standard Verilog syntax>
event_declaration ::= <standard Verilog syntax>
See Also

Memory Examples

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