ECE 274 – Digital Logic

Combinational Logic Design Process Digital Design

Chapter 2:
Digital Design (Vahid): Ch. 2.7-2.10
Combinational Logic Design
Slides to accompany the textbook Digital Design, First Edition,
by Frank Vahid, John Wiley and Sons Publishers, 2007.
http://www.ddvahid.com

Copyright © 2007 Frank Vahid

Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities,
subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf
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2
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2.7

Combinational Logic Design Process Example: Three 1s Detector

Step Description • Problem: Detect three consecutive 1s
in 8-bit input: abcdefgh
Step 1 Capture the Create a truth table or equations, whichever is • 00011101 Æ 1 10101011 Æ 0
function most natural for the given problem, to describe 11110000 Æ 1
the desired behavior of the combinational logic. – Step 1: Capture the function
Step 2 Convert to This step is only necessary if you captured the • Truth table or equation?
– Truth table too big: 2^8=256 rows a
equations function using a truth table instead of equations. a
– Equation: create terms for each
Create an equation for each output by ORing all the possible case of three consecutive 1s
a
b abc
minterms for that output. Simplify the equations if c
• y = abc + bcd + cde + def + efg + fgh
desired. bcd
– Step 2: Convert to equation -- already d
Step 3 Implement For each output, create a circuit corresponding done cde
e y
as a gate- to the output’s equation. (Sharing gates among – Step 3: Implement as a gate-based
def
based multiple outputs is OK optionally.) circuit f
circuit
efg
g
fgh
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Example: Number of 1s Count Example: Prime Number Detector

• Problem: Output in binary on
two outputs yz the number of 1s
on three inputs
• 010 Æ 01 101 Æ 10 000 Æ 00
– Step 1: Capture the function
• Truth table or equation?
– Truth table is straightforward
– Step 2: Convert to equation
• y = a’bc + ab’c + abc’ + abc
• z = a’b’c + a’bc’ + ab’c’ + abc
– Step 3: Implement as a gate-
based circuit
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Frank Vahid
Problem: Create a 4-bit prime number detector. The
circuit has four inputs, N3, N2, N1, and N0
that correspond to a 4-bit number (N3 is the
most significant bit) and one output labeled P
that outputs a 1 when the input is a prime
number, 0 otherwise.
a
b
a c
b
c a
b
a y c z
b
c a
b
a c
b a
b
c
5 6

1
 2.8

Example: Squared Number Detector More Gates

1 1
NAND NOR XOR XNOR NAND NOR
x x x
Problem: Create a 4-bit squared number detector. The y
F
y
F x y

circuit has four inputs, N3, N2, N1, and N0 F y

x y F x y F x y F x y F
that correspond to a 4-bit number (N3 is the 0 0 1 0 0 1 0 0 0 0 0 1
x F

most significant bit) and one output labeled S 0 1 1 0 1 0 0 1 1 0 1 0

y
x y
1 0 1 1 0 0 1 0 1 1 0 0
that outputs a 1 when the input is the square 1 1 0 1 1 0 1 1 0 1 1 1 0 0
of a positive integer, 0 otherwise.
• NAND: Opposite of AND (“NOT AND”) • NAND same as AND with power &
• NOR: Opposite of OR (“NOT OR”) ground switched
• XOR: Exactly 1 input is 1, for 2-input • Why? nMOS conducts 0s well, but not
XOR. (For more inputs -- odd number 1s (reasons beyond our scope) -- so
of 1s) NAND more efficient
• XNOR: Opposite of XOR (“NOT XOR”) • Likewise, NOR same as OR with
power/ground switched
• AND in CMOS: NAND with NOT
• OR in CMOS: NOR with NOT
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• So NAND/NOR more common
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Frank Vahid

More Gates: Example Uses Completeness of NAND

Circuit • Any Boolean function can be implemented using just
• Aircraft lavatory sign
example
a
b S
NAND gates. Why?
c
– Need AND, OR, and NOT
– S = (abc)’
– NOT: 1-input NAND (or 2-input NAND with inputs tied together)
• Detecting all 0s 0
0
0
1 a0 – AND: NAND followed by NOT
– Use NOR b0
– OR: NAND preceded by NOTs
• Detecting equality a1 A=B
• Likewise for NOR
b1
– Use XNOR
a2
• Detecting odd # of 1s b2

– Use XOR
– Useful for generating “parity”
bit common for detecting
errors
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2.9

Number of Possible Boolean Functions Decoders and Muxes

• How many possible functions of 2 a b F • Decoder: Popular combinational
variables? 0 0 0 or 1 2 choices logic building block, in addition to
0 1 0 or 1 2 choices d0 1 d0 0 d0 0 d0 0
– 22 rows in truth table, 2 choices for each 1 0 0 or 1 2 choices logic gates
2 0 i0 d1 0 1 i0 d1 1 0 i0 d1 0 1 i0 d1 0
– 2(2 ) = 24 = 16 possible functions 1 1 0 or 1 2 choices – Converts input binary number to
0 i1 d2 0 0 i1 d2 0 1 i1 d2 1 1 i1 d2 0
• N variables one high output
24 = 16 d3 0 d3 0 d3 0 d3 1
– 2Nrows possible functions • 2-input decoder: four possible
N
– 2(2 ) possible functions
input binary numbers
– So has four outputs, one for each d0 0
i1’i0’ d0
possible input binary number 1 i0 d1 0
a b f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 • Internal design i1’i0 d1 1 i1 d2 0
0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
– AND gate for each output to e d3 1
1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 i1i0’ d2
1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
detect input combination 1
• Decoder with enable e i1i0 d3 d0 0
a

a NOR b

1
b

a OR b

a NAND b
0

a AND b

a XOR b

a XNOR b

b’

a’

' '

0 1

– Outputs all 0 if e=0

b

b
R
O
1 i0 d1 0
X

– Regular behavior if e=1

b
R
O
a

b
D
N
A
a
a

b
R
O
N
a

b
R
O
N
X
a
1 i1 d2 0
b
D
A
N
a

• n-input decoder: 2n outputs e d3 0

i1 i0
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2
 Decoder Example Multiplexor (Mux)
• New Year’s Eve 210 21 0 0
Happy • Mux: Another popular combinational building block
0 1 0 0 0 1 New Year
Countdown Display 1 0 0
i0 d0
0 1 0
– Routes one of its N data inputs to its one output, based on binary
i1 d1 1
– Microprocessor counts 0 0 0 i2 d2 1 0 0 2 value of select inputs
0 0 0 i3 d3 0 0 0 3 • 4 input mux Æ needs 2 select inputs to indicate which input to route
r
so
e

from 59 down to 0 in
c

a
0 0 0 i4
r

binary on 6-bit output p

o

ci

0 0 0 i5 through
– Want illuminate one of
M

d58 0 0 0 • 8 input mux Æ 3 select inputs

e d59 0 0 0
60 lights for each binary d60 • N inputs Æ log2(N) selects
d61 58
number 59 – Like a railyard switch
6x64 d62
– Use 6x64 decoder dcd d63

• 4 outputs unused

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Mux Internal Design Mux Example

i0 i0 (1*i0=i0)
2×1 2×1 2×1 d • City mayor can set four switches up or down, representing
1 i0
i0
d
i0
d
i0
d
i1
0 (0+i0=i0)
his/her vote on each of four proposals, numbered 0, 1, 2,
i1 i1 i1
0 3
s0 s0 s0
a
0 1
• City manager can display any such vote on large
2x1 mux 0 s0
green/red LED (light) by setting two switches to represent
binary 0, 1, 2, or 3 Mayor’s switches
i0

i0
4⋅ 1
• Use 4x1 mux 1
i1 4x1 on/off
i1 d
d i0
i2 i2
2 i1
i3 d
i3 i2
s1 s0
r

i3 Green/
3
P

s1 s0 Red
4x1 mux LED

s1 s0 4
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Muxes Commonly Together -- N-bit Mux N-bit Mux Example

2⋅ 1
a3 i0 Simplifying
d
b3 i1 notation:
s0
4-bit 4
2⋅ 1 4 C
a2 i0 2x1
d A I0 4
b2 i1 D C is short
s0 4
B I1 for
2⋅ 1
a1 i0 s0
d
b1 i1 c3
s0
s0 c2
i0 2⋅ 1
a0
d c1
b0 i1
s0
s0 c0

• Four possible display items

• Ex: Two 4-bit inputs, A (a3 a2 a1 a0), and B (b3 b2 b1 b0) – Temperature (T), Average miles-per-gallon (A), Instantaneous mpg (I),
– 4-bit 2x1 mux (just four 2x1 muxes sharing a select line) can and Miles remaining (M) -- each is 8-bits wide
– Choose which to display using two inputs x and y
select between A or B
– Use 8-bit 4x1 mux
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3
 2.10
Additional Considerations Additional Considerations
Schematic Capture and Simulation Non-Ideal Gate Behavior -- Delay
Inputs Inputs
i0 i0
i1 i1
Simulate Simulate
Outputs Outputs
d3 d3

d2 d2

d1 d1

d0 d0

• Schematic capture
– Computer tool for user to capture logic circuit graphically
• Simulator • Real gates have some delay
– Computer tool to show what circuit outputs would be for given inputs – Outputs don’t change immediately after inputs change
• Outputs commonly displayed as waveform
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Additional Considerations Design Challenge

Encoders
• Encoder: Combinational logic • Design Challenge
building block with opposite
functionality of decoder 1 d0 0 d0 0 d0 0 d0 – Design a 4x2 encoder using AND, OR, and NOT gates.
– Outputs binary encoding for input 0 d1 e0 0 1 d1 e0 1 0 d1 e0 0 0 d1 e0 1
signal that is 1 0 d2 e1 0 0 d2 e1 0 1 d2 e1 1 0 d2 e1 1
– 4x2 encoder would have four inputs 0 d3 0 d3 0 d3 1 d3
and 2 outputs

• What if two inputs are 1?

– Can use a priority encoder 0 d0
– Gives priority to the highest input that 1 d1 e0 1
is 1, and outputs binary encoding for 0 d2 e1 1
that input 1 d3
– Example: If d3=1 and d1=1, will
output e0=1 and e1=1 because d3
has priority
Due Next Lecture (as announced in class)
21 1 point extra credit (Homework) 22