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Introduction to
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vid /2 Electronics
rπ βib1 βib2 rπ vid /2
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An
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Online
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Text
(β+1)i
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Bob Zulinski
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Associate Professor
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of Electrical
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+ Engineering
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ib1 o1 o2 ib2
Michigan Technological University
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vid /2 rπ βib1 βib2 rπ vid /2
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Version 2.0
Introduction to Electronics ii
Dedication
Table of Contents
Preface xvi
Philosophy of an Online Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi
Notes for Printing This Document . . . . . . . . . . . . . . . . . . . . . . . . xviii
Copyright Notice and Information . . . . . . . . . . . . . . . . . . . . . . . . xviii
Amplifier Cascades 13
Decibel Notation 14
Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Cascaded Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Current Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Using Decibels to Indicate Specific Magnitudes . . . . . . . . . . . . . . . . . . . 15
Voltage levels: 15
Power levels 16
Differential Amplifiers 27
Example: 27
Modeling Differential and Common-Mode Signals . . . . . . . . . . . . . . . . . 27
Amplifying Differential and Common-Mode Signals . . . . . . . . . . . . . . . . 28
Common-Mode Rejection Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Diodes 46
Diode Models 50
The Shockley Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Forward Bias Approximation 51
Reverse Bias Approximation 51
At High Currents 51
The Ideal Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
An Ideal Diode Example 53
Piecewise-Linear Diode Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
A Piecewise-Linear Diode Example 57
Other Piecewise-Linear Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Notation 142
DC Imperfections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Input Offset Voltage, VIO 195
Input Currents 195
Modeling the DC Imperfections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Using the DC Error Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
DC Output Error Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Finding Worst-Case DC Output Error 201
Canceling the Effect of the Bias Currents . . . . . . . . . . . . . . . . . . . . . . 203
Noise 206
Johnson Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Johnson Noise Model 207
Shot Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
1/f Noise (Flicker Noise) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Other mechanisms producing 1/f noise 209
Interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Preface
The technology of the Internet and the World Wide Web now allows
us to virtually give away knowledge! Yet, we don’t, choosing
instead to write another conventional text book, and print, sell, and
use it in the conventional manner. The “whys” are undoubtedly
intricate and many; I offer only a few observations:
1
I use the word “supposedly” because, in my view, the official rewards for textbook
authoring fall far short of what is appropriate and what is achievable through an equivalent
research effort, despite all the administrative lip service to the contrary. These arguments,
though, are more appropriately left to a different soapbox.
Introduction to Electronics xvii
You may also note that exercise problems are not included with this
text. By their very nature problems quickly can become “worn out.”
I believe it is best to include problems in a separate document.
Until all of these enhancements exist, I hope you will find this a
suitable and worthwhile compromise.
Thus, you will need my permission to print it. You may obtain that
permission simply by asking: tell me who you are and what you
want it for. Route your requests via email to rzulinsk@mtu.edu, or
by USPS mail to Bob Zulinski, Dept. of Electrical Engineering,
Michigan Technological University, Houghton MI 49931-1295.
Resistors in Series
R1 This is the simple one!!!
Rtotal = R1 + R2 + R3 + (1)
R2
Resistors must carry the same current!!!
Fig. 1.
R’s in series. L’s is series and C’s in parallel have same form.
Resistors in Parallel
R1 R2 Resistors must have the same voltage!!!
Equation takes either of two forms:
Fig. 2.
R’s in parallel. Product Over Sum:
R1 R2
Rtotal = (2)
R1 + R2
Inverse of Inverses:
1
Rtotal =
1 1 1 (3)
+ + +
R1 R2 R3
Real Sources
i
All sources we observe in nature exhibit a
ISC
1/RTH decreasing voltage as they supply increasing
current.
We presume that i-v relationship to be linear,
so we can write the equations:
v
VOC
v
Fig. 5. Typical linear i - v v = VOC − i RTH or i = ISC − (4)
characteristic of a real source. RTH
Review of Linear Circuit Techniques Introduction to Electronics 3
+ Voltage Dividers
RA VA
- Example - finding the voltage across RB :
+ +
VX RB VB RB
- - VB = VX (6)
+ R A + RB + RC
RC VC
-
Resistors must be in series, i.e., they must
Fig. 8. Example of a
voltage divider. carry the same current!!!
IB
Current Dividers
1
IX RA RB RC
RB
IB = I (7)
1 1 1 X
+ +
Fig. 9. Example of a current divider. R A RB RC
Superposition
Superposition applies to any linear circuit - in fact, this is the
definition of a linear circuit!!!
An example of finding a response using superposition:
I IA IB
+ +
- -
Fig. 10. The total Fig. 11. . . . is the sum of Fig. 12. . . . and the
response current I . . . the response IA . . . response IB . . .
A quick exercise:
Use superposition and voltage division to show that VX = 6 V:
10 kΩ 30 kΩ
4V 12 V
VX
Fig. 13. A quick exercise . . .
Review of Linear Circuit Techniques Introduction to Electronics 5
Signal + +
vi (t) Amplifier vo (t) Load
Source - -
Ground
Signal Source
A signal source is anything that provides the signal, e.g., . . .
. . . the carbon microphone in a telephone handset . . .
. . . the fuel-level sensor in an automobile gas tank . . .
Amplifier
An amplifier is a system that provides gain . . .
. . . sometimes voltage gain (illustrated below), sometimes current
gain, always power gain.
vi vo vo
t t t
Fig. 15. Generic input Fig. 16. Output voltage Fig. 17. Output voltage
signal voltage. of noninverting of inverting amplifier.
amplifier.
Basic Amplifier Concepts Introduction to Electronics 7
Signal + +
vi (t) Amplifier vo (t) Load
Source - -
Ground
Load
The load is anything we deliver the amplified signal to, e.g., . . .
. . . loudspeaker . . .
. . . the leg of lamb in a microwave oven . . .
Ground Terminal
Usually there is a ground connection . . .
. . . usually common to input and output . . .
. . . maybe connected to a metal chassis . . .
. . . maybe connected to power-line ground . . .
. . . maybe connected to both . . .
. . . maybe connected to neither . . . use caution!!!
RS ii Ro io
+ + +
vs + vi Ri Avocvi vo RL
- - - -
Signal Source
Our emphasis is voltage . . . source voltage decreases as source
current increases, as with any real source . . .
. . . so we use a Thevenin equivalent.
Amplifier Input
When the source is connected to the amplifier, current flows . . .
. . . the amplifier must have an input resistance, Ri .
Amplifier Output
Output voltage decreases as load current increases . . .
. . . again we use a Thevenin equivalent.
Load
Load current flows . . . the load appears as a resistance, RL .
Voltage Amplifier Model Introduction to Electronics 9
RS ii Ro io
+ + +
vs + vi R i Avocvi vo R L
- - - -
vo
Avoc = (8)
vi RL = ∞
Voltage Gain
With a load in place our concept of voltage gain changes slightly:
vo RL RL
AV = ⇒ vo = Avocv i ⇒ Av = Avoc (9)
vi Ro + RL Ro + RL
We can think of this as the amplifier voltage gain if the source were
ideal:
ii Ro io
+ + +
vi +- vi Ri Avocvi vo R L
- - -
Amplifier Load
Fig. 21. Av = vo /vi illustrated.
Voltage Amplifier Model Introduction to Electronics 10
RS ii Ro io
+ + +
vs + vi R i Avocvi vo R L
- - - -
With our “real” source model we define another useful voltage gain:
vo Ri Ri RL
Avs = ⇒ vi = vs ⇒ Avs = Avoc (10)
vs RS + Ri RS + Ri Ro + RL
Notice that Av and Avs are both less than Avoc , due to loading effects.
Current Gain
We can also define the amplifier current gain:
vo
io RL v o Ri R
Ai = = = = Av i (11)
ii vi v i RL RL
Ri
Power Gain
Because the amplifier input and load are resistances, we have
Po = Vo Io , and Pi = Vi Ii (rms values). Thus:
Po VoIo 2 Ri 2 R
G= = = Av Ai = Av = Ai L (12)
Pi Vi Ii RL Ri
Power Supplies, Power Conservation, and Efficiency Introduction to Electronics 11
IA V AA
+ -
V AA
RS ii Ro io
+ + +
vs + vi Ri A vocv i vo RL
- - - -
DC Input Power
PS = VAAI A + VBBIB (13)
This is sometimes noted as PIN. Use care not to confuse this with
the signal input power Pi .
Conservation of Power
Signal power is delivered to the load ⇒ Po
Power is dissipated within the amplifier as heat ⇒ PD
The total input power must equal the total output power:
PS + Pi = Po + PD (14)
IA V AA
+ -
V AA
RS ii Ro io
+ + +
vs + vi Ri A vocv i vo RL
- - - -
Efficiency
Efficiency is a figure of merit describing amplifier performance:
Po
η= × 100% (15)
PS
Amplifier Cascades Introduction to Electronics 13
Amplifier Cascades
Amplifier stages may be connected together (cascaded) :
+ + + + +
vi1 Ri1 vo1 = vi2 Ri2 vo2
- -A v - -A v -
voc1 i1 voc2 i2
Amplifier 1 Amplifier 2
Fig. 25. A two-amplifier cascade.
Gain of stage 1: v o1
Av 1 = (16)
v i1
Gain of stage 2: v o2 v o2
Av 2 = = (17)
v i 2 v o1
Gain of cascade: v o1 v o 2
Avoc = = Av 1Av 2 (18)
v i 1 v o1
+ + +
vi1 Ri1 vo2
- -A v -
voc i1
Decibel Notation
Power Gain
Recall that G = Po /Pi , and define:
GdB = 10logG (19)
Cascaded Amplifiers
We know that Gtotal = G1 G2 . Thus:
Voltage Gain
To derive the expression for voltage gain in decibels, we begin by
recalling from eq. (12) that G = Av2(Ri /RL ). Thus:
Ri
10 logG = 10 log Av
2
RL
= 10 log Av + 10 log Ri − 10 log RL
2
(21)
Av dB = 20log Av (22)
Only when Ri does equal RL , will the numerical values of GdB and
Av dB be the same. In all other cases they will differ.
From eq. (22) we can see that in an amplifier cascade the product
of voltage gains becomes the sum of voltage gains in decibels.
Current Gain
In a manner similar to the preceding voltage-gain derivation, we can
arrive at a similar definition for current gain:
Ai dB = 20log Ai (23)
Voltage levels:
dBV, decibels with respect to 1 V . . . for example,
3.16 V
3.16 V = 20 log = 10 dBV (24)
1V
Decibel Notation Introduction to Electronics 16
Power levels:
dBm, decibels with respect to 1 mW . . . for example
5 mW
5 mW = 10 log = 6.99 dBm (25)
1 mW
5 mW
5 mW = 10log = −23.0 dbW (26)
1W
RS ii Ro io
+ + +
vs + vi Ri Avocvi vo RL
- - - -
ii io
+ +
is RS vi Ri Ro vo RL
- Aiscii -
io
Aisc = (27)
ii RL = 0
Other Amplifier Models Introduction to Electronics 18
RS ii io
+ +
vs + vi Ri Ro vo RL
- - Gmscvi -
io
Gmsc = (siemens, S) (28)
vi RL = 0
ii Ro io
+ + +
is RS vi Ri Rmocii vo R L
- - -
vo
Rmoc = (ohms, Ω ) (29)
ii RL = ∞
Other Amplifier Models Introduction to Electronics 19
RS ii Ro io
+ + +
vs + vi Ri Avocvi vo R L
- - - -
+ +
vi Avocvi
- -
ii io
+ +
is RS vi Ri Ro vo RL
- Aiscii -
How can we maximize the current that gets delivered to the load ?
● We can get the most current out of the signal source if
Ri << RS , i.e., if the amplifier can “measure” the signal current
with a low input resistance, like an ammeter does.
In fact, if Ri ⇒0 , we won’t have to worry about the value of RS
at all!!!
Amplifier Resistances and Ideal Amplifiers Introduction to Electronics 22
ii Aiscii
+
vi Gmscvi
-
+
ii Rmocii
-
Vo V ∠Vo
Av = = o = A v ∠A v (30)
Vi Vi ∠Vi
Magnitude Response:
A plot of |Av| vs. f is called the magnitude response of the amplifier.
Phase Response:
A plot of ∠ Av vs. f is called the phase response of the amplifier.
Frequency Response:
Taken together the two responses are called the frequency
response . . . though often in common usage the term frequency
response is used to mean only the magnitude response.
Amplifier Gain:
The gain of an amplifier usually refers only to the magnitudes:
A v dB = 20log A v (31)
Frequency Response of Amplifiers Introduction to Electronics 25
|Av|dB
midband region
|Av mid|dB
3 dB
Bandwidth, B
f (log scale)
fH
|Av|dB
midband region
|Av mid|dB
3 dB
Bandwidth, B
f (log scale)
fL fH
+ +
- -
+ +
- -
Differential Amplifiers
1
1 +
vID /2
2 vICM -
+ + - +
vI1 vI2 +
- - vID /2
-
2
Fig. 41. Representing two sources by their differential and
common-mode components.
Note that the differential voltage vID is the difference between the
signals vI1 and vI2 , while the common-mode voltage vICM is the
average of the two (a measure of how they are similar).
+
vicm +
vid /2
- Amplifier vo = Ad vid + Acm vicm
- + +
vid /2 -
-
Fig. 42. Amplifier with differential and common-mode input signals.
Slew Rate
So far we have said nothing about the rate at which vo increases or
decreases . . . this is called the slew rate.
In our ideal op amp, we’ll presume the slew rate is as fast as we
need it to be (i.e., infinitely fast).
Op Amp Circuits - The Inverting Amplifier Introduction to Electronics 31
Let’s put our ideal op amp concepts to work in this basic circuit:
+
vO
0 -
i1 i2
+ R1 R2
vi
Voltage Gain
Because the ideal op amp has Ri = ∞ , the current into the inputs
will be zero.
This means i1 = i2 , i.e., resistors R1 and R2 form a voltage dividerIII
Therefore, we can use superposition to find the voltage v- .
(Remember the quick exercise on p. 4 ??? This is the identical
problem!!!):
v i R2 + v o R1
v− = (35)
R1 + R2
R2 R2
v i R2 + v oR1 = 0 ⇒ vo = − vi ⇒ Av = − (36)
R1 R1
Op Amp Circuits - The Inverting Amplifier Introduction to Electronics 32
+
vO
0 -
i1 i2
+ R1 R2
vi
Input Resistance
This means resistance “seen” by the signal source vi , not the input
resistance of the op amp, which is infinite.
Because v- = 0, the voltage across R1 is vi . Thus:
vi vi vi
i1 = ⇒ Rin = = v = R1 (37)
R1 i1 R
i
1
Output Resistance
This is the Thevenin resistance which would be “seen” by a load
looking back into the circuit (Fig. 45 does not show a load attached).
Our op amp is ideal; its Thevenin output resistance is zero:
RO = 0 (38)
Op Amp Circuits - The Noninverting Amplifier Introduction to Electronics 33
+ +
vi vO
0
-
i1 i2
R1 R2
Fig. 46. Noninverting amplifier circuit.
Voltage Gain
This time our rules of operation and a voltage divider equation lead
to:
R1
vi = v+ = v− = vo (39)
R1 + R2
from which:
R1 + R2 R R2
vo = v i = 1 + 2 v i ⇒ Av = 1 + (40)
R1 R1 R1
+
+
vi vo
-
Voltage Gain
This one is easy:
vi = v+ = v − = vo ⇒ Av = 1 (43)
+
vO
iA
-
+ RA iF
vA iB
+ + -
RB RF
vB
Voltage Gain
We could use the superposition approach as we did for the
standard inverter, but with three sources the equations become
unnecessarily complicated . . . so let’s try this instead . . .
Recall . . . vO takes on the value that causes v- = v+ = 0 . . .
So the voltage across RA is vA and the voltage across RB is vB :
vA vB
iA = and iB = (45)
RA RB
v v
iF = i A + iB and v RF = RF (i A + i B ) = RF A + B (46)
R A RB
R R
v O = − F v A + F v B (47)
RA RB
Op Amp Circuits - Another Inverting Amplifier Introduction to Electronics 36
+
vO
-
i1 R2 R4
+ R1
vi i2 R3
Voltage Gain
One common approach to a solution begins with a KCL equation at
the R2 - R3 - R4 junction . . .
. . . we’ll use the superposition & voltage divider approach, after we
apply some network reduction techniques.
Notice that R3 , R4 and the op amp output voltage source can be
replaced with a Thevenin equivalent:
R4 RTH
+ +
R3 vO vTH
R1 REQ = R2 + RTH
vi vTH
v- = 0
Fig. 51. Equivalent circuit to original amplifier.
R3 R + (R3 || R4 ) R R || R
vO = − 2 v i = − 2 + 3 4 v i (50)
R3 + R 4 R1 R1 R1
vO R R R || R
Av = = −1 + 4 2 + 3 4 (51)
vi R3 R1 R1
Op Amp Circuits - The Differential Amplifier Introduction to Electronics 38
R1 Voltage Gain
Again, vO takes on the value
+ required to make v+ = v- .
v2 R2 +
vO Thus:
- R2
i1 i2 v+ = v2 = v− (52)
R1 + R2
+ + -
v1 R1 R2
We can now find the current
i1 , which must equal the
Fig. 52. The differential amplifier.
current i2 :
v1 − v − v1 R2
i1 = = − v 2 = i2 (53)
R1 R1 R1(R1 + R2 )
R2 R2R2
v R = i 2R2 = v1 − v
R1(R1 + R2 ) 2
(54)
2
R1
R2 R R2R2
vO = v + − v R = v 2 − 2 v1 + v
R1(R1 + R2 ) 2
(55)
2
R1 + R2 R1
Op Amp Circuits - The Differential Amplifier Introduction to Electronics 39
R2 R 2R 2 R1R2 R2R2
v2 + v2 = v2 + v2
R1(R1 + R2 ) R1(R1 + R2 ) R1(R1 + R2 )
(56)
R1 + R2
R1R2 + R2R2 R (R + R2 ) R
= v2 = 2 1 v2 = 2 v2 (57)
R1(R1 + R2 ) R1(R1 + R2 ) R1
R2 R R
vO = − v 1 + 2 v 2 = 2 (v 2 − v 1) (58)
R1 R1 R1
So, under the conditions that we can have identical resistors (and
an ideal op amp) we truly have a differential amplifier!!!
Op Amp Circuits - Integrators and Differentiators Introduction to Electronics 40
The Integrator
+
From our rules and previous
vO experience we know that v- = 0
-
and iR = iC , so . . .
iR iC
vi
+ + - iR = = iC (59)
vi R C R
From the i-v relationship of a
Fig. 53. Op amp integrator. capacitor:
t t
1 1
v C = ∫ iC dt = ∫ iC dt + v C (0) (60)
C −∞ C0
Normally vC (0) = 0 (but not always). Thus the output is the integral
of vi , inverted, and scaled by 1/RC.
Op Amp Circuits - Integrators and Differentiators Introduction to Electronics 41
The Differentiator
+
vO This analysis proceeds in the
-
same fashion as the previous
iC iR analysis.
+ + -
vi C R
From our rules and previous
experience we know that v- = 0
Fig. 54. The op amp differentiator. and iC = iR . . .
dv C dv
iC = C = C i = iR (62)
dt dt
Recognizing that vO = -vR :
dv i
v O = −v R = −i R R = −RC (63)
dt
Op Amp Circuits - Designing with Real Op Amps Introduction to Electronics 42
Resistor Values
Our ideal op amp can supply unlimited current; real ones can’t . . .
+ To limit iF + iL to a reasonable
+
vi iL
value, we adopt the “rule of
iF
- thumb” that resistances should
+
RL vO be greater than approx. 100 Ω.
-
R1 R2
Of course this is highly
Fig. 55. Noninverting amplifier with load. dependent of the type of op amp
to be used in a design.
Larger resistances render circuits more susceptible to noise and
more susceptible to environmental factors.
To limit these problems we adopt the “rule of thumb” that
resistances should be less than approximately 1 MΩ.
Let’s re-visit some 7th-grade algebra . . .we can find the solution of
two simultaneous equations by plotting them on the same set of
axes.
Here’s a trivial example:
y =x and y =4 (64)
0, for x < 0
y = (65)
0.4x , for x ≥ 0
2
and
4x
y =8− (66)
5
and
4x
y =8− (68)
5
Diodes
free free
”holes” electrons
Anode Cathode
+ + + + - - -
p-type n-type
+ + + - - - -
iD
+ -
vD
Fig. 60. Simplified physical construction and schematic symbol of
a diode.
Fig. 61. PSpice-generated i-v characteristic for a 1N750 diode showing the various regions of
operation.
i=iD
. . . where VOC and ISC are the open-
ISC circuit voltage and the short-circuit
current, respectively.
1/R TH
A plot of this line is called the load
line, and the graphical procedure is
v=v D
V OC called load-line analysis.
Fig. 64. Graphical solution.
Graphical Analysis of Diode Circuits Introduction to Electronics 49
R
iD
Case 1: VS = 2.5 V and R = 125 Ω
+ +
VS vD Case 2: VS = 1 V and R = 25 Ω
-
-
Case 3: VS = 10 V and R = 1 kΩ
Fig. 65. Example circuit
(Fig. 62 repeated).
Case 3: VOC = VS = 10 V
ISC = 10 V / 1 kΩ = 10 mA
VOC not on scale, use slope:
1
1 kΩ = 1mA
V = 2.5 V
2.5 mA
Diode Models
v
iD = IS exp D − 1 (73)
nVT
i
v D = nVT ln D + 1 (74)
IS
v
iD ≈ IS exp D (75)
nVT
i D ≈ −IS (76)
At High Currents:
i
v D = nVT ln D + 1 + i DRS (77)
IS
4 kΩ iD + vD - 7 kΩ We need first to
assume a diode state,
+ +
10 V 6 kΩ 3 kΩ 10 V
i.e., ON or OFF.
- -
We’ll arbitrarily choose
Fig. 68.Circuit for an ideal diode example.
OFF.
4 kΩ 7 kΩ
+ vD -
+ + If OFF, iD = 0, i.e., the
10 V 6 kΩ 3 kΩ 10 V diode is an open circuit.
- -
iD
+ -
vD
3. If all OFF diodes have vD < 0, and all ON diodes have iD > 0,
the initial assumption was correct. If not make new
assumption and repeat.
Diode Models Introduction to Electronics 55
v = VX + iR X (78)
1/RX
v
VX The same equation is provided
by the following circuit:
-V X /RX
VX RX i
- +
Fig. 74. A piecewise-linear segment. - v +
Fig. 75. Circuit producing eq. (?).
iD
1/RF
VZ
vD
1/RZ VF
iD
+ - Our ideal diode model is a
special case . . .
fwd bias (ON) . . . it has VF = 0, RF = 0 in the
vD forward bias region . . .
. . . it doesn’t have a
rev bias (OFF) breakdown region.
Fig. 79. Ideal diode i-v characteristic.
(Fig. 67 repeated)
Introduction
This application uses diodes in the breakdown region . . .
For VZ < 6 V the physical breakdown phenomenon is called zener
breakdown (high electric field). It has a negative temperature
coefficient.
For VZ > 6 V the mechanism is called avalanche breakdown (high
kinetic energy). It has a positive temperature coefficient.
For VZ ≈ 6 V the breakdown voltage has nearly zero temperature
coefficient, and a nearly vertical i-v char. in breakdown region, i.e.,
a very small RZ .
RTH = 500 Ω
Note that vOUT = -vD . Fig. 83
- + below shows the graphical
+ vD
VTH vOUT construction.
+
7.5 V to 10 V - Because the zener is upside-down
iD -
the Thevenin equivalent load line
Fig. 82. Thevenin equivalent source with
unpredictable voltage and zener diode.
is in the 3rd quadrant of the diode
(Fig. 81 repeated) characteristic.
As VTH varies from 7.5 V to 10 V, the load line moves from its blue
position, to its green position.
As long as the zener remains in breakdown, vOUT remains nearly
constant, at ≈ 4.7 V.
As long as the minimum VTH is somewhat greater than VZ (in this
case VZ = 4.7 V) the zener remains in the breakdown region.
If we’re willing to give up some output voltage magnitude, in return
we get a very constant output voltage.
RTH = 500 Ω
+
+ 8Ω
VTH vOUT
+
7.5 V to 10 V - 4.6 V
- -
Fig. 85. Regulator circuit of Fig. 81 with piecewise-
linear model replacing the diode.
The Zener Diode Voltage Regulator Introduction to Electronics 62
RTH = 500 Ω
+
+ 8Ω
VTH vOUT
+
7.5 V to 10 V - 4.6 V
- -
Fig. 86. Regulator with diode model
(Fig. 85 repeated).
Circuit Analysis:
The 500 Ω and 8 Ω resistors are in series, forming a voltage divider.
For VTH = 7.5 V:
8Ω
V8 Ω = (7.5 V − 4.6 V) = 45.67 mV (81)
500 Ω + 8 Ω
For VTH = 10 V:
8Ω
V8 Ω = (10 V − 4.6 V) = 85.04 V (83)
500 Ω + 8 Ω
Thus, for a 2.5 V change in the line voltage, the output voltage
change is only 39.4 mV !!!
The Zener Diode Voltage Regulator Introduction to Electronics 63
RS
- +
+
vD vOUT
VSS RL
- +
iD -
Fig. 87. Zener regulator with load.
RS RTH
+ - + -
+ +
vOUT vD vOUT vD
VSS RL VTH
- + - +
- iD - iD
Fig. 88. Regulator drawn with zener and Fig. 89. Regulator of Fig. 87 with VSS , RS ,
load in reversed positions. and RL replaced by Thevenin eq.
Different loads will result in different values for VTH and RTH , but the
analysis procedure remains the same!!!
The Zener Diode Voltage Regulator Introduction to Electronics 64
RS = 500 Ω
- +
+
vD vOUT
VSS 10 V RL
- +
iD -
Fig. 90. Example of loaded zener regulator for
graphical analysis.
(a) 10 kΩ
VOC = VTH = 10 V = 9.52 V (85)
10 kΩ + 500 Ω
VSS 10 V
ISC = = = 20 mA (86)
RS 500 Ω
(b) 1 kΩ
VOC = VTH = 10 V = 6.67 V (87)
1kΩ + 500 Ω
VSS 10 V
ISC = = = 20 mA (88)
RS 500 Ω
The Zener Diode Voltage Regulator Introduction to Electronics 65
(c) 100 Ω
VOC = VTH = 10 V = 167
. V (89)
100 Ω + 500 Ω
VSS 10 V
ISC = = = 20 mA (90)
RS 500 Ω
The three load lines are plotted on the zener characteristic below:
Fig. 91. Load line analysis for the loaded zener regulator.
Introduction
+ vD -
This diode application changes
ac into dc. The voltage source is
+ + most often a sinusoid (but can be
vS Vm sin ωt RL vO anything).
- - We’ll assume the diode is ideal
for our analysis.
Fig. 92. The half-wave rectifier circuit.
t
. . . vD = vS
T
Fig. 94. Output voltage waveform.
vD
Peak Inverse Voltage, PIV:
Another term for breakdown
T t voltage rating . . .
-Vm
. . . in this circuit, the diode
Fig. 95. Diode voltage waveform. PIV rating must be > Vm .
The Half-Wave Rectifier Introduction to Electronics 67
Rtotal D
+ +
110 Vrms Vm sin ωt VBATTERY
- -
A
Fig. 96. A circuit typical of most battery chargers.
vS
Vm Charging
current
VBATT
t
T
-Vm
Fig. 97. Battery charger waveforms.
Here vS represents the transformer secondary voltage, and VBATT
represents the battery voltage.
The Half-Wave Rectifier Introduction to Electronics 68
iD (t) iL (t)
Analysis of this circuit
+ with a nonlinear element
+
vS (t) is very difficult . . .
C RL vL (t)
- - . . . so we will use the
ideal diode model.
Fig. 98. Filtered half-wave rectifier.
vL(t)
Ripple voltage, Vr
Vm
t
on diode off on diode off on
T T
vL(t)
Ripple voltage, Vr
Vm
t
on diode off on diode off on
T T
vL(t)
Ripple voltage, Vr
Vm
t
on diode off on diode off on
T T
Because all of the charge supplied to the load must come from the
source only when the diode is ON, iD PEAK can be very large, as
illustrated below..
vL(t)
Ripple voltage, Vr
Vm
t
on diode off on diode off on
T T
i(t)
iD PEAK iD(t)
iL(t)
t
on diode off on diode off on
T T
Vm Vm
t t
Fig. 106. Full-wave load voltage.
-Vm
vA (t)
+
vS (t) DA iL (t)
vin (t) -
+
vS (t) DB +
- RL vL (t)
vB (t) -
Fig. 107. The full-wave rectifier (Fig. 104 repeated).
Thus the diode PIV rating must be 2Vm . Diode voltage waveforms
are shown below . . .
vA vB
t t
-2Vm -2Vm
Fig. 108. Voltage across diode DA . Fig. 109. Voltage across diode DB .
The Bridge Rectifier Introduction to Electronics 74
D4 D1
+ iL (t)
vin (t) vS (t)
- +
D3 D2 vL (t)
-
Fig. 110. The bridge rectifier.
vS Operation
Vm 1st (Positive) Half-Cycle:
t
Current flows from top end of vS ,
-Vm through D1 and RL , then via
ground through D3 , and back to
Fig. 111. Input voltage to diode bridge. vS .
vL
Vm
2nd (Negative) Half-Cycle:
t Current flows from bottom end
Fig. 112. Full-wave load voltage. of vS , through D2 and RL , then
v 1, v 3 via ground through D4 , and back
t
to vS .
-Vm
Peak Inverse Voltage:
Fig. 113. Diode voltage for D1 and D3 .
v 2, v 4
In each half-cycle the OFF
diodes are directly across vS ,
t
thus the diode PIV is Vm .
-Vm
Fig. 114. Diode voltage for D2 and D4 .
Full-Wave/Bridge Rectifier Features Introduction to Electronics 75
Bridge Rectifier
Much cheaper transformer more than offsets the negligible cost of
two more diodes.
Full-Wave Rectifier
Archaic since vacuum tube rectifiers have largely been replaced by
semiconductor rectifiers.
Preferable only at low voltages (one less diode forward-voltage
drop), if at all.
Vm Vm
Vr C = ⇒ C= (94)
2fRL 2Vr fRL
Introduction
The BJT is a nonlinear, 3-terminal device based on the junction
diode. A representative structure sandwiches one semiconductor
type between layers of the opposite type. We first examine the npn
BJT:
We’re most interested in the active region, but will have to deal with
cutoff and saturation, as well.
Discussion of inverse region operation is left for another time.
Bipolar Junction Transistors (BJTs) Introduction to Electronics 77
C
● The relative current magnitudes are
n indicated by the arrow thicknesses in the
figure.
B p ● Because iB is so small, a small change in
base current can cause a large change in
collector current - this is how we get this
n device to amplify!!!
E
Fig. 116. Active-region
BJT currents.
Bipolar Junction Transistors (BJTs) Introduction to Electronics 78
v
iC = αi E = αIES exp BE − 1 (98)
VT
v
iC ≈ IS exp BE (99)
VT
i E = iC + i B ⇒ i E = αi E + i B ⇒ i B = (1 − α )i E (100)
thus iC αi E α
= = =β (101)
iB (1 − α )iE 1 − α
iC = β i B (103)
Introduction
iC We use the term common-emitter
characteristics because the emitter is
iB common to both voltage sources.
+ +
vCE The figure at left represents only how we
+ v+
BE
- -
- might envision measuring these
-
characteristics. In practice we would
Fig. 118.Circuit for measuring
never connect sources to any device
BJT characteristics. without current-limiting resistors in
series!!!
Input Characteristic
First, we measure the iB - vBE relationship (with vCE fixed). Not
surprisingly, we see a typical diode curve:
Output Characteristics
iC
iB + +
vCE
+ v+
BE
- -
- -
Active Region:
Recall that the active region requires that the EBJ be forward-
biased, and that the CBJ be reverse-biased.
A forward-biased EBJ means that vBE ≈ 0.7 V. Thus, the CBJ will
be reverse-biased as long as vCE > 0.7 V.
Note that iC and iB are related by the ratio β, as long as the BJT is
in the active region.
Cutoff:
The EBJ is not forward-biased (sufficiently) if iB = 0. Thus the cutoff
region is the particular curve for iB = 0 (i.e., the horizontal axis).
Saturation:
When the EBJ is forward-biased, vBE ≈ 0.7 V. Then, the CBJ is
reverse-biased for any vCE > 0.7 V. Thus, the saturation region lies
to the left of vCE = 0.7 V.
Note that the CBJ must become forward-biased by 0.4 V to 0.5 V
before the iC = βiB relationship disappears, just as a diode must be
forward-biased by 0.4 V to 0.5 V before appreciable forwardcurrent
flows.
The pnp BJT Introduction to Electronics 83
In general,
v
i E = i B + iC and iE = IES exp EB − 1 (104)
VT
v
iC = α i E , i C = βi B and iC ≈ IS exp EB (105)
VT
where, the latter equation is the approximation for a forward-biased
EBJ.
The pnp BJT Introduction to Electronics 84
Because the voltage and current references are reversed, the input
and output characteristics appear the same also:
Description of Operation
The p-n junction is a
Drain typical diode . . .
D
iD Holes move from p-type
iG = 0 + into n-type . . .
n-type p G vDS
Gate p
channel +v
GS - Electrons move from n-
-
iD type into p-type . . .
S
Source
Region near the p-n
junction is left without
Fig. 127. The n-channel JFET any available carriers -
representative physical structure (left) and schematic depletion region
symbol (right).
+
pulls holes away from junction,
vGS < 0
-
And positive voltage at the Source
Source pulls electrons away from junction.
Fig. 129. Thus, the channel becomes narrower,
Depletion region for negative and the channel resistance increases.
vGS (reverse bias).
Cutoff Region:
The FET is in cutoff for vGS ≤ VP , and for any vDS :
iD = 0 (106)
Triode Region:
The FET is in the triode region for 0 > vGS > VP , and vGD > VP :
[
i D = K 2(v GS − VP )v DS − v DS 2 ] (107)
i D = K (v GS − VP )
2
(110)
iD
v DS = ⇒ i D = Kv DS
2
(113)
K
i D = K (v GS − VP )
2
(114)
D
S G D
metal SiO 2
n channel n G B
p-type substrate (body)
B
S
D
S G D
metal SiO 2
n n G B
p-type substrate (body)
B
S
iD
● The n-channel JFET can only have
negative gate voltages . . .
p-n junction must remain reversed
biased . . .
IDSS
Actual device can operate with vGS
vGS
VP
slightly positive, approx. 0.5 V max.
i D = K (v GS − VP )
Fig. 139. Transfer char., 2
(116)
n-channel JFET.
iD
● The n-channel depletion MOSFET
can have either negative or positive
gate voltages . . .
Gate current prevented by oxide
IDSS
insulating layer in either case.
vGS
i D = K (v GS − VP )
2
VP (117)
iD
● The n-channel enhancement
MOSFET can have only positive
gate voltages . . .
Gate current prevented by oxide
insulating layer . . .
vGS
VTH
Only the notation changes in the
equation:
Fig. 141. Transfer char., n-
i D = K (v GS − VTH )
channel enhancement MOSFET. 2
(118)
Comparison of n-Channel FETs Introduction to Electronics 95
D D D
iD iD iD
iG = 0 + iG = 0 iG = 0
G vDS G B G B
+v +v +v
GS - GS GS
- - -
iD
S S S
n-ch. JFET
n-ch. depl. MOSFET
VTH VP
p-ch. enh. MOSFET
p-ch. JFET
p-ch. depl. MOSFET
But more often you’ll see negative signs used to labels axes, or
values along the axes, such as these examples:
Fig. 147. Typical p-channel transfer Fig. 148. Typical p-channel transfer
characteristic. characteristic.
p-Channel JFETs and MOSFETs Introduction to Electronics 98
Fig. 149. Typical p-channel output Fig. 150. Typical p-channel output
characteristic. characteristic.
Triode Region:
(for vGS < VP , and vGD < VP )
[
i D = K 2(v GS − VP )v DS − v DS 2 ] (120)
Pinch-Off Region:
(for vGS < VP , and vGD > VP )
i D = K (v GS − VP )
2
(121)
Other FET Considerations Introduction to Electronics 99
VBB /RB
iB max
IBQ Q
iB min
vBE
VBB -vin max VBB VBB +vin max
iB
VBB /R B
iB max
IBQ Q
iB min
vBE
VBB -vin max VBB VBB +vin max
● Thus, as vin varies through its cycle, base current varies from
iB max to iB min .
The base-emitter voltage varies also, from vBE max to vBE min ,
though we are less interested in vBE at the moment.
Basic BJT Amplifier Structure Introduction to Electronics 102
A Numerical Example
Let’s look at a PSpice simulation of realistic circuit:
RC = 1 kΩ
iC
RB = 10 kΩ + +
+ + vCE VCC = 10 V
iB vBE - -
vin = 0.1 sin ωt V - Q1
+ 2N2222
VBB = 1 V
-
Fig. 161. 2N2222 output characteristics, with curves for base currents of (from
bottom to top) 4 µA, 13 µA, 22 µA, 31 µA, 40 µA, and 49 µA.
∆v CE 2.95 V - 6.11V
Av = = = −15.8 !!! (124)
∆v in 0.2 V
Basic BJT Amplifier Structure Introduction to Electronics 106
Fig. 163. Output (collector) waveform for the circuit of Fig. 159.
Basic FET Amplifier Structure Introduction to Electronics 107
The basic FET amplifier takes the same form as the BJT amplifier.
Let’s go right to a PSpice simulation example using a 2N3819 n-
channel JFET:
RD = 1 kΩ
iD
+ +
+ vDS VDD = 15 V
+ -
vin = 0.5 sin ωt V vGS -
- J1
+ 2N3819
VBB = -1 V
-
while KVL around the drain-source loop gives the familiar result:
VDD = i DRD + v DS (126)
Fig. 165. PSpice-generated 2N3819 transfer characteristic showing the bias line,
and lines for vGS min and vGS max .
VGSQ = −10
. V ⇒ IDQ = 5.30 mA (128)
v GS max
= −0.5 V ⇒ iD max
= 8.22 mA (129)
Fig. 166. 2N3819 output characteristics, with curves for gate-source voltages of
(from bottom to top) -3 V, -2.5 V, -2 V, -1.5 V, -1 V, -0.5 V, and 0 V.
From the output characteristics and the drain-source load line, the
indicated gate-source voltages correspond to the following drain-source
voltage values:
v GS min
= −15
. V ⇒ v DSmax
= 12.0 V (130)
VGSQ = −10
. V ⇒ VDSQ = 9.70 V (131)
v GSmax
= −0.5 V ⇒ v DS min
= 6.78 V (132)
Amplifier Distortion
Fig. 167. Output (drain) waveform for the FET amplifier example.
RD = 1.3 kΩ
iD
+ +
+ vDS VDD = 15 V
+ -
vin = 1.5 sin ωt V vGS -
- J1
+ 2N3819
VBB = -1.5 V
-
Fig. 169. Severely distorted output waveform resulting from operation in the
cutoff region (top) and the triode region (bottom).
Biasing and Bias Stability Introduction to Electronics 112
VCC Example
We let VCC = 15 V,
RB RC iC
RB = 200 kΩ, and RC = 1 kΩ
For β = 100:
VCC − VBE 15 V - 0.7 V
IB = = . µA
= 715 (134)
RB 200 kΩ
For β = 300:
VCC − VBE 15 V - 0.7 V
IB = = . µA
= 715 (136)
RB 200 k Ω
IC = βIB = 215
. mA ⇒ VCE = VCC − IC RC = −6.45 V (137)
Thus our calculations for β = 300 are incorrect, but more importantly
we conclude that fixed bias provides extremely poor bias stability!!!
Biasing BJTs - The Constant Base Bias Circuit Introduction to Electronics 114
For β = 100:
VBB − VBE β
IE = = 215
. mA ⇒ IC = IE = 213
. mA (138)
RE β +1
For β = 300:
VBB − VBE β
IE = = 215
. mA ⇒ IC = IE = 214
. mA (140)
RE β +1
Introduction
This combines features of fixed bias and constant base bias, but it
takes a circuit-analysis “trick” to see that:
VCC
R1 RC R1 RC
+ +
VCC VCC
- -
R2 RE
R2 RE
RC
RB +
VCC
+ -
VBB
- RE
Circuit Analysis
RC
RB +
VCC
+ -
VBB
- RE
β (VBB − VBE )
βIB = IC = (145)
RB + (β +1)RE
We complete the analysis with KVL around c-e loop:
VCE = VCC − IC RC − IE RE (146)
Biasing BJTs - The Four-Resistor Bias Circuit Introduction to Electronics 117
Bias Stability
Bias stability can be illustrated with eq. (145), repeated below:
β (VBB − VBE )
βIB = IC = (147)
RB + (β +1)RE
1
Rule of Thumb: let VRC ≈ VCE ≈ VRE ≈ VCC
3
Example
15 V
R1 RC RC
10 kΩ 1 kΩ 1 kΩ
R B = 3.3 kΩ +
15 V
+ -
R2 5 kΩ RE 5 V
1 kΩ - RE 1 kΩ
IC
⇒ IE = = 416
. mA ⇒ VCE = VCC − IC RC − IE RE = 6.72 V (149)
α
For β = 300:
VBB − VBE
IB = . µA
= 141 ⇒ IC = βIB = 4.24 mA
RB + (β + 1)RE
(150)
IC
⇒ IE = = 4.25 mA ⇒ VCE = VCC − IC RC − IE RE = 6.50 V (151)
α
Finally, note the complete lack of bias stability. Fixed bias is not
practical!!!
Biasing FETs - The Self Bias Circuit Introduction to Electronics 120
iD
Note the improvement in bias
High-current device
stability over a fixed bias approach.
V DD V DD
RD
R1 RD iD
RG +
v DS
-
+
VG RS
R2 RS
-
Fig. 182. Fixed + self-bias Fig. 183. Equivalent circuit after using
circuit for FETs. Thevenin’s Theorem on gate divider.
i D = K (v GS − VP )
2
(155)
iD
High-current device
Bias line
vGS = VG - RS iD
IDQ
Low-current device IDQ
vGS
VG
Intercept at
V G / RS
iC
VCC
RC + RE
PMAX = iC vCE
Q-point area
VCC vCE
Design Procedure
● First, we decide how VCC divides among VR , VCE , VE . For C
● Choose VCEQ . Here a rule of thumb is: VCEQ ≈ VCC /2. Then:
RC =
[
VCC − VCEQ − −(VB + VBEQ ) ]=V CC − VCEQ + VB + VBEQ (161)
ICQ ICQ
β VCC − 1 (VEE + VBEQ )
R
-VEE
R2
≈ (162)
Fig. 188. Grounded-emitter ICQ
bias circuit. R1 + βRC
Design Procedure
● Allocate VCC between VRc and VCEQ . With supply voltage split
between only two elements the rule of thumb becomes:
VCEQ ≈ VCC / 2 (163)
β VCC − 1 (VEE + VBEQ )
RC
R
i1 R2
≈ (166)
ICQ
R1 iC R1 + βRC
iB
A. We begin by noting that :
R2 i2
I1 = I2 + IB (167)
and
-VEE
Fig. 189. Grounded-emitter IRC = I1 + IC = I2 + (β + 1)IB (168)
bias circuit (Fig. 188 repeated).
[
VCC = VBEQ + (I2 + IB )R1 + I2 + (β + 1)IB RC ] (170)
VCC = VBEQ +
R1
R2
(VEE + VBEQ ) + IBR1 + C (VEE + VBEQ ) + (β + 1)IBRC
R
R2
(171)
Design of Discrete BJT Bias Circuits Introduction to Electronics 128
VCC = VBEQ +
R1
R2
(VEE + VBEQ ) + IBR1 + C (VEE + VBEQ ) + (β + 1)IBRC
R
R2
(172)
VCC − VBEQ −
R1
R2
( R
R2
[
VEE + VBEQ ) − C (VEE + VBEQ ) = IB R1 + (β + 1)RC ] (173)
Finally, if we apply the following approximations:
VCC - VBEQ ≈ VCC RC /R2 ≈ 0 β + 1≈ β
β VCC − 1 (VEE + VBEQ )
R
R2
= (174)
ICQ
R1 + βRC
Bipolar IC Bias Circuits Introduction to Electronics 129
Introduction
Integrated circuits present special problems that must be
considered before circuit designs are undertaken.
For our purposes here, the most important consideration is real
estate. Space on an IC wafer is at a premium. Anything that takes
up too much space is a liability. Consider the following:
● Resistors are very inefficient when it comes to real estate.
The area required is directly proportional to the value of
resistance (remember R = ρL / A ?).
As a result, use of resistances in ICs is avoided, if possible.
And resistances greater than 100 kΩ are extremely rare.
When used, it is quite difficult to control resistance values with
accuracy unless each resistor is laser-trimmed. Tolerances
are as large as 50% are not unusual.
Because all resistors are fabricated at the same time, all
resistors are “off” by the same amount. This means that
resistors that are intended to be equal will essentially be equal.
● Capacitors are also liabilities. Capacitance values greater
than 100 pF are virtually unheard of.
● Inductors only recently became integrable. Their use is quite
limited.
● BJTs are very efficient. And while β values suffer the same
3:1 to 5:1 variation found in discrete transistors, all BJTs on an
IC wafer are essentially identical (if intended to be).
This latter point is most important, and drives all IC circuit design.
We begin to examine this on the following pages.
Bipolar IC Bias Circuits Introduction to Electronics 130
Current Ratio:
VCC VCC This is the most simple of all IC bias
circuit techniques.
IREF
Load The key here is that the BJTs are
identical !!! Because VBE1 = VBE2 , this
RREF IO = IC2 means that IB1 = IB2 = IB .
Note that VCB1 = 0, thus Q1 is active
IC1 (at the edge of saturation).
Q1 Q2 If we assume Q2 is also active, we
IB1 IB2 have IC1 = IC2 = IC .
Fig. 190. Diode-biased current mirror. From this point the analysis proceeds
straightforwardly . . .
IO β IB β 1
= = =
IREF (β + 2)IB β + 2 1 + 2 (177)
β
Thus, as long as Q2 remains active, for large β, IO ≈ IREF , i.e., IO
reflects the current IREF (hence “mirror”), regardless of the load!!!
Bipolar IC Bias Circuits Introduction to Electronics 131
VCC VCC
Reference Current:
IREF IREF is set easily, by choosing RREF :
Load
RREF IO = IC2 VCC − VBE VCC − 0.7 V
IREF = ≈ (178)
RREF RREF
IC1
Output Resistance:
Q1 Q2
IB1 IB2 Finally, the output resistance seen by
Fig. 191. Diode-biased current mirror
the load is just the output resistance
(Fig. 190 repeated. of Q2 :
−1
∂i
ro = C 2 (179)
∂v CE 2
Bipolar IC Bias Circuits Introduction to Electronics 132
IC2
Compliance Range
ro = 1/slope
This is defined as the range of
voltages over which the mirror
Compliance Range
circuit functions as intended.
For the diode-biased mirror, this
VCE2 is the range where Q2 remains
0.5 V BV
active.
Fig. 193. Example of the compliance range of a
current mirror. The diode-biased mirror is
represented in this figure.
VCC
Amplifier
IDC
Current
Mirror -VEE
Fig. 195. Representation
-VEE
of the mirror circuit of
Fig. 194. Follower
Fig. 194.
biased with a current
nirror.
V CC V CC Current Ratio:
The addition of another transistor
creates a mirror with an output
IREF Load
resistance of ≈ βro2 (very large!!!)
R REF IO = IC2 Because VBE1 = VBE3 we know that
IB1 = IB3 = IB .
Because VCB3 = 0, Q3 is active.
Q2
Because VCB1 = VBE2 , Q1 is active.
Q1 Q3 Thus we know that IC1 = IC3 = βIB .
We assume also that Q2 is active.
Fig. 196. Wilson current mirror.
β β (β + 2)
IO = IC 2 = IE 2 = IB (181)
β +1 β +1
1 β +2
IB 2 = IE 2 = IB (182)
β +1 β +1
β +2
IREF = IC1 + IB 2 = βIB + IB (183)
β +1
Bipolar IC Bias Circuits Introduction to Electronics 134
β (β + 2) β (β + 2)
IB
IO β +1 β +1 β (β + 2)
= = = (184)
IREF β +2 β (β + 1) β + 2 β (β + 1) + (β + 2)
β IB + IB +
β +1 β +1 β +1
IO β 2 + 2β 1 1
= 2 = ≈ ≈1
IREF β + 2β + 2 1 + 2
1+ 2
2 (185)
β + 2β
2
β
Thus the Wilson mirror ratio is much closer to unity than the ratio of
the simple diode-biased mirror.
Reference Current:
The reference current can be found by summing voltages rises from
ground to VCC :
VCC − VBE 2 − VBE 3 VCC − 14
. V
IREF = ≈ (186)
RREF RREF
Output Resistance:
The output resistance of the Wilson can be shown to be βro2 .
However, the derivation of the output resistance is a sizable
endeavor and will not be undertaken here.
Bipolar IC Bias Circuits Introduction to Electronics 135
v i
iC = IS exp BE and v BE = VT ln C (187)
VT IS
Thus we may write:
i i
VBE 1 = VT ln C1 and VBE 2 = VT ln C 2 (188)
IS IS
Note that VT and IS are the same for both transistors because they
are identical (and assumed to be at the same temperature).
Bipolar IC Bias Circuits Introduction to Electronics 136
VCC VCC
Continuing with the derivation from the
previous page . . .
Load
R1 From a KVL equation around the base-
emitter loop:
IC1 IO = IC2
VBE 1 = VBE 2 + R2IE 2 ≈ VBE 2 + R2IC 2 (189)
Q1 Q2
V+
BE1 V+
BE2
- - Rearranging:
R2
Substituting the base-emitter voltages from eq. (188) into eq. (190):
I I I
VT ln C1 − VT ln C 2 ≈ R2IC 2 ⇒ VT ln C1 ≈ R2IC 2 (191)
IS IS IC 2
VT IC1 VT IC1
Analysis: ln = IC 2 Design: R2 = ln (192)
R2 IC 2 IC 2 IC 2
where:
VCC − VBE 1
IC1 ≈ IREF = (193)
R1
Bipolar IC Bias Circuits Introduction to Electronics 137
VCC
Load 1 Load 2
-VEE -VEE
IREF
VCC VCC
Load 3 Load 4
-VEE
Fig. 199. Multiple current mirrors.
iD iD
vs
+
vD
+ -
VDC Q
IDQ
Fig. 200. Generalized diode circuit.
vD
VDQ
Fig. 201. Diode characteristic.
The Concept
First, we allow vs to be zero. The circuit is now dc only, and has a
specific Q-point shown.
We can find the Q-point analytically with the Shockley equation, or
with a diode model such as the ideal, constant-voltage-drop, or
piecewise-linear model.
The Equations
This straight-line approximation allows us to write a linear equation
relating the changes in diode current (around the Q-pt.) to the
changes in diode voltage:
∆i D = K ∆v D (194)
Diode Small-Signal Equivalent Circuit Introduction to Electronics 140
Q
IDQ
vD
VDQ
Fig. 202. Diode curve with tangent at
Q-point.
1 ∂i D
= (197)
rd ∂v D Q − po int
v v
iD = IS exp D − 1 ≈ IS exp D (198)
nVT nVT
Thus:
∂ vD IS VDQ
S
I exp = exp (199)
∂v D nVT Q − po int nV T nVT
Notes:
1. The calculation of rd is easy, once we know IDQ !!!
2. IDQ can be estimated with simple diode models !!!
3. Diode small-signal resistance rd varies with Q-point.
4. The diode small-signal model is simply a resistor !!!
Notation Introduction to Electronics 142
Notation
iD
IDQ
id
iD
t
Fig. 203. Illustration of various currents.
iB
iC
vs ib
IBQ
iB
+ iB iE
VDC
t
Fig. 204. Generalized BJT circuit. Fig. 205. Generalized base current waveform.
Q VT
IBQ where rπ ≈ (203)
IBQ
vBE
~0.7 V
ib ic
B C
+
vbe rπ β ib
-
ie
E
Fig. 207. BJT small-signal equivalent circuit.
Introduction
VCC
R1 RC
Cout
RS Cin
+ Q1
+
vs +
- vin
CE RL vo
R2 RE
- -
Fig. 208. Standard common emitter amplifier circuit.
VCC
R1 RC
Cout
RS Cin
+ Q1
+
vs +
- vin
CE RL vo
R2 RE
- -
Fig. 209. Standard common emitter. (Fig. 208 repeated)
RS B ib C
+ +
+
vs vin R2 R1 rπ β ib RC RL vo
- -
-
E
Fig. 210. Small signal equivalent circuit of common emitter amplifier.
The Common-Emitter Amplifier Introduction to Electronics 147
RS B ib C
+ +
+
vs vin RB rπ β ib R L’ vo
- -
-
E
Fig. 211. Simplified small signal equivalent of common emitter amplifier.
Voltage Gain
Our usual focus is Av = vo /vin , or Avs = vo /vs . We concentrate on the
former. Because ib is the only parameter common to both sides of
the circuit, we can design an approach:
1. We write an equation on the input side to relate vin to ib .
2. We write an equation on output side to relate vo to ib .
3. We combine equations to eliminate ib .
Thus: v in = v be = i b rπ (205)
′
v o = −βi bRL (206)
And: ′ ′
v o −βi bRL −βRL
Av = = = (207)
v in i b rπ rπ
Input Resistance
Rin
RS iin B ib C
+ +
+
vs vin RB rπ β ib RL vo
- -
-
E
Output Resistance
Recall that to find Ro , we must remove the load, and set all
independent sources to zero, but only independent sources. We do
not set dependent sources to zero!!!
Thus:
RS B ib C
RB rπ βi b RC Ro
E
Fig. 213. Output resistance of common emitter amplifier.
Ro = RC (210)
The Emitter Follower (Common Collector Amplifier) Introduction to Electronics 149
Introduction
VCC
R1
RS Cin
+ + Q1 Cout
vs +
- vin
RL vo
R2 RE
- -
Fig. 214. Standard emitter follower circuit.
RS B ib C
+
+
vs vin R2 R1 rπ βi b
- E
-
R1 || R2 = RB (β+1)ib
+
RE || RL = RL’ RE R L vo
-
Voltage Gain
RS B ib C
+
+
vs vin R2 R1 rπ βib
- E
-
R1 || R2 = RB (β+1)ib
+
RE || RL = RL’ RE RL vo
-
Fig. 216. Emitter follower small-signal equivalent (Fig. 215 repeated).
′
v o = (β + 1)i bRL (212)
vo (β + 1)RL ′
Av = = (213)
v in r + (β + 1)R ′
π L
Typical values for Av range from 0.8 to unity. The emitter (output)
voltage follows the input voltage, hence the name emitter follower.
The feature of the follower is not voltage gain, but power gain, high
input resistance and low output resistance, as we see next . . .
The Emitter Follower (Common Collector Amplifier) Introduction to Electronics 151
Input Resistance
Rin Rit
RS B ib C
+
+
vs vin R2 R1 rπ βib
- E
-
R1 || R2 = RB (β+1)ib
+
RE RL vo
RE || RL = RL -
Note that :
v in v in
Rin = = RB || Rit , where Rit = (214)
i in ib
We’ve already written the equation we need to find Rit . It’s equation
(211), from which:
′
Rit = rπ + (β + 1)RL (215)
Thus
[
Rin = RB || rπ + (β + 1)RL ′ ] (216)
Output Resistance
B ib C
RS R2 R1 rπ β ib
E
R 1||R 2||R S = R S’ (β+1)ib iy itest
+
RE vtest
-
R ot Ro
Fig. 218. Circuit for calculating follower output resistance.
RS ′ + rπ
But
v test (
= − i b RS ′ + rπ ) ∴ Rot =
β +1
(218)
4. Solve.
5. Check units!!!
FET Small-Signal Equivalent Circuit Introduction to Electronics 154
iD iD
vs
+ iS IDSS
V DC Q IDQ
Fig. 219. Generalized FET circuit.
vGS
VP VGSQ
iD
Transconductance
Q
∂i IDQ
gm = D (221)
∂v GS Q
vGS
VP VGSQ
From the pinch-off region Fig. 222.FET transfer characteristic.
equation:
i D = K (v GS − VP )
2
(222)
We obtain:
gm =
∂
∂v GS [
K (v GS − VP )
2
] Q
= 2K (VGSQ − VP ) (223)
IDQ
VGSQ − VP = (224)
K
Substituting this into eq. (223), we see that the transconductance
can also be written as:
gm = 2 KIDQ (225)
IDSS IDQ
gm = 2 (226)
VP
FET Small-Signal Equivalent Circuit Introduction to Electronics 156
∂i D ∂i D v ds
id = v gs + v ds = gmv gs + (227)
∂v GS Q
∂v DS Q
rd
where ∂i D 1
= = slope of output char. at Q (228)
∂v DS Q
rd
+ +
vsig +
vin
- RL vo
RG RS CS
- -
Fig. 225. Standard common source amplifier circuit.
Rsig iin G D
+ + +
+
vsig vin RG vgs gmvgs rd RD R L vo
- - - -
S
rd ||RD ||RL = RL’
Fig. 226. Small-signal equivalent circuit for the common source amplifier.
The Common-Source Amplifier Introduction to Electronics 158
Rsig iin G D
+ + +
+
vsig vin RG vgs gmvgs rd RD R L vo
- - - -
S
rd ||RD ||RL = RL’
Fig. 227. Common source small signal equivalent (Fig. 226 repeated).
Voltage Gain
′
v in = v gs and v o = −gmv gs RL (229)
Thus: vo ′
Av = = −gmRL (230)
v in
Input Resistance
v in
Rin = = RG (231)
i in
Output Resistance
Remember, we must remove RL , and set all independent sources
to zero. For this circuit we can determine Ro by inspection:
Ro = rd || RD (232)
The Source Follower Introduction to Electronics 159
Rsig Cin
+ + Cout
RG
vsig +
- vin
RL vo
RS
- -
Fig. 228. Source follower circuit.
+
rd ||RS ||RL = RL’ RS RL vo
-
Rsig iin G D
+ +
+
vsig vin RG vgs gmvgs rd
- - S
-
+
rd ||RS ||RL = RL’ RS RL vo
-
Voltage Gain
This one requires a little more algebra. Beginning with:
v in = v gs + v o ⇒ v gs = v in − v o (233)
and
v gs ′ 1 ′
(
v o = gmv gs ) ′
+ i in RL = gmv gs +
RG
RL = v gs gm +
R
RG L
(234)
We replace vgs in eq. (234) with eq. (233), and solve for vo /vin :
1 ′
v o = (v in − v o ) gm + RL (235)
RG
1 ′ 1 ′
1 + gm + RL v o = v in gm + RL (236)
R G RG
1 ′
gm + RL
vo RG
Av = = = 0.5 to 0.8 typically (237)
v in 1 ′
1 + gm + RL
RG
The Source Follower Introduction to Electronics 161
Rsig iin G D
+ +
+
vsig vin RG vgs gmvgs rd
- - S
-
+
rd ||RS ||RL = RL’ RS RL vo
-
Input Resistance
1 ′
v in = v gs + v o = v gs + v gs gm + RL (238)
RG
But vgs = iin RG :
1 ′
v in = i inRG + i inRG gm + RL (239)
RG
Solving for vin /iin :
v in ′
Rin = = RG + (1 + gmRG )RL (240)
i in
Rsig G D
+
RG vgs gmvgs rd
- S
itest +
RS vtest
-
Output Resistance
This calculation is a little more involved, so we shall be more formal
in our approach.
We remove RL , apply a test source, vtest , and set the independent
source to zero.
From a KCL equation at the source node:
v test v test v test
itest = + + − gmv gs (241)
RS rd RG + Rsig
1 1 1 gmRG
itest = v test + + + (243)
RS rd RG + Rsig RG + Rsig
The Source Follower Introduction to Electronics 163
Rsig G D
+
RG vgs gmvgs rd
- S
itest +
RS vtest
-
Thus:
v test 1
Ro = =
i test 1 1 1 gmRG (244)
+ + +
RS rd RG + Rsig RG + Rsig
R + Rsig
Ro = RS || rd || (RG + Rsig )|| G (245)
gmRG
Review of Bode Plots Introduction to Electronics 164
Introduction
The emphasis here is review. Please refer to an appropriate text if
you need a more detailed treatment of this subject.
Let us begin with a generalized transfer function:
f f
j 1 + j
fZ 1 fZ 2
Av (f ) = (246)
f
1 + j
fP 1
Remember:
● Bode plots are not the actual curves, but only asymptotes to
the actual curves.
● Bode magnitude plots are not based on the transfer function
itself, but on the logarithm of the transfer function - actually, on
20 log Av .
● The total Bode response for Av(f) consists of the magnitude
response and the phase response. Both of these consist of
the sum of the responses to each numerator and denominator
factor.
Review of Bode Plots Introduction to Electronics 165
f
20 dB/decade The numerator term 1 + j :
fZ 2
f
0 dB The denominator term 1 + j :
fp fP 1
f
+90O The numerator term j :
fZ1
Fig. 237. Bode phase response
for jf/fZ1 . The phase response is simply 90o for all
f.
f
+90O
The numerator term 1 + j :
10fz2 fZ 2
45O/decade
0O
For f << fZ2 the imaginary term is
fz2 /10
negligible; the phase is just 0o.
Fig. 238. Bode phase response
for 1 + jf/fZ2 . For f >> fZ2 the imaginary term
dominates, thus the phase is 90o.
At f = fZ2 , the term is 1 + j1; its phase is
45O.
f
0O
The denominator term 1 + j :
fp /10 O
-45 /decade fP 1
-90O
For f << fZ2 the imaginary term is
10fp
negligible; the phase is just 0o.
Fig. 239. Bode phase response
for 1 + jf/fP1 . For f >> fZ2 the imaginary term
dominates, thus the phase is -90o.
At f = fZ2 , the term is 1 + j1; its phase is
-45O.
Review of Bode Plots Introduction to Electronics 167
Single-Pole Low-Pass RC
We obtain:
2
1 f
Av = 20 log = 20 log(1) − 20 log 12 +
dB
f
2
fb
1 +
2
fb (250)
f
2
f 2
= −20 log 12 + = −10 log1 +
fb fb
Av , dB
fb /10 fb 10fb 100fb
f Note that the latter
-3 dB
equation decreases 20
dB for each factor of 10
-20 dB
increase in frequency
(i.e., -20 db per decade).
-40 dB
The Bode phase plot shows the characteristic shape of this inverse
tangent function:
θ, deg
fb /10 fb 10fb 100fb
0O f
-45O
-90O
Single-Pole High-Pass RC
1/sC The s-domain transfer function:
+
R sRC
+ Av = =
R Vo(s) 1 sRC + 1 (255)
Vin(s) +R
sC
-
Note there is a pole at s = -1/RC,
Fig. 244. Single-pole high-pass RC
circuit.
and a zero at s = 0.
Recall from Fig. (234) that the first term is a straight line, with +20
dB/dec slope, passing through 0 dB at fb .
The last term is the same term from the low pass example, which
has the form of Fig. (236).
The total Bode magnitude response is merely the sum of these two
responses.
Review of Bode Plots Introduction to Electronics 171
Av , dB
fb /10 fb 10fb 100fb
f
-3 dB
-20 dB
-40 dB
θ, deg
90O
45O
0O f
fb /10 fb 10fb 100fb
Coupling Capacitors
VCC
RB RC
Cout
RS Cin
+ + Q1
vs +
- vin
RL vo
- -
(1) we can draw the sm. sig. eq. (2) analyze it, determine the its
ckt. of the amplifier section only, model parameters, and . . .
ib Ro
+
+
RB r β ib RC vx Rin A v
- - vo x
Fig. 248. Amplifier sm. sig. eq. ckt. Fig. 249. Model equivalent to
amplifier section.
Coupling Capacitors Introduction to Electronics 173
RS Cin Ro Cout
+ + +
+
vs vx Rin Avo vx RL vo
- -
- -
Fig. 250. Complete circuit redrawn with amplifier section replaced by its model.
Note that both sides are identical topologically, and are single-pole,
high-pass circuits:
Now let’s work our way lower in frequency. . . when we get to the
first of the two pole frequencies, our Bode magnitude plot begins to
drop at 20 dB/decade. . . when we get to the second pole, the plot
drops at 40 dB/decade. . . see the illustration on the next page.
Coupling Capacitors Introduction to Electronics 174
20 log Av mid
20 dB/dec
f2
40 dB/dec
f1
1. RC-Coupled amplifiers:
Coupling capacitors - capacitors cost $
Direct-Coupled amplifiers:
No capacitors - bias circuits interact - more difficult design, but
preferable.
Introduction
We begin with two of the most common topologies of common-
emitter amplifier:
VCC
R1 RC
Cout
RS Cin
+ + Q1
vs REF +
- vin
RL vo
R2 REB
- CE -
VCC
RC
Cout
RS Cin
+ + Q1
vs REF +
- vin
RL vo
RB REB
- CE -
-VEE
Fig. 253. Generic dual-supply common emitter ckt.
(Let RL’ = RL || RC , RE = REF + REB )
Low- & Mid-Frequency Performance of CE Amplifiers Introduction to Electronics 177
RS iin B ib C io
+ +
+
vs vin RB r β ib RC RL vo
- -
-
E RL’
Rin REF
Midband Performance
vo − βRL ′ −RL ′
Av = = ≈ , if β >> 1 (261)
v in rπ + (β + 1)REF REF
vo Rin
Av = = Av (262)
s
vs RS + Rin
Rin =
v in
i in
[
= RB || rπ + (β + 1)REF ] (263)
where RX = rπ + (β + 1)REF .
Low- & Mid-Frequency Performance of CE Amplifiers Introduction to Electronics 178
Design Considerations
● In choosing a device we should consider:
Frequency performance
Noise figure
Power Dissipation
Device choice may not be critical. . .
● Design Tradeoffs:
1. RB large for high Rin and high Ai
RB small for bias (Q-pt.) stability
2. RC large for high Av and Ai
RC small for low Ro , low signal swing, high frequency
response
3. REF small (or zero) for maximum Av and Ai
REF > 0 for larger Rin , gain stability, improved high and
low frequency response, reduced distortion
● Gain Stability:
Note from eq. (261), as REF increases, Av ≈ -RL’/REF , i.e., gain
becomes independent of β !!!
Low- & Mid-Frequency Performance of CE Amplifiers Introduction to Electronics 179
vo 1
for Av = fin = (268)
vs 2π (RS + Rin )Cin
Equations for fin are approximate, because the effects of Cin and CE
interact slightly. The interaction is almost always negligible.
Low- & Mid-Frequency Performance of CE Amplifiers Introduction to Electronics 180
RS B ib C io
+ +
+
vs vin RB rπ β ib R L’ v o
- -
-
E
REF
REB CE
Fig. 256. Approximate common emitter sm. sig. equivalent at low frequencies.
Only the effect of CE is accounted for in this circuit.
Av , dB
CE = short ckt.
f1
f2
CE = open ckt.
REB Rthevenin
ib ic v be v
ib = = − test (270)
rπ rπ
+
vbe r βib
- i test = −(β + 1)i b (271)
itest v test r
+ RY = = π (272)
vtest itest β +1
RY =
(RB || RS ) + rπ (273)
β +1
Low- & Mid-Frequency Performance of CE Amplifiers Introduction to Electronics 182
1
The zero f2 is the frequency where ZE ( jf2 ) = RE || =∞ :
jf2CE
1
f2 = (276)
2πCE REB
20 log Av mid
20 dB/dec
f1
The Bode magnitude plot of a common
40 dB/dec fout emitter amplifier is the summation of the
effects of poles fin , fout , f1 , and the zero f2 .
fin
60 dB/dec
One of many possible examples is shown
f2
at left.
40 dB/dec
Introduction
Before we can examine the high frequency response of amplifiers,
we need some additional tools. The Miller Effect is one of them.
Consider:
Iz
Z
“Black Box”
+ +
Vin Vout = AvVin
- -
“Black Box”
Iz
+ +
Vin Zin, Miller Zout, Miller Vout = AvVin
- -
If we can choose Zin. Miller so that Iz is the same in both circuits, the
input port won’t “know” the difference - the circuits will be equivalent
at the input port.
The Miller Effect Introduction to Electronics 184
π BJT Model
The Hybrid-π
The Model
This is another tool we need before we examine the high frequency
response of amplifiers.
The hybrid-π BJT model includes elements that are negligible at low
frequencies and midband, but cannot be ignored at higher
frequencies of operation:
Cµ
B rx B’ rµ C
+
vπ rπ Cπ g mv π ro
-
E E
Effect of Cπ and Cµ
Cµ
B rx B’ rµ C
+
vπ rπ Cπ g mv π ro
-
E E
B B’ C
+
vπ rπ C1 Cπ gmvπ C 2 ro
-
E E
Fig. 265. Simplified hybrid-π BJT model using the Miller Effect and the other
assumptions described in the text..
The Hybrid-π BJT Model Introduction to Electronics 187
B B’ C
+
vπ rπ C1 Cπ gmvπ C 2 ro
-
E E
Fig. 266. Miller Effect applied to hybrid-π model (Fig. 265 repeated).
C1 = Cµ (1 − Av ) ≈ Av Cµ (281)
1
C2 = Cµ 1 − ≈ Cµ (282)
Av
Individually, all Cs in Fig. 266 have a single-pole low-pass effect.
As frequency increases they become short circuits, and vo
approaches zero .
Thus there are two low-pass poles with the mathematical form:
1
fb = (283)
2πCeqRThevenin
fh1
Because C1 + Cπ >> C2 , the pole
due to C1 + Cπ will dominate.
fh2
The pole due to C2 is usually
negligible, especially when RL’ is
Fig. 267. Typical amplifier response in the included in the circuit.
midband and high-frequency regions. fh1 is
normally due to C1 + Cπ , and fh2 is normally
due to C2 .
The Hybrid-π BJT Model Introduction to Electronics 188
B B’ C
+
vπ rπ C1 Cπ gmvπ C 2 ro
-
E E
Fig. 268. Miller Effect applied to hybrid-π model (Fig. 265 repeated).
1 1
fH ≈ ≈ (285)
2πC1RThevenin 2π Av Cµ RThevenin
+ + Q1
vs +
- vin
CE RL vo
R2 RE
- -
Now we use the hybrid-π equivalent for the BJT and construct the
small-signal equivalent circuit for the amplifier:
Cµ
RS B rx B’ rµ C
+
+ +
vs vin RB = R1||R2 vπ rπ Cπ g mv π ro RL||RC
- -
- E E
RL’ = ro||RL||RC
Fig. 270. Amplifier small-signal equivalent circuit using hybrid-π BJT model.
High-Frequency Performance of the CE Amplifier Introduction to Electronics 190
High-Frequency Performance
We can simplify the circuit further by using a Thevenin equivalent
on the input side, and by assuming the effect of rµ to be negligible:
Cµ
RS’ B’ C
+ + +
vs’ vπ Cπ g mv π R L’ vo
- - -
R S’ B’ C
+ + +
v s’ vπ Cπ Cµ (1+gmRL’) g m vπ R L’ vo
- - -
Fig. 272. Final (approximate) equivalent after applying the Miller Effect.
High-Frequency Performance of the CE Amplifier Introduction to Electronics 191
R S’ B’ C
+ + +
v s’ vπ Cπ Cµ (1+gmRL’) g m vπ R L’ vo
- - -
Fig. 273. Final (approximate) equivalent after applying the Miller Effect (Fig. 272
repeated).
So we have
1
fh1 =
′ (287)
2πRS Ctotal
where
′
Ctotal = Cπ + Cµ 1 + gmRL (288)
and
[
RS ′ = rπ || rx + (RB || RS ) ] (289)
High-Frequency Performance of the CE Amplifier Introduction to Electronics 192
20 log Av mid
20 dB/dec
-20 dB/dec
f1 fh1
40 dB/dec
fout
fin
60 dB/dec
f2
40 dB/dec
Fig. 274. One example of the entire Bode magnitude response of a common
emitter amplifier.
Of this plot, the lower and upper 3-dB frequencies are the most
important, as they determine the bandwidth of the amplifier:
BW = fH − fL ≈ fh1 − f1 (290)
where the latter approximation assumes that adjacent poles are far
away.
We’ve estimated the frequency response of only one amplifier
configuration, the common-emitter. The techniques, though, can be
applied to any amplifier circuit.
Nonideal Operational Amplifiers Introduction to Electronics 193
Linear Imperfections
Input and Output Impedance:
Ideally, Rin = ∞ and Rout = 0.
Realistically, Rin ranges from ≈ 1 MΩ in BJT op amps to ≈ 1 TΩ in
FET op amps.
Rout ranges from less than 100 Ω in general purpose op amps, to
several kΩ in low power op amps.
Gain and Bandwidth:
Ideally, Av = ∞ and BW = ∞ .
Realistically, Av ranges from 80 dB (104) to 140 dB (107).
Many internally-compensated op amps have their BW restricted to
prevent oscillation, producing the Bode magnitude plot shown:
Av , dB The transfer function, then, has a
100 20 log A0
single-pole, low-pass form:
80 fb
A0
A(s ) =
60 20 dB/decade
s (291)
40
+1
20 ft = A0fb
2πfb
0 f, Hz
1 10 102 103 104 105 106 And gain-bandwidth product is
constant:
Fig. 275. Typical op amp Bode magnitude
response.
ft = A0fb = Aof fbf (292)
Nonideal Operational Amplifiers Introduction to Electronics 194
Nonlinear Imperfections
Output Voltage Swing:
BJT op amp outputs can swing to within 2VBE of ± VSUPPLY .
FET op amp outputs an swing to within a few mV of ± VSUPPLY .
Slew-Rate Limiting:
dv o
This is the maximum rate at which vO can change, ≤ SR . It
dt
is caused by a current source driving the compensation capacitor.
As an example, the LM741 has a SR of ≈ 0.5 V/µs.
vo
Expected output
Actual output
Full-Power Bandwidth:
This is defined as the highest frequency for which an undistorted
sinusoidal output is obtainable at maximum output voltage:
dv o
v o (t ) = VOM sin ωt ⇒ = SR = ωVOM = 2πfVOM (293)
dt max
DC Imperfections:
Many of the concepts in this section are rightly credited to Prof. D.B.
Brumm.
Input Currents:
Currents into noninverting and inverting inputs are not exactly zero,
but consist of base bias currents (BJT input stage) or gate leakage
currents (FET input stage):
II+ , current into noninverting input
II- , current into inverting input
These also have a polarity as well as a magnitude.
Nonideal Operational Amplifiers Introduction to Electronics 196
VIO
II- i=0
v- - + -
ideal vO
+ op amp
II i=0
v+ +
IB - IIO/2 IB + IIO/2
RN RF + RN RF
- vIN
- -
+ +
R+ R+
+ vIN
-
Fig. 279. Inverting op amp
configuration.
Fig. 278. Noninverting op amp
configuration.
RN RF
-
+
R+
VIO
I I- i=0
v- - + -
ideal vO
+ op amp
II i=0
v+ +
IB - IIO/2 IB + IIO/2
And replace the ideal op amp of Fig. 280 with this model:
RN RF
-
I
-
VOE
+
I+
R+
VIO -
+
We can now determine the dc output error for virtually any op amp
configuration. We have already noted the dc output error as VOE .
R
VOE , Part A = − 1 + F (VIO + R + I + ) (297)
RN
Nonideal Operational Amplifiers Introduction to Electronics 200
RN RF
I- Next, we consider just I- , i.e.,
- we let VIO = 0 and I+ = 0.
Now v+ = v- = 0, so there is no
VOE
+
current through RN .
+
I The current I- must flow
R+
through RF , creating the dc
VIO - output error component:
+
RN + RF RN R
VOE , Part B = RF I − = 1 + F R − I − (299)
RN RN + RF RN
where
RN
R− = RF = RF || RN (300)
RN + RF
R
VOE = − 1 + F (VIO + R + I + − R − I − ) (301)
RN
Nonideal Operational Amplifiers Introduction to Electronics 201
10 kΩ 100 kΩ
The maximum bias current is
vIN +
- 100 nA, i.e.,
-
IB ∈[0, 100] nA (302)
vO
+ A positive value for IB means
into the chip.
Fig. 285. DC output error example.
R
VOE = − 1 + F (VIO − R − I − ) (305)
RN
● Thus we know VOE will lie between -22 mV and +34 mV.
R
VOE = − 1 + F (VIO + R + I + − R − I − ) (308)
RN
R I I
VOE = − 1 + F VIO + R + IB + IO − R − IB − IO
RN 2 2
(309)
R I
= − 1 + F VIO + (R + − R − )IB + (R + + R − ) IO
RN 2
R + = R − = RF || RN (310)
Instrumentation Amplifier
Introduction
R1 R2 Recall the basic op amp
v2 difference amplifier:
-
R2
-
vID
vO = (v 1 − v 2 ) (311)
vO R1
+
+
R3 R4
v1
R4 R 2
only if: =
Fig. 286. Difference amplifier. R3 R1
-
- R2 R R
- -
R1 -
vID vID vY
vO
R1 +
+ + R R
+ R2
-
v1 +
Fig. 287. Instrumentation amplifier.
Instrumentation Amplifier Introduction to Electronics 205
v2 +
-
- R2 R R
- -
R1 -
vID vID
vO
R1 +
+ + R R
+ R2
-
v1 +
Simplified Analysis
The input op amps present infinite input impedance to the
sources, thus the internal resistances of v1 and v2 are now
negligible.
Because the op amps are ideal vID appears across the series
R1 resistances. Current through these resistances is:
v
iR1 = ID (312)
2R1
R
v O = v Y = 1 + 2 (v 1 − v 2 ) (313)
R1
Instrumentation amplifiers are available in integrated form,
both with and without the R1 resistances built-in.
Noise Introduction to Electronics 206
Noise
Johnson Noise
This is noise generated across a resistor’s terminals due to random
thermal motion of electrons.
Johnson noise is white noise, meaning it has a flat frequency
spectrum - the same noise power in each Hz of bandwidth:
pn = 4kTB (314)
er = 4kTRB (315)
Shot Noise
Shot noise arises because electric current flows in discrete charges,
which results in statistical fluctuations in the current.
The rms fluctuation is a dc current IDC is given by:
Ir = 2qIDC B (317)
1/f noise is pink noise - it has a 1/f spectrum, which means equal
power per decade of bandwidth, rather than equal power per Hz.
Noise Introduction to Electronics 209
The table below lists the excess noise for various resistor types.
The entries are given in rms voltage, per volt applied across the
resistor, and measured over one decade of bandwidth:
Interference
In this case any interfering signal or unwanted “stray” pickup
constitutes a form of noise.
Rsig en
+ Noiseless
vsig in
Noisy amplifier
Fig. 289. Noise model of an amplifier.
Signal-to-Noise Ratio:
Expressed in decibels, the default definition is a ratio of signal
power to noise power (delivered to the same resistance, and
measured with the same bandwidth and center frequency):
P
SNR = 10log sig dB (318)
Pn
It can also be expressed as the ratio of rms voltages:
v
SNR = 20log sig dB (319)
en
Amplifier Noise Performance Introduction to Electronics 213
Noise Figure:
This is a figure of merit for comparing amplifiers. It indicates how
much noise an amplifier adds.
Defined simply:
Psig / Pn ( )
NF = 10log input
dB
( )
(320)
Psig / Pn output
It can be written even more simply:
NF = SNRinput − SNRoutput (321)
Noise Temperature:
An alternative figure of merit to noise figure, it gives the same
information about an amplifier. The definition is illustrated below:
Av Vn Av Vn
Fig. 290. Noisy amplifier with ideal Fig. 291. Ideal amplifier with noisy
input. input.
Converting NF to/from Tn :
( ) ⇔ NF = 10 log n + 1
T
Tn = T 10NF / 10 − 1 (322)
T
where, NF is expressed in dB
T is the ambient (room) temperature, usually 290 K
v total = v sig + en
2 2 2
(323)
Amplifier Noise Calculations Introduction to Electronics 215
Introduction
Rsig en
+ Noiseless
vsig in
Noisy amplifier
Fig. 292. Noise model of an amplifier (Fig. 289 repeated).
et = er + en + i n Rsig
2 2 2 2 2
(324)
For convenience, we define the last two terms of eq. (324) as the
equivalent amplifier input noise, i.e., the amplifier noise contribution
with a noise-free Rsig :
eeq = en + i n Rsig
2 2 2 2
(325)
Amplifier Noise Calculations Introduction to Electronics 216
(
Psig / Pn )
= 10 log Psig input × Pn output
NF = 10 log
input
(
Psig / Pn
)
output
P
n input × Psig output
P
= 10 log 2
(
sig input Gp et
2
) = 10 log e 2 er 2 + en 2 + i n 2Rsig 2 (326)
2 = 10 log
t
(
er Psig inputGp
) er er 2
en 2 + i n 2Rsig 2 eeq 2
= 10 log 1 + 2
= 10 log 1 + 2
e r er
Observe that for small Rsig , amplifier noise voltage dominates, while
for large Rsig , the amplifier noise current dominates.
FET amplifiers have nearly zero noise current, so they have a clear
advantage !!!
Introduction
Fig. 293. 2N5210 noise voltage vs. Fig. 294. 2N5210 noise current vs. frequency,
frequency, for various quiescent collector for variousquiescent collector currents.
currents.
et = er + en + i n Rsig
2 2 2 2 2
(327)
Example #1
Calculate the total equivalent input noise per unit bandwidth, for a
2N5210 operating at 100 Hz with a source resistance of 1 kΩ, and
a collector bias current of 1 mA:
1. er ≈ 4.02 nV / Hz from eq. (316).
2. en ≈ 4.5 nV / Hz (f = 100 Hz, IC = 1 mA) from Fig. 293.
3. in ≈ 3.5 pA / Hz (f = 100 Hz, IC = 1 mA) from Fig. 294.
Evaluating eq. (327) - remembering to square the terms on the
right-hand side, and take the square root of the resulting sum -
gives :
et = 6.97 nV / Hz (328)
Example #2
Determine the narrow bandwidth noise figure for the amplifier of
example #1 (f = 100 Hz, ICQ = 1 mA, Rsig = 1 kΩ).
1. From eq. (326), repeated here
en 2 + i n 2Rsig 2
NF = 10 log1 + 2
(329)
e r
with the values of en , in , and er from example #1, we calculate:
(5.70)2
NF = 10 log1 + 2
= 10 log(3.01) = 4.79 dB (330)
(4.02)
which compares favorably to the value of approx. 5 dB obtained
from the manufacturer’s data shown below:
2. The Art of Electronics, 2nd ed., Paul Horowitz and Winfield Hill,
Cambridge University Press, New York, 1989.
3. The 2N5210 data sheets, of which Figs. 293 - 296 are a part,
are available from Motorola, Inc., at http://www.motorola.com
Introduction to Logic Gates Introduction to Electronics 221
The Inverter
We will limit our exploration to the logic inverter, the simplest of
logic gates. A logic inverter is essentially just an inverting amplifier,
operated at its saturation levels:
VO
VDC ideal
VDC
VI VO
actual
Noise Margin
Noise margin is the maximum noise amplitude that can be added
to the input voltage, without causing an error in the output logic
level. It is the smaller of:
NM H = VOH − VIH and NM L = VIL − VOL (331)
VDC
VO Output:
tr. fn. forbidden regions Logic 1
VDC Input sees
Logic 1
VOH
NMH
VOH
VIH
VIL
VOL NML Input sees
VI VOL Logic 0
VIL VIH VDC Output: Logic 0
0
Fig. 300. Mfr’s voltage specs illustrated with Fig. 299. Mfr’s voltage specs illustrated
example transfer functions. on a number line.
Introduction to Logic Gates Introduction to Electronics 223
Fan-Out
I
FOH = int OH (332)
IIH
and
I
FOL = int OL (333)
IIL
Fig. 302. Fan-out illustrated.
Introduction to Logic Gates Introduction to Electronics 224
Power Consumption
But energy per unit time is power, i.e., the dynamic power
dissipation:
Pdynamic = CLOADVDC f
2
(338)
Introduction to Logic Gates Introduction to Electronics 226
tr tf
vI
VOH
100%
90%
50%
10% VOL
0%
t
tPHL tPLH
vO
VOH
50%
VOL
Speed-Power Product
advanced LS
advanced S
low-power S
parameter
standard
Schottky
FAST
ALS
AS
LS
unit
F
tPD ns 10 3 10 2 4 3
Pstatic mW 10 19 2 7 1 4
IOH µA -400 -1000 -400 -2000 -400 -1000
IOL mA 16 20 8 20 8 20
IIH µA 40 50 20 20 20 20
IIL mA -1.6 -2.0 -0.4 -0.5 -0.1 -0.6
VOH V 2.4 2.7 2.7 3.0 3.0 2.7
VOL V 0.4 0.5 0.5 0.5 0.5 0.5
VIH V 2.0 V for all TTL families
VIL V 0.8 V for all TTL families
. . . table compiled by Prof. D.B. Brumm
Introduction to Logic Gates Introduction to Electronics 229
74HCT
74HC
4000
ACT
74C
AC
unit
tPD ns 80 90 9 10 5 5
Pstatic < 1 µW for all versions
IOH mA -1.0 -0.36 -4.0 -4.0 -24 -24
IOL mA 2.4 0.36 4.0 4.0 24 24
IIH µA 1.0 1.0 1.0 1.0 1.0 1.0
IIL mA -1.0 -1.0 -1.0 -1.0 -1.0 -1.0
VOH V 2.5 2.4 3.5 3.5 3.7 3.7
VOL V 0.4 0.4 0.4 0.4 0.4 0.4
VIH V 3.5 3.5 3.5 2.0 3.5 2.0
VIL V 1.5 1.5 1.0 0.8 1.5 0.8
VDC V 3 - 15 3 - 15 2-6 5±0.5 2-6 5±0.5
. . . table compiled by Prof. D.B. Brumm
MOSFET Logic Inverters Introduction to Electronics 230
Circuit Operation:
The term NMOS implies an n-channel enhancement MOSFET.
Using a graphical analysis technique, we can plot the load line on
the output characteristics, shown below.
When the FET is operating in its triode region, it pulls the output
voltage low, i.e., toward zero. When the FET is in cutoff, the drain
resistance pulls the output voltage up, i.e., toward VCC , which is why
it is called a pull-up resistor.
Because VGS = VI and VDS = VO , we can use Fig. 307 to plot the
transfer function of this inverter.
V DD 10 V 9 8V VGS = 7 V
VGS = 6 V
R pull-up
Drain Current, ID
VO VGS = 5 V
VI
VGS = 4 V
VGS = 3 V
Output Voltage, VO
Input Voltage, VI
Fig. 308. Inverter transfer function.
Drawbacks:
1. A large R results in reduced VO for anything but the largest
loads, and slows output changes for capacitive loads.
2. A small R results in excessive current, and power dissipation,
when the output is low.
CMOS Inverter
10 V 9 8V VGSN = 7 V
VGSN = 6 V
Drain Current, ID
VGSN = 5 V
VGSN = 4 V
VGSN = 3 V
10 V 9 8V VSGP = 7 V
VSGP = 6 V
Drain Current, |ID|
VSGP = 5 V
VSGP = 4 V
VSGP = 3 V
The PMOS output curves, above, are typical also, but on the input
side of the PMOS FET:
v SGP = VDD − v GSN (339)
This means we can “rotate and shift” the curves to display them in
terms of vDSN. This is done on the following page.
MOSFET Logic Inverters Introduction to Electronics 234
VGSN = 3 V 2V 1 0V
VGSN = 4 V (VSGP = 6 V)
Drain Current, |ID|
VGSN = 5 V (VSGP = 5 V)
VGSN = 6 V (VSGP = 4 V)
VGSN = 7 V (VSGP = 3 V)
VDSN (= 10 V - VSDP )
Fig. 312. PMOS “load curves” for VDD = 10 V.
The curves above are the same PMOS output characteristics of Fig.
233, but they’ve been:
10 V 9 8V VGSN = 7 V VGSN = 3 V 2 V 1 0V
VGSN = 4 V VGSN = 6 V
Drain Current, |ID|
VGSN = 5 V VGSN = 5 V
VGSN = 6 V VGSN = 4 V
VGSN = 7 V VGSN = 3 V
Note from Fig. 313 That for VI = VGSN ≤ 2 V the NMOS FET (blue
curves) is in cutoff, so the intersection of the appropriate NMOS and
PMOS curves is at VO = VDSN = 10 V.
As VI increases above 2 V, we select the appropriate NMOS and
PMOS curve, as shown in the figures below.
Drain Current, |ID|
VI = VGSN = 3 V
VI = VGSN = 4 V
VI = VGSN = 5 V
VI = VGSN = 6 V
VI = VGSN = 7 V
Input Voltage, VI
Fig. 319. CMOS inverter transfer function. Note the similarity to
the ideal transfer function of Fig. 298.
Differential Amplifier Introduction to Electronics 239
Differential Amplifier
1
1 +
vID /2
2 vICM -
+ + - +
vI1 vI2 +
- - vID /2
-
2
Fig. 320. Representing two sources by their differential and
common-mode components (Fig. 41 repeated).
Note that the differential voltage vID is the difference between the
signals vI1 and vI2 , while the common-mode voltage vICM is the
average of the two (a measure of how they are similar).
Differential Amplifier Introduction to Electronics 240
RC RC
Now we let vID = 2 V and vICM = 0.
+ vOD - Note that Q1 is active, but Q2 is
iC1 + + iC2
vO1
-
vO2
-
cutoff. Thus we have:
+1 V -1 V iC2 = 0 (348)
+ Q1 Q2 +
0.7 V -1.3 V
- 0.3 V - v O 2 = VCC (349)
+ IBIAS -
vID /2 = 1 V vID /2 = 1 V iC1 = αi E 1 = αIBIAS (350)
- +
-VEE v O1 = VCC − αRC IBIAS (351)
Fig. 323. Differential amplifier with +2 V
differential input. v OD = −αRC IBIAS (352)
RC RC
This is a mirror image of Case
#2A. We have vID = -2 V and
+ vOD -
iC1 + + iC2 vICM = 0.
vO1 vO2
- -
-1 V +1 V Now Q2 is active and Q1 cutoff:
+ Q1 Q2 +
-1.3 V 0.3 V 0.7 V iC1 = 0 (353)
- -
+ IBIAS - v O1 = VCC (354)
vID /2 = -1 V vID /2 = -1 V
- + iC 2 = αi E 2 = αIBIAS (355)
-VEE
Fig. 324. Differential amplifier with -2 V v O 2 = VCC − αRC IBIAS (356)
differential input.
v OD = αRC IBIAS (357)
VCC
We begin by assuming identical devices
RC RC in the active region, and use the forward-
+ vOD - bias approximation to the Shockley
+ +
iC1 vO1 vO2 iC2 equation:
- -
vI1 Q1 Q2 vI2 V
iC1 = IS exp BE 1 (358)
VT
IBIAS
v
-VEE iC 2 = IS exp BE 2 (359)
Fig. 325. Differential amplifier circuit VT
(Fig. 321 repeated).
iC 1 v − v BE 2 v
= exp BE 1 = exp ID (360)
iC 2 VT VT
iC 1 v
+ 1 = 1 + exp ID (361)
iC 2 VT
vID / VT
Fig. 326. Normalized collector currents vs.
normalized differential input voltage, for a differential
amplifier.
Note that IBIAS is steered from one side to the other . . .as vid
changes from approximately -4VT (-100 mV) to +4VT (+100 mV)!!!
Large-Signal Analysis of Differential Amplifier Introduction to Electronics 244
Using (363) and (364), and recalling that vOD = RC ( iC2 - iC1 ):
v ID v ID
exp − α I BIAS exp −
α I 2V 2VT
iC 2 = BIAS T
= (365)
v ID v ID v ID v ID
1 + exp exp − exp + exp−
V T 2V
T 2 V T 2V T
v ID v ID
exp α I BIAS exp
α I 2V 2V T
iC 1 = BIAS T
= (366)
v ID v ID v ID v ID
1 + exp − exp exp + exp −
VT 2V
T 2V T 2 VT
v v
exp ID − exp − ID
2VT 2VT
v OD = −αIBIAS RC (367)
v v
exp ID + exp − ID
2VT 2VT
v
v OD = −αIBIAS RC tanh ID (368)
2VT
VOD / αRCIBIAS
vID / VT
Fig. 327. Normalized differential output voltage vs.
normalized differential input voltage, for a differential
amplifier.
This transfer function is linear only for |vID /VT| much less than 1,
i.e., for |vID| much less than 25 mV!!!
We usually say the transfer function is acceptably linear for a |vID|
of 15 mV or less.
If we can agree that, for a differential amplifier, a small input signal
is less than about 15 mV, we can perform a small-signal analysis of
this circuit !!!
Small-Signal Analysis of Differential Amplifier Introduction to Electronics 246
RC RC
+ vod -
+ +
ib1 vo1 vo2 ib2
- -
+ -
vid /2 rπ βib1 βib2 rπ vid /2
- +
vX
(β+1)ib1 (β+1)ib2
REB
RC RC
+ vod -
+ +
ib1 vo1 vo2 ib2
- -
+ -
vid /2 rπ βib1 βib2 rπ vid /2
- +
vX
(β+1)ib1 (β+1)ib2
REB
−
v id
2
[ ]
= i b 2 rπ + (β + 1)REB + i b1 (β + 1)REB [ ] (372)
Small-Signal Analysis of Differential Amplifier Introduction to Electronics 248
RC RC
+ vod -
+ +
ib1 vo1 vo2 ib2
- -
+ -
vid /2 rπ βib1 βib2 rπ vid /2
- +
vX
(β+1)ib1 (β+1)ib2
REB
[
0 = (i b1 + i b 2 ) rπ + 2(β + 1)REB ] (373)
(ib1 + ib 2 ) = 0 (374)
RC RC
+ vod -
+ +
ib1 vo1 vo2 ib2
- -
+ -
vid /2 rπ βib1 βib2 rπ vid /2
- +
vX
(β+1)ib1 (β+1)ib2
REB
VCC
We now restrict the input to a
RC RC common-mode voltage only.
+ vOD - This is, we let vID = 0.
iC1 + + iC2
vO1 vO2
- -
We again construct the small-signal
vI1 Q1 Q2 vI2 circuit using the techniques we
studied previously.
RC RC
+ vod -
+ +
ib1 vo1 vo2 ib2
- -
+ +
vicm rπ βib1 βib2 rπ vicm
- -
(β+1)ib1 (β+1)ib2
2REB 2REB
RC RC
+ vod -
+ +
ib1 vo1 vo2 ib2
- -
+ +
vicm rπ βib1 βib2 rπ vicm
- -
iX = 0
(β+1)ib1 (β+1)ib2
2REB 2REB
This “decouples” the left half-circuit from the right half-circuit at the
emitters.
At the top of the circuit, the small-signal ground also decouples the
left half-circuit from the right half-circuit.
Avcd = 0 (382)
Ricm =
v icm v 1
[
= icm = rπ + (β + 1)2REB
ib1 + i b 2 2i b1 2
] (383)
5943
Summer 1999
HIGHER STILL
Electronic and
Electrical
Fundamentals
Combinational Logic
Intermediate 2
Support Materials
qrstuv
The Higher Still Development Programme gratefully acknowledges the support and assistance of
colleagues at South Lanarkshire College in contributing material and helpful advice for this pack, as
well as the help of lecturers and development officers from other colleges who assisted in the
preparation of this pack by contributing material and commenting on drafts.
Every attempt has been made to trace copyright owners. The Higher Still Development Programme
apologises for any omission which, if notified, it will be pleased to rectify at the earliest opportunity.
This publication may be reproduced in whole or in part for educational purposes provided that no profit
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Teacher/Lecturer Notes
TEACHER/LECTURER MATERIALS
CONTENTS
Section 1 Outcomes
Section 7 Safety
Outcome 1
Perform simple binary operations.
Performance criteria
a. The conversion between decimal and binary quantities is correctly performed.
b. The conversion between decimal and hexadecimal quantities is correctly
performed.
c. The conversion between hexadecimal binary and quantities is correctly
performed.
d. The operation of binary addition is correctly performed.
Evidence requirements
The student will be set short answer questions to test the ability to perform simple
binary operations. The test could comprise 8 short answer questions involving
numbers with no more than four bits. The questions could be allocated as follows
1. Conversion - 6 questions
2. Addition - 2 questions
Outcome 2
Identify the function of logic gates.
Performance criteria
a. Logic functions are correctly identified from given BS-EN 60617 and ANSI
symbols
b. Truth tables are constructed using measurement of input and output conditions.
c. Boolean expressions are obtained from the truth tables
Evidence requirements
The student will be presented with a set of logic gates and a supply for each. He/she
will then test the input/output for NOT function, three input OR, AND, NAND and
NOR from which he/she will identify each gate and provide the truth table and
boolean expression for each.
Performance criteria
a. The assembly of a three input logic circuit is correct.
b. The construction of the truth table for the assembled circuit is accurate.
c. The Boolean expression is correctly derived from the truth table.
Evidence requirements
A diagram of a circuit with a minimum of four gates should be given to the student.
The student will be required to assemble the circuit and test its operation by obtaining
the truth table and deriving the expression.
Satisfactory achievement of the outcome will be based on the student attaining all of
the performance criteria.
Outcome 4
Solve combinational logic system problems.
Performance criteria
a. An accurate logic system is produced.
b. The assembly of the sytem designed is correct.
c. The recording of results and measurement of the system specification in the form
of a truth table is accurate.
Evidence requirements
The student will be required to design and assemble a practical circuit for a task
which will be stated by the teacher/lecturer. The task will be restricted to three input
variables.
Satisfactory achievement of the outcome will be based on the student attaining all of
the performance criteria.
Teaching and learning advice, including how to use the resource material
Teaching methods
The teaching and learning methods used are very dependent on the contents of the
unit and the facilities and expertise available at the delivering centre. By their very
nature, however, the units in the Intermediate 2 Electronic and Electrical
fundamentals course suggest the following teaching methods:
OUTCOME 1
Number systems Explain number system rules and importantance to digital
systems, handout and tutorial examples.
OUTCOME 2
Identify logic gates Logic gate function and truth tables, simple electrical
representation of logic gates, handout and tutorial
examples, practical investigation of each gate with
student constructing each circuit.
OUTCOME 3
Assemble and test a logic circuit Practical exercises to introduce the student to logic circuit
construction, followed by student developing each circuit.
Production of annotated circuit diagrams using data
Use of data sheets sheets should be encouraged at all times.
Construction of truth tables from working circuits and
Truth tables derivation of Boolean expression.
OUTCOME 4
Solve combinational logic problems Analysis of given problem, development of truth tables
and Boolean expression, construction and testing of
circuits.
Recommended entry for this unit is currently given as Mathematics and either
Technological Studies or Physics at Standard Grade 3 or above.
Mathematics
Addition and subtraction of numbers.
Electrical
Having covered the work for Electrical Fundamentals prior to starting on
combinational logic would cover all the electrical concepts required for this unit.
Electronics
Identification of electronic components, interpretation of schematic diagrams and
their relationship with wiring diagrams should be covered before starting this unit
(this can be covered by outcomes 1 and 2 of unit 2150220). Use of electronic test
instruments, such as digital multimeters.
The following table shows how assessment tasks are related to their learning
outcomes. It also lists the evidence, which should be collected.
ASSESSMENT OUTCOME EVIDENCE
TASK
The assessments both assignments and practical exercise are carried out individually
and under closed book conditions apart from the data sheets supplied.
1 20 minutes
2 20 minutes
3 60 minutes
4 90 minutes
5 90 minutes
Resource requirements including course notes, book list, and audio/visual aid list
Course notes
Student notes covering all course work are provided in the student’s support material.
These should be either adopted by the centre or modified to suit the teaching approach
taken and the equipment available.
Book list
The following book will provide all the information required for the electrical and
electronics fundamentals course and is only one of many books that could be adopted
as a course book:
Electronics for Today and Tomorrow, Tom Duncan (John Murray Publishers).
Audio/visual aids
The electronics laboratory should have prominently displayed an electrical safety
notice. These are available from a variety of electrical and electronic wholesale
outlets and distributors and are relatively inexpensive.
Component manufacturers and distributors offer wall charts and posters showing
many aspects of electronics. These vary from resistor colour codes to product
processing details and application advertisements. They are generally free and
available on request. They are useful as visual aids on the walls of the electronics
teaching laboratory as they create atmosphere and over a period of time act as a
constant reminder to students.
There are numerous sources of technical information on electronics other than the
traditional library books. These sources, however are only helpful if they are both
accessible and relevant. The following has been refined through use and experience
but inevitably will be superseded by better methods as the technology advances and
they become available.
RS
Web Site http://rswww.com
e-mail http://rswww.com
Telephone: Customer services: 01536 201201
Free technical helpline: 01536 402888
Address RS Components Ltd. P.O.Box 99, Corby, Northants NN17 9RS
Farnell
Web Site http://www.farnell.co.uk
e-mail Enquiries@farnell.com
Telephone: Customer services: 0113 263311
Free technical helpline: 0113 2799123
Address Farnell Electronic Components, Canal Road, Leeds, LS12 2TU
Selected data books, reference books and specialist texts should also be provided from
those offered by the above sources. There are so many good items on offer it is
impossible to recommend a definitive list, which is largely a matter of local
preference. Choices should be based on staff expertise, the teaching and learning
approaches used and the available budget. As many of the smaller specialised texts
are low cost it should be possible to provide several reference copies for use in the
electronics laboratory.
Many manufacturers of electronic components have web sites. These may be located
by a net search using the manufacturer’s name. Once into the web site it is often
possible to locate technical data, application information and in some situations
design tutorials.
Components
The Electronics Laboratory should offer access to component stocks as a standard
facility. This is for the benefit of both staff and students who will require access to
components for demonstrations, experimentation and for case study and project work.
The stock however, has to be managed and controlled if the quality of the facility is to
be sustained. The approach taken to this is a matter for the centre’s organisational
structure but experience suggests that one person needs to be clearly identified as
having responsibility for the stock, for issuing it and reordering.
resistors Low cost metal film 0.25 W – standard preferred values from 1Ω to10
MΩ
High powered resistors 2.5 W silicon coated – standard available
values.
potentiometers 150mW carbon trimmers - standard preferred values from 100Ω to10
MΩ
Light emitting diodes 3mm and 5mm red, orange and green
Other analogue integrated NE555N timer, ICM7555 timer, L7805CP, L7812CP positive voltage
circuits regulators, L7905CT, L7912CT negative voltage regulators
Transformers As required
Lamps and bulbs Low voltage and power selection to meet requirements
Connectors Terminal blocks, 4mm plugs and sockets in red, black, blue yellow
and green
Equipment
In the electronics laboratory each student should have access to the following
equipment. Ideally there should be one set of equipment per student.
1. Multimeter
2. Dual power supply The computer does not
3. Signal generator necessarily form part of the set
4. Dual beam oscilloscope
5. Logic probe
6. Computer
The types of tools and equipment on the market are constantly changing through a
process of continuous improvement. It is strongly recommended that before
purchasing any items for an electronics laboratory advice is sought from a current
user experienced in this area. Issues such as the cost of hand tools in relation to their
quality and life expectancy with inexperienced users who may damage or remove
them from the laboratory have to be given due consideration. Equipment may be
found which is both adequate for the teaching laboratory, student proof and
inexpensive requiring little maintenance.
There are many suppliers of test equipment and tools and those specialising in the
educational market are likely to offer products at an acceptable price. These suppliers
are also likely to have tools and equipment, which can survive the rigours of the
teaching laboratory.
Other centres, which have tried and tested equipment are often the best source of
information and should be consulted as part of the purchasing exercise.
In addition, however, circuit simulation and drawing software may also be used but is
less widely available and more difficult to locate in a form, which is cost effective for
the teaching, laboratory. To meet these criteria the software must be easy to use
without extensive training and be available at low cost with multiple copy site
licensing. The following packages might be considered.
Smart Draw (drawing of diagrams and plans with associated symbol libraries)
Web Site http://www.smartdraw.com
e-mail Sales@ttp.co.uk
Telephone: 01889 564601
Fax 01889 563219
Address The Thompson Partnership, Lion Buildings, Market Place, Uttoxeter, Staffs. ST14 8HZ
Safety
The safety of teaching staff and students working in the electronics laboratory must be
the primary concern of everyone involved.
This has to take precedence over all other activities and be sustained against all
other pressures.
It is beyond the scope of this document to provide details of all aspects of a centre’s
safety policy. Staff must, however, be content that all appropriate safety measures are
in place before embarking on work within the electronics laboratory.
Appendix A
APPENDIX A
CONTENTS
NOTE: these support notes are supplementary to the student support notes and are only
intended for the lecturer/teacher .
Teacher/lecturer notes
When delivering this unit the following approach is recommended to assist in
maximising the students learning experience.
Delivery of Outcome 1
Deliver outcome 1 on number systems using exercises as appropriate but delay the
assessment of this outcome until the practical exercises have been completed. This
allows the students to become familiar with binary numbers and the production of truth
tables. The revision exercise could be used after the practical assessments have been
completed and it could also be marked and retained for grading purposes.
A mixture of 74 series and Cmos IC’s should be used throughout the unit and the
requirements for driving LED’s from the logic chips should also be noted during the
practical exercises. The student is not required to design or wire up the driver circuits
required and therefore they should be provided at all times.
Students should be allowed to work in groups for the earlier practical exercises but
should also produce there own work for the later practical work. A checklist similar to
the one given in the appendix should be used to keep track of the students progress
through the practical work.
N.B. Most tutor kits have the driver circuits incorporated and the student should be
made aware of their purpose. The computer simulation packages on the other hand do
not show any requirement for a driver circuit and this should also be pointed out to the
student.
Irrespective of which practical approach is used the students should also spend some
time using a computer simulation package on logic circuits (electronic workbench,
crocodile clips or other similar packages) The facilities offered by many of these
packages goes well beyond the scope of this unit, but the student should be encouraged
to look at some of these facilities, such as minimisation and construction of circuits
containing only NAND gates.
The remaining outcomes should be assessed in their normal order but should be
arranged later in the unit after all the practical exercises and computer simulations have
been completed (see work schedule). This will allow the student to be extremely
familiar with the concept of logic gates, truth tables and logic problems.
The use of software tutor packages should also be encouraged whenever possible as the
interactive nature of many of them encourage the student to continue studying.
5. Outcome 2 Combinational logic gates, notes including incomplete gate symbols and
truth tables ( computer software tutor packages could be used from this point
to assist with the learning)
8. Outcome 2/3 Practical exercises on logic gates cont’d plus introduction to computer
simulation.
10. Outcome 2/1 Revision of Logic Gates and assessment of number systems
11. Outcome 2/3 Practical assessments starting with assessment on logic gates symbols.
Exercise/tutorial solutions
Exercise 1
Answers
Answers
1 i) 11 ii) 101 iii) 110 iv) 101 v) 1000
vi) 1100 vii) 1110 viii) 10110 ix) 11100 x) 11110
Answers
1 i) 1 ii) 10 iii) 101 iv) 101 v) 100
vi) 1 vii) 1 viii) 10 ix) 1 x) 0
Exercise 4
2. What is the largest decimal positive and negative number possible with:
i) 4-bit binary ii) 8-bit binary
(7, -8) (127, -128)
Exercise 5
Answers
Exercise 6
Answers
Question 1
a) 11 b) 37 c) 125
Question 2
a) 00001101 b) 01110100
c) 00110011 d) 11110001
Question 3
Question 4
b) 11110000 ÷ 10 = 111100
c) 10101011 x 10 = 101010110
Question 5
Question 6
b) 18 0 0010010 0 0010010
+ (-12) 1 0001100 1 1110100
6 1 0 0000110
Extra bit is ignored
d) 41 0 0101001 0 0101001
- 61 1 0111101 1 1000011
-20 1 0010100 1 1101100
No extra bit
1 0 0 1
0 1
1 0 0
> 1
0 1 1
0 1 1
1 0
0
=1 0
0 0
0
1 1
0 1
1
&
0 0
1 1
>
0 0
1
1
Electronic and Electrical Fundamentals: Combinational Logic – Int 2 – Appendix A
12
1
0
0
0
1
1
1
0
>
0 1 0
0
&
1
0
& 1
1
0
0 0
1
1
0
1 0
1
A A.B
B Z =(A.B).C.(A + B)
C
A+B
1 With the aid of a suitable logic tutor board (LT1 Tutorkit) or logic construction
board (limrose deck) Identify and test, with the aid of the logic data sheets
(appendix A), the following logic gates and state the Boolean expression as you
progress.
A B Z A B Z
0 0 0 0 0 0
Z=A+B Z = A.B
0 1 1 0 1 0
1 0 1 1 0 0
1 1 1 1 1 1
A B Z A B Z
0 0 1 0 0 1
Z=A+B Z = A.B
0 1 0 0 1 1
1 0 0 1 0 1
1 1 0 1 1 0
A B Z A Z
0 0 0 0 1
0 1 1 Z=A+B Z=A
1 0
1 0 1
1 1 0
The output to the drill motor should be a logic ‘1’ only when the safety guard is
in place AND the workpiece is in position AND the switch is on.
Safety guard
A
Workpiece
position B
Output to drill
motor
On/ off switch C
Figure 2.1
Construct this circuit with the equipment provided and the test its operation
with the aid of the following truth table (Table 2.1)
INPUTS
Safety guard
A
Workpiece
position B
Output to drill
motor
On/ off switch C
D
Drill in place
Figure 2.2
NB. This is only one possible solution to the problem and the fact that there are other
solutions should be emphasised
Derive the Boolean expression and the truth table for the following logic circuits.
a)
A
B Z =(A + B).(A + C)
A B C A+B A+C (A + B ) . (A + C)
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 1 1 1
1 0 0 1 1 1
1 0 1 1 1 1
1 1 0 1 1 1
1 1 1 1 1 1
b)
A
>
B 1 Z = (A + B) + C
=1
C
A B C A+B C (A + B) + C
0 0 0 1 1 0
0 0 1 1 0 1
0 1 0 1 1 0
0 1 1 1 0 1
1 0 0 1 1 0
1 0 1 1 0 1
1 1 0 0 1 1
1 1 1 0 0 0
A B C A A+B (A + B) + C
0 0 0 1 1 0
0 0 1 1 1 0
0 1 0 1 0 1
0 1 1 1 0 0
1 0 0 0 1 0
1 0 1 0 1 0
1 1 0 0 1 0
1 1 1 0 1 0
A
G1
B
Z=
G3
C G2 Fig 4.6
1. Write the Boolean expression for the circuit shown in figure 4.6
Z = (A.B) + C
BOTH 1
G3 output = 0
A G1
G2 Z=
B G3
Fig 4.7
Z=A+B
5. What is the output expression for the circuit shown in figure 4.7?
Z = (A + B) . B
BOTH = 0
7. Find the output of the circuit shown in figure 4.7 when A = 1 and B = 0?
Z=1
8. Find the output of the circuit shown in figure 4.7 when A = 0 and B = 1?
Z=1
A B A A+B (A + B ) . B
0 0 1 0 1
0 1 1 0 1
1 0 0 1 1
1 1 0 0 1
A
G1
B Z=
G2
C
Fig 4.8
10. Write the output expression for the circuit of figure 4.8
Z=(A+B)+C
0 0 0 0 0
0 0 1 0 1
0 1 0 1 1
0 1 1 1 0
1 0 0 1 1
1 0 1 1 0
1 1 0 1 1
1 1 1 1 0
11. What is the output for the circuit of figure 4.8 when A = 0, B = 1 and C = 1?
12. What is the output for the circuit of figure 4.8 when A = 1, B = 1 and C = 0?
A 0
=1
0 0 >
B G1
1 Z=1
0 1 G3
C
0
&
D G2 Fig 4.9
14. Write the Boolean expression for the output of G1 in figure 4.9
Z=A+B
Z = C.D
16. Write the output expression for the output of G3 in figure 4.9
Z = (A + B) + C.D
17. What is the output of the circuit in figure 4.9 when all four circuit inputs are
equal to 0?
A B C D A+B C.D Z
0 0 0 0 0 1 1
0 0 0 1 0 1 1
0 0 1 0 0 1 1
0 0 1 1 0 0 0
0 1 0 0 1 1 1
0 1 0 1 1 1 1
0 1 1 0 1 1 1
0 1 1 1 1 0 1
1 0 0 0 1 1 1
1 0 0 1 1 1 1
1 0 1 0 1 1 1
1 0 1 1 1 0 1
1 1 0 0 0 1 1
1 1 0 1 0 1 1
1 1 1 0 0 1 1
1 1 1 1 0 0 0
Output is a ‘1’
Output is a ‘1’
20. List the input combinations that will produce an output of logic 0 at gate 3 in
figure 4.9
Z = A.B.C.D + A.B.C.D
22. Given the following truth table, write the corresponding Boolean expression.
0 0 0 0
0 0 1 0 Z = A.B.C + A.B.C + A.B.C
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1 Table 4.22
1 1 1 1
23. Draw the logic circuit for the truth table given in question 21 (Table 4.21)
1 2 1
A 7404 3 Z=A+B
B 2 7408
A B C
1 3
04 04
2 4
1
2 12
11 1
13 32 6
32
2
3 5
4 6
11
5
9
10 8
11
11
For each of the following questions use the IC data sheet provided to produce an
annotated circuit diagram, then produce a truth table for the circuit, finally connect and
test the circuit using the truth table to confirm the operation of the circuit.
1.
A Z=
Solution
1 A Z
A Z=A
IC 3 0 1
7400
2 1 0
A 1 3 Q
4 Z=A
00
2 6
5 00
A Q Z
0 1 0
1 0 1 Z=A
5. Given the Boolean expression Z = A.B + C.D produce the annotated circuit
diagram and truth table then construct and test the circuit.
1
A
08 3
2
B 13
11
32
12
4
C
08 6
5
D
A B C Z
Truth Table
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
7. Draw the logic gate(Ansi symbol) that will give the output Z = A + B + C .
Now draw an annotated logic circuit that can be used to construct a working
circuit to produce the same output. Construct and verify the circuits operation
with the aid of a truth table.
A 1
A Z 3 4
B 2 32 6 1 2 Z
B 32 04
C 5
C
A B C Z
0 0 0 1 Truth table
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
A
3
4 6 3 4
B 11 04 Z
5
C 1 04 2
Truth Table
A B C C A.B.C Z
0 0 0 1 0 1
0 0 1 0 0 1
0 1 0 1 0 1
0 1 1 0 0 1
1 0 0 1 0 1
1 0 1 0 0 1
1 1 0 1 1 0
1 1 1 0 0 1
1
A
3
2 08
B 1 04 2 13
11
12 08
4
C 6
4 5 08
D 3
04
1. A simple logic control for a central heating system has the following inputs
When the output of the control logic = 1 then the gas valve will be opened
allowing the system to produce heat.
Design, construct and test a logic system that will provide frost protection (i.e.
heating on if the temperature falls below 4o C at any time) as well as provide
heating as required by the signals from the clock and thermostat.
But from the question it can be seen that the heating should be on when the Clock AND the
Thermostat are on, OR the Frost protection is on
Z = A.B + C
NOTE:
Although minimising Boolean expression is not part of this course students should be
encouraged to look for the simplest expression from the information given in the question.
Then to prepare a truth table for the circuit they have constructed and how to compare working
table to the theoretical table obtain above. Given that the output of both tables are identical then
the simplified circuit must be correct.
Construct and verify the logic circuit operation using a truth table.
0 0 0 1
0 0 1 1 1
P
0 1 0 1
I 2 10 12
0 1 1 1
13
1 0 0 1
1 0 1 1 3
J
1 1 0 0 4 6
10 Version 1
1 1 1 1 5
P 1 2
04
1
3 4
3 4 2 32 6
I 04 5 32
J Version 2
NOTE: while both version 1 and version 2 will produce the same result it should be
noted that version 1 only requires 1 logic IC and will therefore be easier to construct
and would take up less space on a printed circuit board than version 2.
P W L Z
0 0 0 1 11
P
0 0 1 1 8
10
0 1 0 1 W 10
0 1 1 1 9
L
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Lights on = logic 1
Door open = logic 0
Ignition on = logic 1
L D I Z
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
L 1 2
04
1
3 4
2 32 6
D
5 32
I Version 2
Copyright permission has been granted to use RS Data sheets extracts for the logic
family pin-out diagrams. It is most likely that institutions offering this unit will
already have the appropriate data sheets. However as these diagrams only show the
pin connection for each Integrated Circuit the pinouts required for this unit are given
below but it would be preferable that the student has access to the data sheets at some
time.
1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND
1 2 3 4 5 6 7 5 7
1 2 3 4 6
GND GND
1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND
14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND
CONTENTS
This unit is designed to introduce you to combinational logic gates and circuits as well
as binary and hexidecimal number systems . The main emphasis of the unit will be on
practical work using a selection of logic Integrated Circuits (IC’s) with some computer
simulation packages (Electronic Workbench, Crocodile Clips) used for some exercises.
There will also be a number of written exercises used to reinforce the learning of logic
gates, logic circuits, truth tables and use of Boolean expressions.
There will be two written assessments, outcome 1 and 2(a). The teaching material for
these outcome will be covered at the beginning of the unit but the assessment will be
nearer the end of the unit as continued use of gate symbols and binary numbers will
improve the understanding.
There will be several tutorials/ practical exercises to be worked through before the three
practical assessments (2b, 3, 4) will be covered.
The main part of the Combinational Logic note consists of a handout, which should be
completed as part of the lesson(s) on logic gates. Time taken to do this will be beneficial
later in the unit
If you have or are currently studying the Technological Studies unit in Applied
Electronics you will have had an introduction to logic gates, symbols and truth tables,
and depending on the level being covered you may have some experience of
constructing logic circuits. You will also have covered Binary and Hexadecimal number
systems.
When you have completed this unit you should be able to:
• Manipulate Binary and Hexadecimal numbers
• Recognise and identify common logic gates and symbols
• Use logic diagrams and connect combinational logic circuits
• Design construct and test simple logic circuits
E.g.: In the denary (base 10) system there are ten discrete or separate characters
0-9 in any column.
3 The column at the extreme right i.e. the least significant column, counts units
(= Radix o e.g. 6 = 6 x 10o ).
Each count in the second column to the left equals the base or radix of the
number system (= radix).
Multiplying the value of any column by the base or radix gives the value of the
next most significant column to the left.
E.g.: 60 x 10 = 600
1
I.e.: (6 x 10 ) x 10 = 6 x 102
Binary
In the binary number system the radix is 2 i.e. there are only two discrete characters 0
and 1. The binary system is desirable in digital computers since it is easy to represent
electrically the two character shapes 0 and 1.
In a binary number the columns represent powers of 2. Since only two characters
exist, it follows that a binary number will contain only 0’s and 1’s.
E.g.: 1101 = (1 x 23 ) + (1 x 22 ) + (0 x 21 ) + (1 x 20 )
eights fours twos units
Example
Convert 26 10 to binary:
Result Remainder
26 ÷ 2 = 13 0 --------- LSB
13 ÷ 2 = 6 1
6÷2 = 3 0
3÷2 = 1 1
1÷2 = 0 1 --------- MSB
Conversion
This can be carried out by adding together the values of the powers of 2 present in the
binary number (the presence of a power of 2 is indicated by a 1, and its absence is
indicated by a 0).
Example
Convert 1011012 into denary:
101101 = (1 x 25 ) + (0 x 24 ) + (1 x 23 ) + (1 x 22 ) + (0 x 21 ) + (1 x 20 ) =
4510
Binary Addition
Similarly, for every pair of 1’s in a column (including any carry digits from the
previous column) a carry 1 is added to the next higher value column of digits.
EXAMPLE
00011
01010
00011
+00110
10110
By inspection the least significant columns has an even number of 1’s hence the
corresponding sum digit will be 0. Also, there is one pair of 1’s in this column hence
there is one carry digit to be carried forward to the next column to the left.
Binary subtraction
EXAMPLE
1 10110 2 101011 3 1011000
- 01001 -010110 -0101111
01101 010101 0101001
NB: When borrowing a 1 from the 21 column to allow the subtraction of the two
figures in column 1, we actually borrow 1 + 1. If we take 1 away.
1 + 1 – 1 = 1 as above
When signed numbers are being used, therefore, the largest number available (in an
8 bit
Word) is 0111 11112 or 12710 .
NB: The MSB is not included in calculations other than to indicate the sign + or -.
There are three basic ways of representing negative number in binary form:
True-Magnitude Form
1’s Complement Form
2’s Complement Form.
The first two will only be mentioned briefly, as the 2’s complement form is the
method, which we will be using.
True-Magnitude Form
True-magnitude form is simply the representation as shown below, where the true-
magnitude of the number is given in binary form. The first bit is always the sign bit,
a 0 representing a positive number and a 1 representing a negative number.
E.g.: 0 1 1 0 1 0 0 = +5210
Sign bits
1 0 1 1 1 1 1 = -3110
When negative numbers are represented in 1’s complement form, the sign-bit is
made a 1 and its magnitude is converted from true binary form to its 1’s
complement form.
E.g.: Sign Bits
Note that the signbit is not complemented but is kept as a 1 to indicate a negative
number.
2’s Complement Form
The 1’s complement and the 2’s complement systems are very similar, but the 2’s
complement system is generally in use because of several advantages it has in
circuit implementation. We will now investigate how the operation of addition and
subtraction are performed in digital machines that use the 2’s complement
representation of negative numbers.
Taking the 1’s complement of the number and adding 1 to the least significant bit
position forms the 2’s complement form of a binary number. The procedure is
illustrated below for converting –57 to 2’s complement.
E.g.: Sign-bits
+ 9 0 1001
+ 4 0 0100
+13 0 1101
Sign-bit
NB: The sign-bit of the augend and addend are both 0 and the sign-bit of the sum is
0, indicating that the sum is positive. Also note that, the augend and addend are
made to have the same number of bits. This must always be done in 2’s
complement.
+9 01001
-4 11100
+5 100101
disregard carry
In computer systems all negative numbers are given their 2’s complement form. If, for
example, a 4 bit word were being used, bit 3 (the MSB) is the sign-bit. If the MSB is
zero then the number is positive and ordinary binary weighting can be applied to
convert bits 0, 1 and 2 to decimal.
If the MSB is 1 then the number is negative and the 2’s complement must be taken of
bits 0-2 to find the equivalent negative number, which can be converted to decimal if
required using normal binary weighting.
It is, therefore, essential to know whether the binary system you are using utilises
signed or unsigned numbers.
+9 0 1001
-4 1 1100
+5 1 0 0101
00101 (+5)
-9 10111
+4 00100
-5 11011
NEGATIVE SIGN-BIT
The sum here has a negative sign-bit. Since the sum is negative it is in 2’s complement
form and the last 4 bits represent the 2’s complement of the sum. To change the 2’s
complement to true binary, simply complement each bit and then add 1 to the LSB.
-9 10111
-4 11100
-13 110011
SIGN-BIT
disregard the carry
E.g.: 27 = 00011011
54 = 00110110
108 = 01101100
It must be noted that a zero enters the empty space.
Shift the original number one place to the left then add the original number to the result.
54 - 00110110
x3 x2 shift left
01101100
00110110 + original
= 162 10100010
Continual division by two is possible by shifting to the right, but this will only be valid
provided there is a zero in the least significant bit position.
Example
24010 divided by 410
Note that each hexadecimal (or hex for short) digit represents a group of 4 binary digits.
Many computers utilise the hex system, rather than octal, to represent large binary
numbers. The conversion between hex and binary is done in exactly the same way as
octal and binary except that groups of four bits are used.
2AE16 = 68610
Decimal to hex is done by repeated division by 16. The remainder are then read in
reverse order to give the hex number.
so 135210 = 5 4 816
To convert from a binary number to a hex number, divide the digits in the binary
number into groups of 4, starting from the right (LSB). Convert each group into its
equivalent hex symbol.
9 F
So 100111112 = 9F16
To convert from a hex number to a binary number, its equivalent group of 4 binary
digits replaces each hex symbol.
E.g. B1F B 1 F
so B1F16 = 1011000111112
Exercise 1
i) 10 ii) 15 iii) 16
vii) 59 viii) 85 ix) 90
x) 99 xi) 120 xii) 127
xiii) 128 xiv) 255 xv) 3843
Exercise 2
1. Add the following binary numbers:
Exercise 3
1. Perform the following binary subtractions:
Exercise 4
1 What is the 2’s complement representation of the following in 8-bit binary?
a) -32 b) 41
c) 62 d) -121
e) -17 f) 120
g) -120 h) -3
i) 100 j) 0
2. What is the largest decimal positive and negative number possible with:
4. Do the following calculations using the 2’s complement notation? Show all
working:
Exercise 5
Exercise 6
Question 1
Convert the following decimal numbers into binary:
a) 11 b) 37 c) 125
Question 2
Convert the following binary numbers into decimal:
a) 00001101 b) 01110100
Ans. Ans.
c) 00110011 d) 11110001
Ans. Ans.
Question 3
Add the following binary numbers:
Question 4
Use arithmetic shift methods to complete the following:
a) 10101100 x 100 =
b) 11110000 ÷ 10 =
c) 10101011 x 10 =
Question 5
Convert the following into 2’s complement:
a) -121
b) -74
c) -10
Question 6
Calculate the following using the 2’s complement method. All working must be shown.
a) 27 - 13
b) 18 + (-12)
c) -17 + (-18)
d) 41 - 61
Combinational logic is also used as part of traffic light control. Two inputs
applied to a circuit, can produce four combinations i.e. RED, RED with
AMBER, GREEN and AMBER.
Combinational
A Logic
circuit
B
0V
The traffic light sequence shown above can be expressed in the form of a “Truth
Table” which lists all the possible combinations of the inputs and outputs.
Truth table
INPUTS OUTPUTS
KEY
A B RED AMBER GREEN 0 = Off
0 0 1 0 0 1 = On
0 1 1 1 0
1 0 0 0 1
1 1 0 1 0
Digital circuits and devices operate in the binary number system: that is all
circuit variables are either 0 or 1 ( Low or High) ( Off or On). The diagram
shown in figure 2 shows a logic circuit with two binary inputs A and B. The
combinations the two binary inputs can have are shown in the input chart
(table1). It can be seen that the combination forms the binary counting sequence
(0 to 3) for a two column binary number
Figure2
A Logic Output
Inputs
Circuit
B Z = f (A, B)
Input chart
No. A B
0 0 0 All possible
Table 1 1 0 1 combinations
2 1 0
3 1 1
n
The possible number of input combinations is given by 2 where the radix or
base of 2 is chosen since the system is binary, and n is the number of input
variables.
Output combinations
The possible number of output combinations for the two input logic circuit in
figure 2 is 16 and can be calculated by 2m where the radix 2 is chosen since the
system is binary and m is the number of combinations of the two input variables
(A,B)
Hence No. of combinations of two inputs m = 2m = 4
Output combinations = 24 = 16
All the possible output combinations are shown in the following table 2
INPUTS OUTPUTS
Table2
Only six of these output combinations are of any logical significance and these
are indicated by bold type in table 2
AND function
Output Z = A AND B
The table 3 below shows the input chart for the two variables along with the
output combination for the AND function, and the table is termed a truth table
for the AND function.
A B Z
Truth table for
0 0 0
a two input
0 1 0
AND gate
1 0 0
1 1 1
Table3
5V A B 0V
Figure3
A A
Z = A.B Z = A.B
B & B
BS EN 60617 ANSI
Exercise1 draw the truth table and BS EN symbol for a three input AND gate.
A B C Z
INCLUSIVE OR function
This is more commonly known as the OR function with the “inclusive” omitted.
Output Z = A OR B
it is normally written as Z = A + B
A B Z
Truth table for a
0 0 0
two input OR
0 1 1
gate
1 0 1
1 1 1
Table 4
5V A 0V
B
Figure4
A A
Z=A+B Z=A+B
>
B 1 B
BS EN ANSI
60617
Exercise 2. Draw the truth table and ANSI symbol for a three input OR gate
Table Symbol
EXCLUSIVE - OR function
Output Z = A EXCLUSIVE – OR B
0V
5V A=0
B=0
Figure5
A A
Z=A+B Z=A+B
B =1 B
BS EN 60617 ANSI
NB. An exclusive-or gate with more than two inputs, gives a logic 1 when there
are an odd number of logic 1’s present at the input.
Exercise 3 draw the truth table and BS EN symbol for a three input
EXCLUSIVE-OR gate.
Table Symbol
B
Z=A+B+C
C
Exercise 4
a) Draw a circuit diagram for a four input EXCLUSIVE-OR gate using three (2
input) EXCLUSIVE-OR gates
b) Draw a truth table for this function.
Exercise 4 answer
a)
b)
The overbar represents the NOT operation i.e. Z = A. thus the expression is read
as Z = NOT A. The NOT operation is often referred to as an inversion or
complement.
A Z=A
Presence of small
circle always
denotes inversion
NAND function
Output Z = NOT A and B
A B Z
Truth table for NAND gate
0 0 1
0 1 1
1 0 1
1 1 0
A A
Z = A.B Z = A.B
B & B
BS EN 60617 ANSI
The small circle at the end of the AND gate indicates inversion.
This gate can also be extended to n number of inputs.
Exercise 5 draw a truth table and BS EN symbol for a three input NAND gate.
Table Symbol
NOR function
The output Z =NOT A or B
A B Z
A A
Z=A+B
> Z=A+B
B 1 B
BS EN ANSI
60617
Exercise 5 draw a truth table and ANSI symbol for a three input NOR gate
Table Symbol
A B Z
A A
Z=A+B Z=A+B
B =1 B
BS EN 60617 ANSI
Summary
Logic gates are switching circuits in which the state of the output at any instant
in time depends on the present state of all the inputs (usually there is more than
one) . They ‘open’ and give a ‘high’ output only for certain input combinations.
There are several types, the behaviour of each type is described by a truth table
showing the output for all possible input combinations. In the table the ‘high and
‘low’ states, i.e. near 5V and near 0V, are represented by 1 and 0 respectively
and are referred to as logic 1 and logic 0
Or alternatively you may find it easier to remember the truth tables for the OR,
AND and EXOR gates then the rest can be found by inverting the outputs
A B Z Z Z Z Z Z
0 0 0 1 0 1 0 1
0 1 0 1 1 0 1 0
1 0 0 1 1 0 1 0
1 1 1 0 1 0 0 1
1 0
0 1
1
> 1
0 1 1
0 1
1
0
=1 0
1
0 1
0
0 1
1
&
0 0
>
0 0 1
1
1
>
0 1
0
&
1
0
&
1
B Z=
C
1 With the aid of a suitable logic tutor board (LT1 Tutorkit) or logic construction
board (limrose deck) Identify and test, with the aid of the logic data sheets
(appendix A), the following logic gates and state the Boolean expression as you
progress.
A B Z A B Z
0 0 0 0
Z = ………. Z = ……….
0 1 0 1
1 0 1 0
1 1 1 1
A B Z A B Z
0 0 0 0
Z = ………. Z = ……….
0 1 0 1
1 0 1 0
1 1 1 1
A B Z A Z
0 0 0
Z = ………. Z = ……….
0 1 1
1 0
1 1
The diagram below (figure 2.1) illustrates how various combinational logic
gates can be connected together to act as a simple drilling system with a safety
guard. This particular arrangement has 3 inputs (safety guard check, workpiece
in position and an on/off switch) and one output to drive the drill motor.
The output to the drill motor should be a logic ‘1’ only when the safety guard is
in place AND the workpiece is in position AND the switch is on.
Safety guard
A
Workpiece
position B
Output to drill
motor
On/ off switch C
Figure 2.1
Construct this circuit with the equipment provided and the test its operation
with the aid of the following truth table (Table 2.1)
INPUTS
Draw a modified circuit diagram to show how the system could be altered to
allow the use of a fourth input which would check if a drill was in the drilling
machine (i.e. if drill is present then 4th input = logic ‘1’.
Logic gates and their Boolean expressions have already been examined as
individual gates, but as practical electronic circuits will contain a number of
different gates, it is important to be able to use Boolean algebra to determine a
circuit’s output. Circuits using these gates will be used to demonstrate how a
logic circuit can be represented as a mathematical expression. The seven logic
gates and their output expressions are summarised in Table 4.1
Given a combinational logic circuit it is useful to determine the Boolean
expression in order to understand what is occurring within the circuit. Once the
mathematical equivalent of the circuit is derived, a truth table to assist in trouble
shooting can be developed. Methods used for simplifying these expressions will
be examined in a later unit.
LOGIC SYMBOL FUNCTION INPUT/ OUTPUT THE EXPRESSION
EXPRESSION INDICATES
A Z is a 1 When both A
Z AND Z = A.B
B AND B are equal to 1
A
Z is a 1 when
B Z OR Z=A+B A OR B is equal to 1
Z is a 1 when A AND/
A
B Z NAND Z = A.B OR B is a 0
Z is a 1 when both A
A
Z NOR Z = A+B AND B are equal to 0
B
Z is a 1 when A OR B
A
Z EXCLUSIVE -OR Z=A+B (but not both) equal 1
B
Z is a 1 when A and B
A
B Z EXCLUSIVE-NOR Z=A+B are equal
As a general rule the process to write the Boolean expression for a simple circuit
is as follows:
• Determine the point at which the circuit has to be evaluated.
• Move back into the circuit to the first gate or gates. Referring to the table 4.1
write the expression for the input and output for each gate. Build up the final
expression as each gate is considered.
• Construct the circuit truth table by substituting 1’s and 0’s into the expression.
A
B 1
3 Z
C
D 2 Fig 4.1
These expressions can then be entered into the circuit diagram as shown in figure
4.2
A
B 1 A.B
3 Z
C C.D
D 2
Fig 4.2
The final gate, gate 3 is an OR gate with the expression written in the format
Z = input 1 OR input 2. Entering the expressions derived above, in place of input
1 and input 2, the final expression becomes: as illustrated in fig 4.3
Z = A.B + C.D
A
B 1
3 Z = A.B + C.D
C
D 2
Fig 4.3
The truth table for the circuit can now be derived using the following method:
• Produce an input chart for the 4 inputs.
• Enter the outputs achieved for the intermediate steps (gates 1 and 2).
• Enter the final output (gate 3)
2. Derive the Boolean expression and truth table for the circuit shown in fig 4.4
A >
1
B
C
& Fig 4.4
The output of the OR gate is A + B. then this gives the output of the second gate
which will now be gate 1 AND C, which gives Z = (A + B). C. This is shown
below in figure 4.5
A > A+B
1
B
& Z = (A + B) .
C
C
Fig 4.5
0 0 0 0 0
0 0 1 0 0
0 1 0 1 0
0 1 1 1 1
1 0 0 1 0
1 0 1 1 1
1 1 0 1 0
1 1 1 1 1
Table 4.1
B
Z=
b)
A
>
B 1 Z=
=1
C
B
Z=
d)
A
Z=
A
G1
B
Z=
G3
C G2 Fig 4.6
1. Write the Boolean expression for the circuit shown in figure 4.6
A G1
G2 Z=
B G3
Fig 4.7
5. What is the output expression for the circuit shown in figure 4.7?
7. Find the output of the circuit shown in figure 4.7 when A = 1 and B = 0?
8. Find the output of the circuit shown in figure 4.7 when A = 0 and B = 1?
A
G1
B Z=
G2
C
Fig 4.8
10. Write the output expression for the circuit of figure 4.8
11. What is the output for the circuit of figure 4.8 when A = 0, B = 1 and C = 1?
12. What is the output for the circuit of figure 4.8 when A = 1, B = 1 and C = 0?
A
=1
>
B G1
1 Z=
G3
C
&
D G2 Fig 4.9
14. Write the Boolean expression for the output of G1 in figure 4.9
15. Write the Boolean expression for the output of G2 in figure 4.9
16. Write the output expression for the output of G3 in figure 4.9
17. What is the output of the circuit in figure 4.9 when all four circuit inputs are
equal to 0?
20. List the input combinations that will produce an output of logic 0 at gate 3 in
figure 4.9
21. Given the following truth table, write the corresponding Boolean expression.
0 0 0
0 1 1
1 0 0
1 1 0 Table 4.21
22. Given the following truth table, write the corresponding Boolean expression.
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1 Table 4.22
1 1 1 1
23. Draw the logic circuit for the truth table given in question 21 (Table 4.21)
24. Draw the logic circuit for the truth table given in question 22 (Table 4.22)
1. State the type of logic gate that would give the truth table shown in figure1.
INPUTS OUTPUTS
A B Z
0 0 0 Fig 1
0 1 0
1 0 0
1 1 1
2. Draw the logic symbol for a 2 input NAND gate using BS-EN symbols.
A
>
B
1 Fig 2
C
Z = ……………………………..
5. Show how the NOT function can be achieved using a three input NAND gate.
Introduction
The Limrose unit is a quick and easy method of constructing and testing a
wide range of digital electronic circuits (without the aid of solder). The units
have a built in power supply (0V and 5V) which is protected against short
circuits. There is also a clock circuit with a fast and slow setting, and 10
buffered LED outputs (One LED may be converted to act as an off/on
indicator by connecting it to the 5V line).
Layout
External
CLOCK inputs
Fast Slow
Mains
On/off
Manual
clock
LED’s
“0” “1”
“0” “1” IC sockets
“0” “1”
“0” “1”
“0” “1”
The basic layout of the unit is as shown above. Connections are made between
the various parts of the unit using coloured leads (each colour is a different
length) which have push fit connectors fitted to the end. These connectors fit on
to the short pins which are fixed on the board. White lines are drawn between
pins which are connected together and there are groups of four pins at the top
and bottom of the board to allow ‘multi-way’ connections.
Power connections are provided above and below the centre rows of IC sockets
and connections must be made to the appropriate pins on the IC +5V(Vcc) and
0V (GND).
IC Sockets
1 14 1 16
2 13 2 15
3 12 3 14
4 11 4 13
5 10 5 12
6 9 6 11
7 8 7 10
N.C N.C 8 9
. .
Input switches
Input signals to the IC’s are provided using a range of switches situated on the
left hand side of the Limrose unit. S1 (press for logic “1”) gives a “clean”
output and is suitable for a manual clock input signal. S2 to S6 are used to
provide all the other input signal required.
Outputs
The final outputs from the constructed logic circuits should be connected to the
RED LED’s on the right hand side of the unit. These LED’s indicate a logic “1”
(LED on) and a logic “0” (LED off). L1 should be connected to the 5V line to
provided a power ‘ON’ indicator which will indicate that the unit is powered on
properly. If this LED fails to light consult your class Teacher/ Lecturer.
Clock
The on board clock provides square wave pulses, at slow approximately 2Hz
and fast approximately 500Hz, selected by a toggle switch.
For each of the following questions use the IC data sheet provided to produce
an annotated circuit diagram, then produce a truth table for the circuit, finally
connect and test the circuit using the truth table to confirm the operation of the
circuit.
1.
A Z=
Solution
1 A Z
A Z=A
IC 3 0 1
7400
2 1 0
A Q
Z=
A Q Z
0
1 Z=
A B C A C A.B.C Z
5. Given the Boolean expression Z = A.B + C.D produce the annotated circuit
diagram and truth table then construct and test the circuit.
Truth Table
7. Draw the logic gate(Ansi symbol) that will give the output Z = A + B + C .
Now draw an annotated logic circuit that can be used to construct a working
circuit to produce the same output. Construct and verify the circuits operation
with the aid of a truth table.
Truth table
Truth Table
Truth
table
1. A simple logic control for a central heating system has the following inputs
When the output of the control logic = 1 then the gas valve will be opened
allowing the system to produce heat.
Design, construct and test a logic system that will provide frost protection (i.e.
heating on if the temperature falls below 4o C at any time) as well as provide
heating as required by the signals from the clock and thermostat.
Construct and verify the logic circuit operation using a truth table.
Lights on = logic 1
Door open = logic 0
Ignition on = logic 1
In order to fault find on any of the logic circuits used in this unit it is
necessary to have the annotated circuit diagram and a truth table available
before checking the circuit.
The first test that should be carried out is a visual inspection which involves
observing the symptoms as well as checking for missing or loose connections.
The observation will consist of two checks, i) is the output on or off at all
times, and ii) is the output sequence comparable to the circuit truth table.
The second check involves the use of the circuit diagram and the circuit
connections must now be compared to the annotated diagram to check for any
errors in the wiring.
N.B. it is important to check that the Logic IC’s being used have had the
power connections made. For all the IC’s used in this unit this means 5
Volts to PIN 14 and 0 Volts to PIN 7
Common faults on logic circuits include faulty gates which give continuous
logic 0 or logic 1or gates having a fault on an input line or a gate not
following its truth table.
Professional logic probe are available to test TTL and Cmos logic IC’s where
a green LED indicates a logic 0 and a red LED indicates a logic 1. Logic
probes often have a ‘pulse stretching’ facility which allows a pulse of very
short duration (30 - 50 ns) to cause the LED’s to blink long enough for the eye
to see. Also when the pin being tested has a continuous pulse wave form
present then both leds will light but not as brightly as a logic 0 or 1, this will
vary depending on the type of probe ( see manufacturers data sheet for more
information) .
When one of the common faults mentioned above occurs, a logic pulsar can
be used to inject a test signal into any appropriate part of the circuit. This test
signal is capable of overriding the logic level present at that point in the
circuit therefore it can be used to indicate, along with a suitable probe, which
parts of a circuit are responding to logic signals and which are not.
Copyright permission has been granted to use RS Data sheets extracts for
the logic family pin-out diagrams. It is most likely that institutions offering
this unit will already have the appropriate data sheets. However as these
diagrams only show the pin connection for each Integrated Circuit the
pinouts required for this unit are given below but it would be preferable that
the student has access to the data sheets at some time.
1 2 3 4 5 6 7 1 2 3 4 5 6 7
GN GN
D D
1 2 3 4 5 6 7 5 7
1 2 3 4 6
GN GN
D D
1 2 3 4 5 6 7 1 2 3 4 5 6 7
GN GN
D D
14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7
GN GN
D D
Se poate face in :
Scopul este de a aduce valoarea variabilei x, cat mai aproape de valoarea variabilei
de referinta w, indiferent de influentele pe care le exercita alte variabile exterioare
(perturbatoare) ( Z1n aupra sistemului de control sau Z2n asupra sistemului controlat ).
Z1n Z2n
SISTEM DE CONTROL
w UNITATE ELEMENT DE y SISTEM x
DE CONTROL EXECU ŢIE CONTROLAT
Circuitul tine cont atit de factorul perturbator Z1 cat si de factorul perturbator Z2, in
sensul reducerii influentelor acestora ( la contr. in bucla deschisa nu se tine cont de Z2)
Control in bucla deschisa : proces prin care una sau mai multe var de intrare (w1)
sunt utilizate pentru reglarea uneia sau a mai multor variabile de iesire (x1)
Z1 Z2n
SISTEM DE CONTROL
wn UNITATE ELEMENT DE yn SISTEM xn
DE CONTROL EXECUŢIE CONTROLAT
Z1 Z2
n n
w w* y* y x
B A
D
μ C D
A E S
T x*
D B M
A
T
Unde :
1 3 8
6 10
9
2 3 4 5 7
9
Semnale
Acestea sunt furnizate de comutatoare de pozitie sau de traductoare ( ex. de tip Hall)
Tensiunea poate varia de la cativa mV pina la valoarea tensiunii furnizate de
instalatia electrica a automobilului ( 14V ).
Prelucrarea semnalelor
Semnale de iesire
Sunt obtinute (realizate) cu ajutorul unor comutatoare de putere sau a unor circuite
de amplificare, ce amplifica semnalul de iesire dat de microcalculator ( U = 0 - 5V si
intensitatea de ordinul mA ) la niveluri corespunzatoare pentru comanda elementelor de
executie ( tensiunea pina la cea din sistemul electric al automobilului, 14V sau 28V si
intesitatea de ordinul A).
MICROCALCULATOR
CEAS
MAGISTRALĂ DE DATE 4, 8, 32 biţi
INTERN
(OSCILATOR)
- Altele :
o Controler de magistrala
o Porturi
o Convertoare
o Baze de timp
La ora actuala solutia cea mai raspandita o reprezinta conectarea prin intermediul
unui sistem de magistrala seriala de date, cunoscuta sub numele de CAN (controller
area network)
3 1 1 1
2 2 2
A
2
1 1 1
2 2 2
B
2
1 1 1
2 2 2
C
2
Expresiile utilizate nu sunt insa in sistem decimal ci in sistem binar. In situatia in care
se utilizeaza si numere negative in sist. decimal ( -4, -3, -2, -1) atunci primul bit al
expresiei digitale va reflecta semnul expresiei astfel: cifra 1 va introduce valoarea
negativa iar cifra 0, valoarea pozitiva. Prin urmare, un cuvint de 3 biti va putea exprima
numere intregi cuprinse intre -4 si +3.
100 = (-1)*22 + 0*21 + 0*20 = -4
011 = 0*22 + 1*21 + 1*20 = 3
101 = (-1)*22 + 0*21 + 1*20 = -3