eee Concurrent assertions check the sequence of events spread over multiple clock cycles. + Concurrent assertion is evaluated only at the occurrence of a clock tick. + Test expression is evaluated at clock edges based on the sampled values of the variables Involved. + Can be placed in a procedural block, a module, an interface or a program definition. assert: assert property(@(posedge clk) not(a && b))5 The Keyword differentiates the immediate assertion from the concurrent assertion is "property."sequence seq @lposecge clk) a #42 d; endsequence In the above sequence we can observe that, sequence starts on every postive edge of the clock ard it looks for “a" lo be high on every posilive clock edge, \f signal “a” fs nol high on any given postive clock edge, an error is issued by the checker. If we want sequence to te checked only after “a” Is high, this can achieved by using Implication operator. implication 's equivalent to an if-then stucture. The left hand side of the implication is called the "antecedent’ and the right hand side is called the ‘consecuent The antececent is the gating condition. IF the antecedent suozeeds, then the consequent is evalueted The implication constuct can be used only with property definitors. It cannot be used in sequences. There are 2 types of implication: + Overlapped implication + Nemoverlapped implicationOna Overtapped implication is denoted by the symbol |->. If there is a match on the antecedent, then the consequent expression is evaluated in the same clock oycle. Below property checks that, if signal "a" is high on a given positive clock edge, then signal "b" should also be high on the same clock edge. property p5 @(posedge clk) a |-> bs endproperty a: assert property(p);RET n Non-Overiapped implication is denoted by the symbol |=>. if there is a match on the antecedent, then the consequent expression is evaluated in the next clock cycle. Below property checks that, if signal "a’ is high on a given positive clock edge, then signal "b" should be high on the next clock edge. property ps @(posedge clk) a [=> bs endproperty a: assert property(p);a fixed delay on the consequent : Below property checks that, if signal "a" is high on a given positive clock edge, then signal "b" should be high after 2 clock cycles. property ps @(posedge clk) a |-> ##2 bs endproperty a: assert property(p);Implication with a sequence as an antecedent ; Below property checks that, if the sequence seq_1 is true on a given positive edge of the clock, then starts checking the seq_2 ("d” should be low, 2 clock cycles after seq_1 is true ). sequence seq_1s (a 8& b) ##1 C5 endsequence sequence seq_23 #2 Nd3 endsequence property pj @(posedge clk) seq_a |-> seq_2s endpeoperty a: assert property(p);Timing windows in SVA Checker Below property checks that, if signal "a" Is high on a given positive clock edge, then within 1 to 4 clock cycles, the signal "b" should be high. property p3 @(posedge clk) a |-> ##[1:4] bs endproperty a: assert praperty(p);Overlapping timing window: Below property checks that, if signal "a" is high on a given positive clock edge,then signal "b" should be high in the same clock cycle or within 4 clock cycles. property pj @(posedge clk) a |-> ##[0:4] bs endproperty a: assert property(p)sIndefinite timing window: The upper limit of the timing window specified in the right hand side can be defined with a *$” sign which implies that there is no upper bound for timing. This is called the "eventuality" operator. The checker will keep checking for a match until the end of simulation, Below property checks that, if signal "a" is high on a given positive clock edge, then signal "b" will be high eventually starting from the next clock cycle. property p3 @(posedge clk) a |-> ##[1:$] b; endproperty a: assert property(p);Properties and Sequences Q Example with property property not_read_and_write; not (Read && Write}; endproperty assert property (not_read_and_write) ; Q Example with Sequence sequence request Req; endsequence sequence acknowledge ##[1:2] Ack; endsequence property handshake; @(posedge Clock) request |-> acknowledge; endproperty assert property (handshake) ;Different Operator with Sequences Q The ## operator delays execution by the specified number of clocking events, or clock cycles a ##1 b “ uw a ##N b “s a ##[1:4] b “ “vs uy a must be true on the current clock tick and b on the next clock tick Check b on the Nth clock tick after a a must be true on the current clock tick and b on some clock tick between the first and fourth after the current clock tick Q The * operator is used to specify a consecutive repetition of the left-hand side operand. a ##1 b [*3] ##1 (a #82 b) [#2] (a ##2 b) [#123] uw uw iW 7A Ww Equiv. to Equiv. to Equiv. to or (a ##2 or (a ##2 a ##1 b ##1 b ##1 b ##1c (a ##2 b ##1 a ##2 b) (a ##2 b) b ##1 a ##2 b) b ##1 a ##2 b ##1 a ##2 b)Different Operator with Sequences Q_ The $ operator can be used to extend a time window to a finite, but unbounded range. a #1 b [*i:$] Hic //E.g. abbbbec Q > The [-> or goto repetition operator specifies a non- consecutive sequence. a ##1 b[->1:3] ##1¢ // E.g. a !bbb !b!bbe QO The [= or non-consecutive repetition operator is similar to goto repetition, but the expression (b in this example) need not be true in the clock cycle before c is true a ##1 b [=1:3] #41 ¢ // E.g. a [bbb !b !bb tb tbeEo! property p3 @(oosedge clk) a |-> #1 b #H1 b HHI bs endpronety a: assert property(p}5 The above property checks that, it the signal “a” is high on given posedge of clock, then signal "b” should be high for’3 consecutive clack cycles. The Consecutive repetition operator is used to specify that a signal or a sequence will match continuously for the number of clocks specified. Syntax signal ['n] or sequence [9] Is the number of repetitions.with repetition operator above sequence can be re-written as, property p3; @(posedge clk) a |-> ##1 b[*3]; endproperty a: assert property(p);The go-to repetition operator is used to specify that a signal will match the number of times specified not necessarily on continuous clock cycles. Signal [>n] property p5 @(posedge clk) a |-> ##1 b[->3] ##1 c; endproperty a: assert property(p)5 the above property checks that, if the signal “a” is high on given posedge of clock, then signal “b” should be high for 3 clock cycles followed by “” should be high after “b” is high for third time. This Is very similar to "go to” repetition except that it does not require that the last match on the signal repetition happen in the clock cycle before the end the entire sequence matching. Signal [=n] ‘Only expressions are allowed to repeat in "go to" and "nonconsecutive" repetitions. Sequences are not allowed,