CAIRO UNIVERSITY Elective Course :VLSI Design

FACULTY OF ENGINEERING Dr. Serag Eldin Habib

Electronics and Communications. DEPT., Fouth Year, Fall 2006
Final Project

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Introduction :
In Prob. Set 2 of this course, you developed a library of primitive gates using the
standard cell layout approach. This cell library is based on the scalable N well
CMOS process. This library is hence fourth named CUSCLIB1 ( Cairo
University Standard Cell LIBrary 1). The aim of the final project of the course is
to further use this standard cell library. Each student shall:

™ Use his/her cell together with CUSCLIB1 cells to build a circuit of his/her
choice (hence named Mycircuit) using the standard cell approach. The
number of cells used in Mycircuit should be at least four cells.

Project Inputs
™ CUSCLIB1 cell library
™ N well process description and design rules

Standard cell specifications

The standard cells should satisfy the same guidelines given in Prob. Set 2.
These guidelines are duplicated below for ease of reference. :
i ) Cell height 40 λ
ii ) VDD runs on a 5λ strip of Metal 1 located at height 34.5 λ to 39.5 λ
iii ) GND runs on a 5λ strip of Metal 1 located at height 0.5 λ to 5.5 λ
iv ) Inputs and outputs of each cell are available via vertical Metal 2
wires as shown in Fig. 1

Strict adherence to these guidelines should be observed. Any deviation

from these rules would simply lead to the rejection of your design.
 VDD

I/O ports GND

for cell
Fig. 1

Project Outputs Each student should submit a report organized as follows :

1. Abstract

2. One page summary of Mycell specifications. These specifications include

Truth Table, Symbol, Pin Capacitance, cell area, power dissipation, and
delays. This specification should take the format given below.

3. Block diagram of Mycircuit showing how the Mycell and the other used
standard cells are connected.

4. CIF file that builds Mycircuit layout by instantating the CIF files of the
standard cells used Mycircuit.

5. One page summary of Mycircuit specifications. These specifications are

similar to Mycell specifications.

6. SPICE simulation of Mycircuit.

The output of this project should be submitted to Eng. Mohammed Khairy in

Electronic form no later than Thursday Feb 15, 2007.
 Template for Mycell specification
Asssume VDD = 3.3, and Cload = 150 fF

Cell Name
Truth Table Symbol Pin Capacitance

A B C F Pin Cap[pf]
A
B
C

Size µm2

Static power dissipation µWatt/ MHz

Propagation delays

Rise Fall
LH transition HL transition
Input Slope [ns] 0.05 2 0.05 2
Delay A =>F
Delay B=>F
Delay C =>F