Boolean Expresions and Truth Tables figisemaeee Boolean Operations and Expressions Laws and Rules of Boolean Algebra Kamaugh Mop SOP Minimization DeMorgon’s Theorems Kenaugh Map POS Minimisation Boolean Analysis of Logic Circuits Five-Variable Kamaugh Maps ‘Simplification Using Boolean Algebra VHDL (optional) [EE Digital system Application Standard Forms of Boolean Expressions1 Apply the basi aus and rules of Boolean algebra Apply DeMorgan’s theorems to Boolean expresions Describe gate networks with Boolean expreions 1 Evaluate Boolean expresions Simplify exprewsions by using the lows and rules of Boolean algebra = Convert any Boolean expression into a sum-of-products (SOP) form Convert any Boolean expression into a product of-sums (POS) form % Use a Kanaugh map to simply Boolean expresions = Use a Karnaugh mop to simplify truth table fonctions © Ustize "don't car” conditions to simply logic functions |= White 3 VHDL. program for mpl logic “= Apply Boolean algebra, the Karnaugh map method, and VHDL to. gstem application Coa Variable Product-of-sums (POS) Complement Karnaugh map ‘Sum term Minimization Product term “Don't care” Sum-of-products (SOP) VHDL INTRODUCTION In 1854, George Boole published a work titled An Investigation of the Laws of Thought, on Which Are Founded the Mathematical Theories of Logic and Probabilities. It was in ths publication thata "logical algebra,” known today as Boolean algebra, was formulated. Boolean algebra isa convenient and sptematic way of expresing and analyzing the operation of logic circuits. Claude Shannon was the fist ‘to apply Boole’s work to the analysis and design of logic creut In 1938, Shannon wrote a thesis at MIT tiled A Symbolic Analyis of Relay and Switching Circuits This chapter covers the laws, rules, nd theorems of Boolean algebra and their application to digital circuits. You will earn how to define a given circuit wth a Boolean ‘expresion and then evaluate is operation. You wil ako learn how to simplify logic circuits using the methods of Boolean algebra and Karnaugh maps The hardware description language VHDL for programming logic devices is introduced. PE The Digital System Application illustrates concepts taught in this chapter. The 7-segment display logic in the tablet ‘counting and control system from Chapter | ie good way to illustrate the application of Boolean algebra and the Karnaugh map method to obtain the simplest possible {implementation in the design of logic circuits, Therefore, in this digital system application, the focus ison the BCD to T-segment logic that drives the two system displays shown in Figure 1-58. Study aids for this chapter are available at http: ww prenhall.com/floyd 183184 = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION [BTM BOOLEAN OPERATIONS AND EXPRESSIONS es Ina microprocesr, the ithmetic logic unit (ALU) perfooms arithmetic and Boolean logic operations on digital data as, directed by program instructions. Logical operation: are equivalent tothe basic gate operations that | you ace famine with but deal with |G minimum of 8 bit ata time, amples of Boolean logic | nsbuctions are AND, OR, NOT, | and XOR, which are called | mnemonics, An asembly language program wes the mnemonics to “specify an operation, Another | progam called an asembler tramlates the mnemonics into a binary code that ean be | undestood by the mieroprocesor The OR gate isa Boolean adder. EXAMPLE 4-1 Solution Related Problem* Boolean algebra isthe mathematics of digital systems. A basic knowledge of Boolean algebra is indispensable to the study and analysis of logic circuits. Inthe last chapter, Boolean operations and expressions in terms of their relationship to NOT, AND, OR, AND, and NOR gates were introduced. After completing this section, you should be able to = Define variable = Define literal ® Identify a sum term ® Evaluate a sum term = Identify a product term ® Evaluate a product term ® Explain Boolean addition = Explain Boolean multiplication Variable, complement, and literal are terms used in Boolean algebra, A variable is a symbol (usually an italic uppercase letter) used to represent a logical quantity. Any single variable can have a 1 or a 0 value. The complement is the inverse of a variable and is indi cated by a bar over the variable (overbar), For example, the complement of the variable A is A.IfA = 1, then A = 0. IFA = 0, then A = 1, The complement of the variable A is read as “not A” or “A bar” Sometimes a prime symbol rather than an overbar is used 0 denote the complement ofa variable; for example, B’ indicates the complement of B. In this book, only the overbar is used. A literal isa variable or the complement of a variable, ‘Boolean Addition Recall from Chapter 3 that Boolean addition is equivalent to the OR operation and the ba- sic rules are illustrated with their relation to the OR gate as follows: 00-0 OF1=1 14021 14 WU) 9) In Boolean algebra, a sum term isa sum of literals. In Iogie circuits, a sum term is pro- duced by an OR operation with no AND operations involved. Some examples of sum terms areA + BA +B,A+ B+ C,andA + B+ C+D. ‘A.sum term is equal to 1 when one or more of the literals in the term are 1, A sum term is equal to 0 only if each of the literals is 0. Determine the values of A, B, C, and D that make the sum term A +B + C + D equal to 0. For the sum term to be 0, each of the literals inthe term must be O. Therefore, A = 0, B= so that B= 0, C = 0,and D = 1 s0 that D = 0. | A+B+C+D=0+1+0+1=04+0+0+4+0-0 Determine the values of A and B that make the sum term A + B equal to 0. TAnswersareattheendofthechaptez. =LAWS AND RULES OF BOOLEAN ALGEBRA = 185 ‘Boolean Multiplication Also recall from Chapter 3 that Boolean multiplication is equivalent to the AND operation The AND gate isa Boolean and the basie rules are illustrated with their relation to the AND gate as follows: ‘multiplier. O+120 1020 Teter slfelielfel In Boolean algebra, a product term is the product of literals. In logic circuits, a prod- uct term is produced by an AND operation with no OR operations involved. Some exam- ples of product terms are AB, AB, ABC, and ABCD. A product term is equal to 1 only if each of the literals in the term is 1. A product term, is equal to 0 when one or more of the literals are 0. EXAMPLE 4-2 = Determine the values of A, B, C, and D that make the product term ABCD equal to 1. Solution For the product term to be 1, each of the literals in the term must be 1. Therefore, 1,B = Osothat B = 1, C = 1,and D = OsothatD = 1 ABCD = 1-0-1 brad Related Problem Determine the values of A and B that make the product term AB equal to 1 fe ION ne REVIEW 1. IFA = 0, what does A equal? Answers are at the end of the 2. Determine the values of A, B, and C that make the sum term A + B + C equal to 0. aap 3, Determine the values ofA, B, and C that make the product term ABC equal to 1, (BRM Laws anv RULEs OF BOOLEAN ALGEBRA AS in other areas of mathematies, there are certain well-developed rules and laws that _must be followed in order to properly apply Boolean algebra, The most important of these are presented in this section, After completing this section, you should be able 10 = Apply the commutative laws of addition and multiplication ® Apply the associative laws of addition and multiplication = Apply the distributive law = Apply twelve basic rules of Boolean algebra ‘Laws of Boolean Algebra ‘The basic laws of Boolean algebra—the commutative laws for addition and multiplication, the associative laws for addition and multiplication, and the distributive law—are the186 © BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION > FIGURE 4-3 ‘Applicaton of swocitive law of addition. Open file F04-03 to vei > FIGURE 4-4 Equation 4-1 Equation 4-2 Equation 4-3 Equation 4-4 same as in ordinary algebra, Each of the laws is illustrated with two or three variables, but the number of variables is not limited to this. Commutative Laws ‘The commutative law of addition for two variables is written as AtB=B+A ‘This law states that the order in which the variables are ORed makes no difference. Re- ‘member, in Boolean algebra as applied to logic circuits, addition and the OR operation are the same, Figure 4-1 illustrates the commutative law as applied to the OR gate and shows that it doesn’t matter to which input each variable is applied. (The symbol = means “equiv- alent 102") > FIGURE 4-1 pneuees ‘ addition, ‘The commutative law of multiplication for (wo variables is AB= BA ‘This law states thatthe order in which the variables are ANDed makes no difference. Figure 4-2 illustrates this law as applied to the AND gate, > FIGURE 4-2 . epee feonmiaia wet of a Associative Laws The associative law of addition is written as follows for three variables: At B+O=(A+B) +E ‘This law states that when ORing more than two variables the result is the same regardless of the grouping of the variables, Figure 4-3 ilustrates this law as applied to 2-input OR gates A 4 A+B+0) ase 2 a asc Uanec ¢ © ‘The associative law of multiplication is written as follows for three variables: A(BO) = (ABC ‘This law states that it makes no difference in what order the variables are grouped when ANDing more than two variables. Figure 4-4 illustrates this law as applied to 2-input AND gates. Application of aociatve lay of rultplication. Open file FO#-04 to ves Equation 4-5 ‘ aos a0) ‘2 er Dy ac goal Distributive Law The distributive law is written for three variables as follows: A(B + 0) = AB + ACLAWS AND RULES OF BOOLEAN ALGEBRA = 187 ‘This law states that ORing two or more variables and then ANDing the result with a sin- gle variable is equivalent to ANDing the single variable with each of the two or more vari ables and then ORing the products. The distributive law also expresses the process of factoring in which the common variable A is factored out of the product terms, for ex- ample, AB + AC = A(B + C). Figure 4-5 illustrates the distributive law in terms of gate implementation. ronan Figure 4-5 . (al be ‘Application of dstbutive lw a =) 4p Open ile FO4-05 to verily ‘ Le ee “as K=Aul+0 XeAn sac “Rules of Boolean Algebra ‘Table 4-1 lists 12 basi rules that are useful in manipulating and simplifying Boolean ex- pressions. Rules 1 through 9 will be viewed in terms of their application to logie gates. Rules 10 through 12 will be derived in terms of the simpler rules and the laws previously discussed. FIGURE 4-8 Rule3.A-0=0 A variable ANDed with 0 is always equal to 0, Any time one input to an AND gate is 0, the output is 0, regardless ofthe value of the variable on the other input ‘This rute is illustrated in Figure 4-8, where the lower input is fixed at 0. > FIGURE 4-9 > FIGURE 4-10 > FiguRE > FIGURE 4-12 det Ano Rule4.A-1=A_ A varinble ANDed with 1 is ulways equal to the variable, ITA is 0 the ‘output of the AND gate is 0. IF is 1, the output of the AND gate is | because both inputs are now 1s, This rule is shown in Figure 4-9, where the lower input is fixed at | Ao—y Rule 5.A+A=A_ A variable ORed with itself is always equal tothe variable. IfA is 0, then 0 + 0 = 0; and ifA is 1, then 1 + 1 = 1, This is shown in Figure 410, where both in- puts are the same variable, azo x0 Azo Rule 6. A+ A= 1 A vatable ORed with its complement is always equal to 1. IFA is 0, then + 0= 0-41 = LIfAis then + T= 1+ 0 = 1,SeeFigure 411, where one input isthe complement ofthe othr. Azo dat Rule 7.A- then 0-0 A_ A variable ANDed with itself is always equal to the variable. ITA = 0, sand if A = I, then | 1 = 1, Figure 4-12 illustrates this rule, Aso—f —— aLAWS AND RULES OF BOOLEAN ALGEBRA = 189 Rule 8. A-A=0 A variable ANDed with its complement is always equal to 0. Either A ‘cA will always be 0; and when a is applied to the input of an AND gate, the output will be 0 also, Figure 4-13 illustrates tis rule Figure 4-13 azo Rule 9. A The double complement of a variable is always equal to the variable. Ifyou Start withthe variable A and complement Giver) tence, you get Af you then take A and complement (inven) it you get A, which i the orignal variable. This rule is shown in Figure 414 using inverters << FiGure 4 Ast re Rule 10.4 +AB=A_ Thisrule can be proved by applying the distributive law, rule 2, and rule 4 as follows: A+ AB=A(L + B) Factoring (distibutive law) AA Rule2 (1+ 8) = 1 =A Rule 4:A-1 =A ‘The proof is shown in Table 4-2, which shows the truth table and the resulting logic cireuit simplification FABLE 4-2 Rule 10:4 + AB= A, Open fle a To#-02 to very. 5 8 1 | 1 4 — Saat connection Rule 11. A+ AB = A+B ‘This rule can be proved as follows ° ° 1 0 0 o 1 ere A+ AB =(4+AB)+AB Rule A= A+AB =(MA-+AB) +AB — Rule7:A = AA =AA+AB+ AA + AB Rule: adding AA = 0 (A+A)(A +B) Factoring =1-4 +2) Rule6:A+A=1 Ate Rate 4 drop the 1190 = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION ‘The proof is shown in Table 4-3, which shows the truth table and the resulting logic cir- cuit simplification, Role 11:4 + AB = file TO4-03 to very +B. Open Rule 12. (A + B)(A + C) = A+ BC This rule can be proved as follows: (A+ B)(A + ©) = AA + AC + AB + BC _Distibutive law =A+AC+AB+ BC Rule7:AA=A = A(I + C) +AB-+ BC Factoring (distributive law) = AL + AB 4 BC Rule2:1+C=1 = A(I +B) + BC Factoring (distributive law) = Al + BC Rule2:1+B=1 =A+ BC Rule 4: +1 ‘The proof is shown in Table 4~4, which shows the truth table and the resulting logic circuit simplification. 1. Apply the associative law of addition to the exprenion A + (B + C+D). | 2. Apply the distributive law to the exprenion A(B + C + D).DEMORGAN’S THEOREMS = 191 (BBM emorcan’s THEOREMS DeMorgan, a mathematician who knew Boole, proposed two theorems that are an important part of Boolean algebra. In practical terms, DeMorgan’s theorems provide ‘mathematical vetification ofthe equivalency of the NAND and negative-OR gates and the ‘equivalency of the NOR and negative-AND gates, which were discussed in Chapter 3. After completing this section, you should be able to ® State DeMorgan’s theorems # Relate DeMorgan’s theorems to the equivalency of the NAND and negative-OR gates and to the equivalency of the NOR and negative-AND_ ‘gates ® Apply DeMorgan’s theorems to the simplification of Boolean expressions (One of DeMorgan’s theorems is stated as follows: ‘The complement of a product of variables is equal to the sum of the complements of the variables. Stated another way, ‘The complement of two or more ANDed variables is equivalent to the OR of the complements of the individual variables. The formula for expressing this theorem fortwo variables is WY=X+¥ Equation 4-6 DeMorgan’s second theorem is stated as follows: ‘The complement of a sum of variables is equal to the product of the complements of the variables. Stated another way, ‘The complement of two or more ORed variables is equivalent to the AND of the ‘complements of the individual variables. ‘The formula for expressing this theorem for two variables is X47 =x7 Equation 4-7 Figure 4-15 shows the gate equivale sand truth tables for Equations 4-6 and 4-7. A URE 4-15 Gate equivalencies and the corresponding truth tables that ‘lytrate DeMorga's theorems. Notice the equality of the two ‘output columas in each table. This shows thatthe equivalent gates perform the same logic function i a = AND, Negative-OR 0 0 1 1 rears Pm aeseaeia Jeeta s = T 1 a y ol a o NOR Negative-AND_ ee oe Deon192. = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION As stated, DeMorgan’s theorems also apply to expressions in which there are more than ‘wo variables, The following examples illustrate the application of DeMorgan’s theorems to 3-variable and 4-variable expressions. EXAMPLE 4-3 =e Apply DeMorgan’s theorems to the expressions XYZ and ¥+ YZ Solution MYZ=X+¥+Z KFV4FZ = XZ Related Problem Apply DeMorgan's theorem tothe expression X + P+ Z. [Pxmote 4-4 a Apply DeMorgan's theorems to the expressions WXYZ and WX FV Z. Solution Way7 = W+X+7+ WHXFVtZ=W L Related Problem Apply DeMorgan's theorem tothe expression WXYZ, Each variable in DeMorgan's theorems as stated in Equations 4-6 and 4~7 ean also rep- resent a combination of other variables, For example, X can be equal to the term AB + C, and ¥'can be equal tothe term A + BC. So if you can apply DeMorgan’s theorem for two ‘variables as stated by XY = X + ¥ tothe expression (AB + C)(A + BC), you get the fol lowing result: (B+ OA + BC) = (GBC) + (AF BC) Notice that in the preceding result you have two terms, AB + C and A + BC, to each of which you can again apply DeMorgan’s theorem XY = XY individually, as follows (AB¥C) + (AF BC) = (ABYC + A(BC) Notice that you sill have two terms in the expression to which DeMorgan’s theorem can again be applied, These terms are AB and BC. A final application of DeMorgan's theorem ives the following result: (Ga\C + ABC) = A+B) + AGE +O Although this result can be simplified further by the use of Boolean rules and laws, De- Morgan's theorems cannot be used any more “Applying DeMorgan’s Theorems ‘The following procedure illustrates the application of DeMorgan's theorems and Boolean algebra to the specific expression F) Step 1. Identify the terms to which you can apply DeMorgan’s theorems, and think of each term as a single variable. Let A + BC = X and D(E + F) = ¥. A+ BC+ DEDEMORGAN'S THEOREMS = 193, Step 2. Since X+ ¥ = XY, (DE + )) Step 3. Use rule 9 (A = A) to cancel the double bars over the left term (this is not part ‘of DeMorgan’s theorem), (A+ BC) + (DIE + F) (A + 8C)(DIE+ F)) (A + BC)D(E + Step 4. Applying DeMorgan's theorem to the second term, (A + BC)(D(E + F)) = (A + BC)(D + (E+ F)) ) to cancel the double bars over the E+ F part of the term Step 5. Use rule 9 (A (A+ BOD +E+F) = (A+ HOD +E +7) ‘The following three examples will further illustrate how to use DeMorgan’s theorems. ee ——_— Apply DeMorgan’s theorems to each of the following expressions: @) @FB+ OD w) ABCTDEF ©) AB + D+ EF Solution (a) Let A + B + C= Xand D = ¥. The expression (A + B+ C)D is of the form XY = X + ¥ and can be rewritten as AFBt+C+D | WrBFC ‘Next, apply DeMorgan’s theorem tothe term A> BC. A¥B4C+D=A8C+D (b) Let ABC = X and DEF = ¥. The expression ABC + DEF is of the form X+ ¥ = XV and can be rewritten as ABC + DEF = (ABC)(DEF) ‘Next, apply DeMorgan’s theorem to each of the terms ABC and DEF. (ABC)\DEF) = (A+ B+ D+ E+F) (©) Let AB = X, CD = Y, and EF = Z The expression AB + CD + EF is of the form X + ¥ + Z = XYZ and can be rewriten as (AB) (Cb)(EF) Next, apply DeMorgan’s theorem to each of the terms AB, CD, and AB + CD + EF G@+ayc+DE+A Related Problem Apply DeMorgan's theorems to the expression ABC + D + E.194 = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION [exemete 4-6 Apply DeMorgan’s theorems to each expression: | (a) (A+B) +C @) (A+B)+CD © (A+ B)CD+E+F Solution (a) (AB) + C= (AF ANE = (A+ B)C BE + D) (4 + B)CD\(E + F) = (AB + C + D)EF (© (A+ B)CD + E+ +E | | | () GB) + C= G+ HD = BC+) Related Problem Apply DeMorgan’s theorems tothe expression AB(C + [eeamece 4-7 = ‘The Boolean expression for an exclusive-OR gate is AB + AB. With this as a starting point, use DeMorgan’s theorems and any other rules or laws that are applicable 10 develop an expression for the exclusive-NOR gate, Solution Start by complementing the exclusive-OR expression and then applying DeMorgan’s theorems as follows: AB + AB = (AB)(AB) Next, apply the distributive law and rule 8 (AA a+ aya +B) ‘A + B)A +B) A=0) (A+ ByA +B) =AA+AB + AB + B= AB + AB ‘The final expression for the XNOR is AB + AB. Note that this expression equals | any time both variables are Os or both variables are 1s. | Related Problem Starting with the expression for a 4-input NAND gate, use DeMorgan’s theorems to | develop an expression for a 4-input negative-OR gate. SECTION 4-3 i 1. Apply DeMorgan’s theorems to the following expressions: | (a) ABC +(D+E) (b) (AF BC (ec) AV BY C+ DE [BRAM S00 LEAN ANALYSIS OF LOGIC CIRCUITS ‘Boolean algebra provides a concise way to express the operation ofa logic circuit formed by a combination of logic gates so that the output can be determined for various, ‘combinations of input values. Alter completing this section, you should be able to ® Determine the Boolean expression for a combination of gates = Evaluate the logic ‘operation of a circuit from the Boolean expression = Construct a truth tableBOOLEAN ANALYSIS OF LOGIC CIRCUITS = 195 ‘Boolean Expression for a Logic Circuit ‘To derive the Boolean expression fora given logic circuit, begin at the let-most inputs and A logic circuit can be described work toward the final output, writing the expression for each gate. For the example cireuit by 2 Boolean equation in Figure 4-16, the Boolean expression is determined as follows: 1. The expression forthe left-most AND gate with inputs C and D is CD. 2. ‘The output of the let-most AND gate is one of the inputs to the OR gate and B is the other input. Therefore, the expression for the OR gate is B + CD. 3. The output of the OR gate is one of the inputs to the right-most AND gate and A is the other input. Therefore, the expression for this AND gate is A(B + CD), which is the final output expression for the entire circuit. cy rune 4-16 2 Ag ca sng Deo development ofthe Boolean a D- ‘expresion for the output. Constructing a Truth Table for a Logic Circuit (Once the Boolean expression for a given logic circuit has been determined. a truth table loge circuit can be described that shows the output for all possible values of the input variables can be developed. The by 2 truth table. procedure requires that you evaluate the Boolean expression for all possible combinations of values forthe input variables. In the case ofthe circuit in Figure 416, there are four in- put variables (4, 8, C, and D) and therefore sixteen (2 = 16) combinations of values are possible Evaluating the Expression To evaluate the expression A(B + CD), frst find the values of the variables that make the expression equal to 1, using the rules for Boolean addition and multiplication. In tis case, the expression equals I only if A = I and B+ CD. because AB+CD)=1-1=1 if either B = 1 or Now determine when the B + CD term equals 1. The term B + CD CD = | orif both Band CD equal | because B+ CD=1+0= B+CD=0+1=1 B+CD=1+1= ‘The term CD = | only if C= 1 and D = 1 ‘To summarize, the expression A(B + CD) = | when A = 1 and B = 1 regardless of the values of Cand D or when A = 1 and C = 1 and D = 1 regardless of the value of B. The expression A(B + CD) = 0 forall other value combinations of the variables. Putting the Results in Truth Table Format ‘The first step is to list the sixteen input vari- able combinations of 1s and Os in a binary sequence as shown in Table 4-5, Next, place & 1 in the output column for each combination of input variables that was determined in the valuation. Finally, place a 0 in the output column for all other combinations of input vari- ables, These results are shown in the truth table in Table 4-5.196 = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION Truth table forthe logic circuit in Figure 4-16. Gey ety ro! 0 Oe Odd 0 0 eerie 0 0 Oe AOE AIT ° a Sete (0 0 oneeai fuses oH a o Ce) 0 Ch o 10 20 0 0 1 ceo 0 he ee a 0 Tee ee ee 1 1 2 0 O 1 ope 1 1 1 to 1 aime 1 SECTION 4- in Fig | FE ic 1. Replace the AND gates with OR gates andthe OR gate with an AND gate in Figure 4-16 and determine the Boolean expression for the output. 2. Construct a truth table forthe circuit in Question 1 GEBBMM simpiricATION USING BOOLEAN ALGEBRA ‘Many times inthe application of Boolean algebra, you have to reduce a particular expression to its simplest form or change its form to a more convenient one t0 ‘implement the expression most efficiently. The approach taken in this section is to use the basie laws, rules, and theorems of Boolean algebra to manipulate and simplify an ‘expression, This method depends on a thorough knowledge of Boolean algebra and ‘considerable practice in its application, not to mention a little ingenuity and cleverness. After completing this section, you should be able to = Apply the laws, rules, and theorems of Boolean algebra to simplify general expressions A simplified Boolean expression uses the fewest gates possible to implementa given ex- pression. Examples 4-8 through 4-11 illustrate Boolean simplification,SIMPLIFICATION USING BOOLEAN ALGEBRA = 197 I EXAMPLE | Boolean algebra techniques, this expression: AB + A(B +O) + BB+ O). Solution ‘The following is not necessarily the only approach. Step 1: Apply the distributive law to the second and third terms in the expression, as follows: AB + AB + AC + BB+ BC Step 2: Apply rule 7 (BB = B) to the fourth term, AB + AB + AC +B + BC | AB+AC+ B+ BC Step 4: Apply rule 10 (B + BC = B) to the last two terms. AB+AC+B Step 5: Apply rule 10 (AB + = B) to the first and third terms. B+AC At this point the expression is simplified as much as possible, Once you gain experience in applying Boolean algebra, you can often combine many individual steps. | Related Problem Simplify te Boolean expression AB + A(B + C) + B(B+ ©), Figure 4-17 shows that the simplification process in Example 4-8 has significantly re- Simplification means fewer gates duced the number of logic gates required to implement the expression. Part (a) shows that _ for the same function. five gates are requited to implement the expression in its original form; however, only two gates are needed for the simplified expression, shown in part (b). Its important to realize that these (wo gate circuits are equivalent, That is, for any combination of levels on the A, B, and C inputs, you get the same output from either circuit i = AB+ A+ €)+18-+0) Bo vac Oi wesai eer 8) Gatco Ege 8 Open FT ov eae198 = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION | [ewe =“ | ‘Simplify the following Boolean expression: [AB(C + BD) + AB}c ‘Note that brackets and parentheses mean the same thing: the term inside is multiplied (ANDed) with the term outside. | Solution Step 1: Apply the distributive law to the terms within the brackets. (ac + ABaD + AB)C 6) o the second term within the parentheses (Ac + a-0-D + AB)c Step 3: Apply le 3(A -0- D = 0) tothe second term within the parentheses (Ac + 0 + AB)C Step 4: Apply rule (drop the 0) within the parentheses. | takes Fe Step: Apply rule 8 (Bi Step 5: Apply the distributive lw Ace Ae Step 6: Apply rule 7(CC = C) to the First term, ABC + ABC | Step 7 Factor out BC. Step 8 Apply rule 6(4 + A= 1). Step 9: Apply rule 4 (drop the I) Bc Related Problem Simplify the Boolean expression (AB(C + BD) + ABCD. | I EXAMPLE 4-10 Simplify the following Boolean expression: ABC + ABC + ABC + ABC + ABC Solution Step 1: Factor BC out ofthe first and last terms. BO(A + A) + ABC + ABT + ABC Step 2: Apply rule 6 (A + A = 1) tothe term in parentheses, and factor AB from the second and last terms BC-1 + AB(C + C) + ABCStep Step 6: Related Problem Simplify SIMPLIFICATION USING BOOLEAN ALGEBRA = Apply rule 4 (drop the 1 tothe ist term and rule 6 (C+ C = 1) tothe term in parentheses te BC + ABAL + Apply rule 4 (drop the 1) to the second term, BC + AB + ABC Factor B from the second and third terms. BC + BA + AC) Apply le 11 (A + AC =A + ©) tothe term in parentheses. BC + BA +7) Use the cistributive and commutative laws to get the following expression: Bc + AB + BC the Boolean expression ABT + ABC + ABC + ABC. [examoce 4 ‘Simplify the following Boolean expression: Solution Step Step 2: Step Step 4: Step 5: Step 6: Related Problem Simplify AB> AC + ABC Apply DeMorgan’s theorem tthe fist ern. (AB)AC) + ABC Apply DeMorgan's theorem to ach term in parentheses G@+BG +0) +ABC Apply the distributive lw to the two terms in parentheses. FA +AC+ AR 4 BC+ ABC Apply tule 7 (A.A = A) to the [AB + ABC = AB + C} st term, and apply rule 10 ‘AB tothe third and last terms H(i + ©) = A) tothe first and second terms. Apply rule 10 [4 + A+AB+ BC Apply rule 10 [A + AB = A(1 + B) A+BC A] to the frst and second terms. the Boolean expression AB + AC + 199200 = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION [fener 4 REVIEW 1. Simplify the following Boolean expressions if posible: (2) A+ AB + ABC (b) (A+ B)C+ABC (e) ABC(BD + CDE) + AC 2. Implement each expression in Question 1 as originally stated with the appropriate logic gates. Then implement the simplified expression, and compare the numberof sates. (BREN sTANDARD FORMS OF BOOLEAN EXPRESSIONS ‘An SOP expression can be implemented with one OR and two oF more ANDs, All Boolean expressions, regardless of their form, can be converted into either of two standard forms: the sum-of-produets form or the product-of-sums form. Standardization ‘makes the evaluation, simplification, and implementation of Boolean expressions much, ‘more systematic and easier After completing this section, you should be able to "= Identify a sum-of- products expression # Determine the domain of a Boolean expression ® Convert any sum-of-produets expression to a standard form = Evaluate a standard sum-of- products expression in terms of binary values ® Identify a produet-of- sums expression ® Convert any produet-of-sums expression toa standard form = Evaluate a standard productof-sums expression in terms of binary values ® Convert from one standard form to the other “The Sum-of-Products (SOP) Form A product term was defined in Section 4-1 as a term consisting of the product (Boolean multiplication) of literals (variables or their complements). When two or more product terms are summed by Boolean addition, the resulting expression is a sum-of-products (SOP). Some examples are AB + ABC ABC + CDE + BCD AB + ABC + AC Also, an SOP expression can contain a single-variable term, as in A + ABC + BCD. Refer 'o the simplification examples in the last section, and you will see that each of the final ex- pressions was either a single product term or in SOP form, In an SOP expression, a single ‘overbar cannot extend over more than one variable; however, more than one variable in aterm ‘can have an overbat. For example, an SOP expression can have the term AB C but not ABC. Domain ofa Boolean Expression The domain of a general Boolean expression is the set of variables contained in the expression in either complemented or uncomplemented form, For example, the domain of the expression AB + ABC is the set of variables A, B, C and the domain of the expression ABC + CDE + BCD is the set of variables A, B, C, D, E. AND/OR Implementation of an SOP Expression Implementing an SOP expression sim- ply requites ORing the outputs of two or more AND gates. A product term is produced by ‘an AND operation, and the sum (addition) of two or more product terms is produced by an OR operation. Therefore, an SOP expression can be implemented by AND-OR logie in which the outputs of a number (equal to the number of product terms in the expression) of AND gates connect to the inputs of an OR gate, as shown in Figure 4~18 for the expression AB + BCD + AC. The output X of the OR gate equals the SOP expression.STANDARD FORMS OF BOOLEAN EXPRESSIONS ao Implementation of the SOP > ‘exprestion AB + BCD + AC. B+ BCD + AC INAND/NAND Implementation of an SOP Expression NAND gates can be used 0 im- plement an SOP expression. Using only NAND gates, an AND/OR function can be ac- ‘complished, a illustrated in Figure 419. The first level of NAND gates feed into a NAND_ ‘gate that acts as a negative-OR gate. The NAND and negative-OR inversions cancel and the result is effectively an AND/OR circuit. Figure 4-19 ‘Thi NANDINAND implementation Is equivalent to the ANDIOR in Ws RCD+AC Figure 4 Db c [Conversion of a General Expression to SOP Form Any logic expression can be changed into SOP form by applying Boolean algebra tech- niques. For example, the expression A(B + CD) can be converted to SOP form by applying the distributive law: A(B + CD) = AB + ACD 201 | [exampLe 4-12 Convert each of the following Boolean expressions to SOP form: (a) AB+ B(CD + EF) (b) (A + BYB+ C+D) Solution (a) AB + B(CD + EF) = AB + BCD + BEF (b) (A+ BIB + C+D) (© GFR) +0 = (4+ BIC Related Problem Convert ABC + (A + B)(B + C + AB) wo SOP form, ‘The Standard SOP Form So far, you have seen SOP expressions in which some of the product terms do not contain all of the variables in the domain of the expression. For example, the expression ABC + ABD + ABCD has a domain made up ofthe variables , B, C, and D. However, notice thatthe complete set of variables in the domain is not represented in the frst wo terms of the expression; that is, D or D is missin from the first tem and C or Cis missing from the second term, ‘A standard SOP expression is one in which al! the variables inthe domain appear in cach product tem in the expression. For example, ABCD + ABCD + ABCD is a stan- dard SOP expression, Standard SOP expressions are important in constructing truth tables, covered in Section 4~7, and in the Karmaugh map simplification method, which is covered (ara +e AB + AC + AD + BB+ BC+ BD (A + BYC = AC + BC202 = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION in Section 4-8, Any nonstandard SOP expression (referred to simply as SOP) can be con. verted to the standard form using Boolean algebra. Converting Product Terms to Standard SOP Each product term in an SOP expression that does not contain all the variables in the domain ean be expanded to standard form to include all variables in the domain and their complements, As stated inthe following steps, 4 nonstandard SOP expression is converted into standard form using Boolean algebra rule 6(A + A= 1) from Table 41: A variable added to its complement equals 1 ‘Step 1. Multiply each nonstandard product term by a term made up of the sum of @ missing variable and its complement. This results in two product terms. As you ‘know, you can multiply anything by 1 without changing its value. ‘Step 2. Repeat Step 1 until all resulting product terms contain all variables in the do- main in either complemented oF uncomplemented form. In converting a prod- uct term to standard form, the number of product terms is doubled for each missing variable, as Example 4-13 shows [Pesmee 4-13 Convert the following Boolean expression into standard SOP form: ABC + AB + ABCD Solution The domain of this SOP expression is A, B, C, D. Take one term at a time, The fist term, ABC, is missing variable D or D, so multiply the first term by D + Das follows: ABC = ABC(D + D) = ABCD + ABCD In this case, two standard product terms are the result. a ‘The second term, AB, is missing variables C or C and D or D, so first multiply the second term by C + Cas follows: | AB = AB(C +0) = ABC + ABC ‘The two resulting terms are missing variable D of D, so multiply both terms by D + Das follows AB = ABc + ABC = ABC(D + D) +A = ABCD + ABCD + ABCD + ABCD In this case, four standard product terms are the result ‘The third term, ABCD, is already in standard form. The complete standard SOP form ofthe original expression is as follows: ABC + AB + ABCD = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD | Related Problem Convert the expression WXY + XYZ + WXY to standard SOP form. Binary Representation of a Standard Product Term A standard product term is equal 10 1 for only one combination of variable values. For example, the product term ABCD is equal to 1 when A= 1, B 1, D = 0, as shown below, and is 0 for all other com- binations of values forthe variables. ABCD = 1-0-1-0 = In tis case, the product term has a binary value of 1010 (decimal ten) Remember, a product term is implemented with an AND gate whose output is I onl ifeach ofits inputs is 1. Inverters are used to produce the complements of the variables as required, his An SOP expression is equal to 1 only if one or more of the product terms in the expression is equal to 1.STANDARD FORMS OF BOOLEAN EXPRESSIONS = 203 i [eemere 4-14 Determine the binary values for which the following standard SOP expression is equal to 1 ABCD + ABCD + ABCD Solution ‘The term ABCD is equal to 1 when A = 1, B I.and D = 1 ABCD = 1-1-1 The term ABCD is equal to when A = 1, B= 0, C= 0, and D ABCD =1-0-0-1 = 11-11 = 1 The term ABCD is equal o | when A = 0, B = 0, C= 0, and D = 0. ABCD = 0-0-0-0 = 1-1-1-1 ‘The SOP expression equals 1 when any or all ofthe three product terms is 1. Related Problem Determine the binary values for which the following SOP expression is equal to 1: Bz + X¥z + XVZ + KvZ + XYZ Is this @ standard SOP expression? "The Product-of-Sums (POS) Form A sum term was defined in Section 4-1 as aterm consisting of the sum (Boolean addition) Of literals (variables or their complements). When two of more sum terms are multiplied, the resulting expression is a product-of-sums (POS). Some examples are t+ aa+e+o) (A+B+O(C+D+ E\(B+C+D) (A+ B\A+B+ C+) ‘A POS expression can contain a single-variable term, a A(A +B + CB + C + D). In a POS expression, a single overbar cannot extend over more than one variable; however, more than one variable in a term can have an overbar. For example, a POS expression can have the term A + B + Cbut not A + B+ C. Implementation of a POS Expression Implementing a POS expression simply requires ANDing the outputs of two or more OR gates. A sum term is produced by an OR operation, ‘and the product of two or more sum terms is produced by an AND operation. Therefore, a POS expression can be implemented by logic in which the outputs of a number (equal to the number of sum terms in the expression) of OR gates connect to the inputs of an AND gate, as Figure 4-20 shows for the expression (A + BB + C + D(A + C), The output X of the AND gate equals the POS expression. v0

ABCD If you substitute, you can see that the product term is 1: ABCD = 1-0-1 Viet=1 ‘To determine the standard POS expression represented by a truth table, list the binary ‘values for which the output is 0. Convert each binary value to the corresponding sum term by replacing each 1 with the corresponding variable complement and each 0 with the cor- responding variable. For example, the binary value 1001 is converted to a sum term as follows: 1001 > A+B+C4+D If you substitute, you can see thatthe sum term is 0: A+B+C+D=14+04+0+1=0+0+0+0=0 ‘From the truth table in Table 4-8, determine the standard SOP expression and the equivalent standard POS expression,BOOLEAN EXPRESSIONS AND TRUTH TABLES = 209 Solution There are four 1s inthe output column and the corresponding binary values are O11, 100, 110, and 111. Conver these binary values to product term as follows on — Asc | 100 —> ABC 110 —> anc 1 — ase | The resulting standard SOP expression forthe output X is X= ABC + ABC + ABC + ABC For the POS expression, the output is O for binary values 000, 001, 010, and 101 Convert these binary values o sum terms as follows: | 000 —+A+B+C 001 +A+B+C | 010 —>a+a+c ol —A+B+C “The resulting standard POS expression for the output X is | X=A+B+OA+E+OA+E+ OA +840) | Related Problem By substitution of binary values, show thatthe SOP and the POS expressions derived in this example are equivalent; that is, for any binary value they should either both be 1 or both be 0, depending on the binary value. SECTION | peta. 1. Ifa certain Boolean expression has a domain of five variables, how many binary ‘values willbe in its truth table? 2, Ina certain truth table, the output is 1 for the binary value 0110. Convert this binary value to the corresponding product term using variables W, X, ¥, and Z. 3. Ina certain truth table, the output is 0 forthe binary value 1100. Convert this binary value to the corresponding sum term using variables W, X, ¥, and Z.210. = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION (RBS tHe KarnaucH map The purpose of a Kamaugh map isto simplify a Boolean expression. A Kamaugh map provides a systematic method for simplifying Boolean expressions and, if properly used, will produce the simplest SOP or POS expression possible, known 1s the minimum expression. As you have seen, the effectiveness of algebraic simplification depends on your familiarity with all the laws, rules, and theorems of Boolean algebra and on your ability o apply them. The Karnaugh map, on the other hhand, provides a “cookbook” method for simplification After completing this section, you should be able to = Construct a Karaugh map for thee or four variables # Determine the binary value ‘of each cell in a Karnaugh map = Determine the standard product term represented by ‘each cell in a Kamnaugh map ® Explain cell adjacency and identify adjacent cells ‘A Karnaugh map is similar toa tuth table because it presents all of te possible values ‘of input variables and the resulting output for each vale. Instead of being organized into columns and rows like a truth table, the Karnaugh map isan array of eellsin which each cell represents a binary value ofthe input variables. The cells are arranged in a way so that sim- plifcation ofa given expression is simply a matter of properly grouping the cells. Karnaugh 1maps can be used for expressions with two, thre, four. and five variables, but we will discuss ‘only 3-variable and 4-variable situations to illustrate the principles. Section 4-11 deals with five variables using a 32-cell Karnaugh map. Another method, which is beyond the scope of this book, called the Quine-MeClusky method ean be used for higher numbers of variables. ‘The number of cells in a Karnaugh map is equal tothe total number of possible input variable combinations as is the numberof rows in a truth table. For three variables, the num- ber of cells is 2° = 8. For four variables, the numberof cells is! = 16. ‘The 3-Variable Karnaugh Map ‘The 3-variable Karnaugh map is an array of eight cells, as shown in Figure 4-21(a). In this case, A, B, and C are used for the variables although other letters could be used. Bi: haty values of A and B are along the left side (notice the sequence) and the values of C are across the top. The value of a given cell is the binary values of A and B at the left in the same row combined with the value of C at the top in the same column, For example, the cell in the upper left corner has a binary value of 000 and the cell in the lower right comer has a binary value of 101. Figure 4~21(b) shows the standard product terms that are represented by each cell in the Karnaugh map. > Figure 4-21 oo. ‘A3-variable Kamaugh map showing 4 a product teem. % 00 | aac | aa on 01 | a0e | Ac 4 1 | ane | anc 0 10 | aac | aac @ » “The 4-Variable Karnaugh Map ‘The 4-variable Karnaugh map is an array of sixteen cells, as shawn in Figure 4-22(a). Bi- nary values of A and B are along the left side and the values of C and D ate across the top. ‘The value of a given cell is the binary values of A and B at the left in the same row com-THE KARNAUGH MAP = 211 D. ep IGURE 4-22 amo aw o_o ‘A 4vcariable Karnaugh map. % 00 |Aaco)anico) aaco}anco o 01 |avco) ance) ance} inca} u 1 |anco}anco} ance] asco} in 10 | co} co} sco) asco} o © bined with the binary values of C and D at the top in the same column, For example, the cell in the upper right comer has a binary value of 0010 and the cell inthe lower right cor- ner has a binary value of 1010. Figure 4-22(b) shows the standard product terms that a represented by each cell in the 4-variable Karnaugh map. "Cell Adjacency ‘The cells in a Kamaugh map are arranged so that there is only a single-variable change be- Cells that differ by only one tween adjacent cells. Adjaceney is defined by a single-variable change. In the 3-variable map variable are adjacent. the 010 cel is adjacent t the 000 cel, the OI! cell, andthe 110 cell "The 010 cel isnot adja- cent to the 001 cel, the 111 cell the 100 cell, or the 101 cell Physically, each cell is adjacent to the cells that are immediately next to it on any of its four sides. A cell is not adjacent to the cells that diagonally touch any of its comers. Also, the cells in the top row are adjacent to the corresponding cells in the bottom row and the cells inthe outer left column are adjacent tothe corresponding cells in the outer right cok ‘umn. This is called “wrap-around” adjacency because you can think of the map as wrap- ping around from top to bottom to form a eylinder or from left to right to form a cylinder. Figure 4-23 illustrates the cell adjacencies with a 4-variable map, although the same rules for adjacency apply 10 Karnaugh maps with any number of cells. Cells with values that differ by ‘more than one variable are not adjacent. GH FIGURE 4-24 c 0 Ae + Alte + ane + Ane ae are Co i> <> a> ap epresion. 4] o EXAMPLE 4-21 ‘Map the following standard SOP expression on a Karnaugh map: ABC + ABC + ABC + ABC | Solution Evaluate the expression as shown below: Place a | on the -variable Karnaugh map in Figure 4-25 for each standard product term inthe expression. ABC + ABC + ABC + ABCKARNAUGH MAP SOP MINIMIZATION = 213 p FIGURE 4-25, © etal o =f ac o anc uf inf 1B ane 0 awe Related Problem Map the standard SOP expression ABC + ABC + ABC ona Kamaugh map. I EXAMPLE 4-22 Map the following standard SOP expression on a Karnaugh map: ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD Solution Evaluate the expression as shown below. Place a 1 on the 4-variable Kamaugh map in Figure 4-26 for each standard product term in the expression. ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD Oo11 0100 1101 1111 1100 0001 1010 > FIGURE 4-26 os amcD ano 1/1 | © at aco | | of inc | u et je tet | anc | 10 1B aca | 7 Related Problem Map the following standard SOP expression on a Karnaugh map: ABCD + ABCD + ABCD + ABCD Mapping a Nonstandard SOP Expression A Boolean expression must first be in standard form before you use a Karnaugh map. If an expression isnot in standard form, then it must be converted to standard form by the proce- dre covered in Section 4-6 or by numerical expansion, Since an expression should be eval- uated before mapping anyway, numerical expansion is probably the most efficient approach, Numerical Expansion of a Nonstandard Product Term Recall that a nonstandard prod- uct term has one or more missing variables. For example, assume that one of the product214" BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION [Pxanece 4-23 Solution terms in a certain 3-variable SOP expression is AB. This term can be expanded numerically. to standard form as follows. First, write the binary value of the two variables and attach a 0 for the missing variable C: 100, Next, write the binary value of the two variables and attach 111 forthe missing variable C: 101. The two resulting binary numbers are the values of the standard SOP terms ABC and ABC. As another example, assume that one of the product terms in a 3-variable expression is B (remember that a single variable counts as a product term in an SOP expression). ‘This term can be expanded numerically to standard form as follows. Write the binary value of the variable; then attach all possible values for the missing variables A and C as follows: B 10 ou 10 11 ‘The four resulting binary numbers are the values of the standard SOP terms ABC, ABC, ABC, and ABC. ‘Map the following SOP expression on a Karnaugh map: A + AB + ABC. ‘The SOP expression is obviously not in standard form because each product term does not have three variables. The first term is missing two variables, the second term is missing one variable, and the third term is standard, First expand the terms numerically as follows: A + AB + ABC 000 100 110 oor 101 o10 ou Map each of the resulting binary values by placing a 1 in the appropriate cell of the 3- variable Kamaugh map in Figure 4-27, » FIGURE 4-27 on off ofa dy Related Problem Map the SOP expression BC + AC on a Karnaugh map.KARNAUGH MAP SOP MINIMIZATION = 215 | EXAMPLE 4-24 Map the following SOP expression on a Karnaugh map: BC + AB + ABC + ABCD + ABCD + ABCD Solution ‘The SOP expression is obviously not in standard form because each product term does not have four variables. The first and second terms are both missing two variables, the third term is missing one variable, and the rest of the terms are standard, First expand the terms by including all combinations of the missing variables numerically as follows: BC AB + ABC + ABCD + ABCD + ABCD 0000 1000 1100 1010 0001 1011 0001 1001 1101 1000 1010 1001 1011 ‘Map each of the resulting binary values by placing a I in the appropriate cell ofthe 4- variable Karnaugh map in Figure 4-28, Notice that some of the values inthe expanded expression are redundant. > FIGURE 4-28 a ano o_o ao Related Problem Map the expression A + CD + ACD + ABCD ona Kamaugh map. \iKarnaugh Map Simplification of SOP Expressions “The process that results in an expression containing the fewest possible terms with the fewest possible variables is called minimization. After an SOP expression has been ‘mapped, a minimum SOP expression is obtained by grouping the 1s and determining, the ‘minimum SOP expression from the map. Grouping the 1s Youcan group 1s on the Karnaugh map according to the following rules by enclosing those adjacent cells containing 1s, The goal is to maximize the size of the ‘groups and to minimize the number of groups. 1. A group must contain either I, 2, 4, 8, or 16 cells, which are all powers of two. In the case of a 3-variable map, 2° = 8 cells is the maximum group. 2, Each cell ina group must be adjacent to one or more cells in that same group, but all cells in the group do not have to be adjacent to each other. 3. Always include the largest possible number of Is in a group in accordance with tule L216 = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION [Pesnetes 25 4, Each I on the map must be included in atleast one group. The Is already in a ‘group can be included in another group as Tong as the overlapping groups include noncommon Is, Group the 1 in each of the Karnaugh maps in Figure 4-29, a co eo Ne Ones ano 1 i Seana otteia Toes Pe Sco Og Con th 0 wo] w] fo om) |: oa 1 o 1 a] a afafafafa afi | 1 uf [a " 1 u ofa [a 1 0 wf] 0 ita wo] rf @ » © o A FIGURE Solution ‘The groupings are shown in Figure 4-30. In some cases, there may be more than one ‘way to group the 1s to form maximum groupings. Wrap sound ajceney Wrsp around ai passin aes ia co | a a a 1 w1@)| oft 1 o1 1 a 1 “LJ Tee A FIGURE 4-30 Determine if there are other ways to group the 1s in Figure 430 to obtain a minimum number of maximum groupings. Determining the Minimum SOP Expression from the Map When all he 1s representing the standard product terms in an expression are properly mapped and grouped, the process ‘of determining the resulting minimum SOP expression begins. The following rules are ap- plied to find the minimum product terms and the minimum SOP expression: 1. Group the cells that have Is. Each group of cells containing 1s creates one product term composed of all variables that occur in only one form (ether uncomplementeddKARNAUGH MAP SOP MINIMIZATION = 217 ‘or complemented) within the group. Variables that occur both uncomplemented and ‘complemented within the group are eliminated. These are called contradictory variables. 2, Determine the minimum product term for each group, a, Fora 3-variable map: (1) A L-cell group yields a 3-variable product term (2) A 2-cell group yields a 2-variable product term. (3) A 4-cell group yields a L-variable term (4) An 8-cell group yields a value of 1 for the expression 1b. Fora4-variable map: (A) A L-cell group yields a 4-variable product term 2) A 2-cell group yields a 3-variable product term 3) A 4-cell group yields a 2-variable product term (@) An 8-cell group yields a I-variable term (8) A.16-cell group yields a value of I for the expression 3. When all the minimum product terms are derived from the Karnaugh map, they tare summed to form the minimum SOP expression. EXAMPLE 4-26 Determine the produet terms for the Karnaugh map in Figure 4-31 and write the resulting minimum SOP expression, sco Solution Eliminate variables that are ina grouping in both complemented and. ‘uncomplemented forms. In Figure 4-31, the product term for the 8:cell group is B because the cells within that group contain both A and A, C and C, and D and D, | which are eliminated. The 4-cell group contains B, B, D, and D, leaving the variables A and C, which form the product term AC. The 2-cell group contains B and B, leaving variables A, C, and D which form the product term ACD. Notice how overlapping i used to maximize the size of the groups. The resulting minimum SOP expression is the sum of these product terms: B+AC+ ACD Related Problem For the Karnaugh map in Figure 4-31, add a 1 in the lower right cell (1010) and determine the resulting SOP expression,218 = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION I EXAMPLE 4-27 Determine the product terms for each of the Karnaugh maps in Figure 4-32 and write the resulting minimum SOP expression. o|@l: ola fa of 1 ee} «| ape w ae w ay ABD @ be alic A FIGURE Solution The resulting minimum product term for each group is shown in Figure 4-32. The ‘minimum SOP expressions for each of the Karmaugh maps in the figure are (a) AB+BC+ABC (b) B+ AC + AC (© AB+AC + ABD (a) D + ABC + BC the Related Problem For the Karnaugh map in Figure 4~32(¢), add a 1 in the O11 cell and dete resulting SOP expression. EXAMPLE 4- = I Use a Kamaugh map to minimize the following standard SOP expression ABC + ABC + ABC + ABC + ABC Solution ‘The binary values of the expression are 101 +011 + 011 + 000 + 100 | ‘Map the standard SOP expression and group the cells as shown in Figure 4-33. > FIGURE 4-33KARNAUGH MAP SOP MINIMIZATION = 219 Notice the “wrap around” 4-cell group that includes the top row and the bottom row of Is. The remaining | is absorbed in an overlapping group of two cells. The | ‘group of four Is produces a single variable term, B. This is determined by observing that within the group, B isthe only variable that does not change from cell to cell. The ‘group of two Is produces a 2-variable term AC, This is determined by observing that within the group, A and C do not change from one cell to the next. The product term for each group is shown. The resulting minimum SOP expression is B+aC Keep in mind that this minimum expression is equivalent to the original standard expression, Related Problem Use a Kamaugh map to simplify the following standard SOP expression: XYZ + XYZ + XYZ + XYZ + XYZ + XYZ I EXAMPLE 4-29 Use a Kamnaugh map to minimize the following SOP expression: BCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD Solution The frst term BCD must be expanded into ABCD and ABCD to get the standard SOP expression, whichis then mapped and the cells re grouped as shown in Figure +34, > FIGURE 4-34 & Ps oo wf «~Y LIa Notice that both groups exhibit “wrap around” adjacency. The group of eight is, formed because the cells in the outer columns are adjacent. The group of four is | formed to pick up the remaining two 1s because the top and bottom cells are adjacent. ‘The product term for each group is shown, The resulting minimum SOP expression is D+BC Keep in mind that this minimum expression is equivalent to the original standard expression Related Problem Use a Karnaugh map to simplify the following SOP expression: WXYZ + Wxyz + WXYz + Wyz + WXYZ220 = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION ‘Mapping Directly from a Truth Table You have scen how to map a Boolean expression; now you will Iearn how to go directly from a truth table to a Kamaugh map. Recall that a truth table gives the output of a Boolean ‘expression for all possible input variable combinations. An example of a Boolean expres sion and its truth table representation is shown in Figure 4~35. Notice in the truth table that the output Xis I for four different input variable combinations. The 1s inthe output column of the truth table are mapped directly onto a Karnaugh map into the cells corresponding to the values of the associated input variable combinations, as shown in Figure 435. In the figure you can see that the Boolean expression, the truth table, and the Karnaugh map are simply different ways to represent a logic function. > Figure PFIGURE 4-35 X= ABC + ABC + ABC + ABC Example of mapping directly from a truth table to a Karnaugh map. "Don't Care” Conditions Sometimes a situation arises in which some input variable combinations are not allowed For example, recall that in the BCD code covered in Chapter 2, there are six invalid com- binations: 1010, 1011, 1100, 1101, 1110, and 1111. Since these unallowed states will never occur in an application involving the BCD code, they can be treated as “don’t care” terms with respect to their effect on the output. That is, for these “don’t care” terms cither a 1 or a 0 may be assigned to the output; it really does not matter since they will ‘The “don’t care” terms can be used to advantage on the Karnaugh map. Figure 4-36 shows that for each “don’t care” term, an X is placed in the eell. When grouping the Is, the Xs can be treated as 1s to make a larger grouping or as Qs if they cannot be used to advan- tage. The larger a group, the simpler the resulting term will be. ‘The truth table in Figure 4~36(a) describes a logic function that has a | output only when the BCD code for 7, 8, or 9 is present on the inputs. Ifthe “don’t cares” are used as Is, the resulting expression for the function is A + BCD, as indicated in part (b). If the “don’t ccares” are not used as 1s, the resulting expression is ABC + ABCD; so you can see the ad- ‘vantage of using “don’t care” terms to get the simplest expression. SECTION w 1. Lay out Kamaugh maps for three and four variables. | 2. Group the Is and write the simplified SOP expression forthe Karnaugh map in. Figure 4-25, | 3. Wit the origina standard SOP expressions fr each ofthe Karnaugh mapsin Figure 4-32.KARNAUGH MAP POS MINIMIZATION = 221

Figure 4-38 | e eayea woo n/o © O[orpaceern | a | f 0 0 | ‘ | \ AsBecsD Avases+d | Related Problem Map the following standard POS expression ona Karmaugh map: | (A+B+T+ DA+B+C+D (A+ B+C+ Dat B+ ‘Karnaugh Map Simpl ‘The process for minimizing a POS expression is basically the same as for an SOP expres- sion except that you group 0s o produce minimum sum terms instead of grouping 1S to pro- ‘duce minimum product terms. The rules for grouping the Os are the same as those for ‘grouping the Is that you learned in Section 4-9. ification of POS ExpressionsKARNAUGH MAP POS MINIMIZATION = 223, eee | (AtB+OA+B+OA+E+ QA+E+O+E+0) EXAMPLE Also, derive the equivalent SOP expression | Solution ‘The combinations of binary values ofthe expression are 0+0+00+0+O+1+H0+1+D0+14+0) “Map the standard POS expression and group the cll as shown in Figure 4-39. > FIGURE 4-39 ac Notice how the 0 in the 110 cells included into a 2-ell group by utilizing the 0 in the 4-cell group. The sum term for each blue group is shown in the figure and the resulting minimum POS expression is AG +0) Keep in mind that this minimum POS expression is equivalent tothe original standard POS expression. Grouping the 1s as shown by the gray areas yields an SOP expression that is ‘equivalent to grouping the Os. AC + AB = A(B + C) Related Problem Use a Kamaugh map to simplify the following standard POS expression: (K+F+ AK +T+ H+ V+ K++ = a) EXAMPLE 4-32 = ie I Use a Kamaugh map 0 minimize the following POS expresso (B+C+DYA+B4+T+D)A+B+C+ DA B+C+DIA+B+C+D) Solution The ist term must be expanded into A + B + C+ DandA +B +C+Dwogeta standard POS expression, whichis then mapped; andthe cells are grouped as shown in |24 8 BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION. Figure 440. The sum term for each group is shown and the resulting minimum POS expression is (C+D A+B+D(A+B+O, inimum POS expression is equivalent tothe original standard POS expression. > FIGURE 4-40 A+peD ao nw 7 “® | ufo ft cep GQ Tenec Related Problem Use a Karnaugh map to simplify the following POS expression: (WHF V+DW+X4 v4 AWHE+ P+ 2W+X+zZ) ‘Converting Between POS and SOP Using the Karnaugh Map ‘When a POS expression is mapped, it can easily be converted to the equivalent SOP form directly from the Karnaugh map. Also, given a mapped SOP expression, an equivalent POS. expression can be derived directly from the map. This provides a good way to compare both ‘minimum forms of an expression to determine if one of them can be implemented with fewer gates than the other. For a POS expression, all the cells that do not contain Os contain 1s, from which the SOP expression is derived. Likewise, for an SOP expression, all the cells that do not con- lain Is contain Os, from which the POS expression is derived, Example 433 illustrates this conversion, fone an eee ne eae aE ta racmagt ha eects tere fon coneerenorn | ‘minimum POS expression, a standard SOP expression, and a minimum SOP expression (@+B4+c4+dla+B+C+D(A+B+C+D) (A+B+C+D)A+B+C+D)(A+B+C+D)FIVE-VARIABLE KARNAUGH MAPS = 225 oo Atnee co ticD anc aN O10 an w/o__n/ 0 | »| WIG le [eb | i Beceo ule ufo B+c+d ABCD ABCD ABCD ABCD (2) Minium POS: (A +B + OB #C + DVB + C+D) ra SOP. Pe ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD (6) Minimam SOP: AC + BC+ BD + BED A Figure 4-41 mum SOP form: (WHEFY+2W+X+ 7+ HW+K+ 7+ HW+K4+7) | Related Problem Use a Karnaugh map to convert the following expression 10 I SECTION 4-10 ; ‘ “Sees 1. Whatis the difference in mapping a POS expresion and an SOP expression? 2. What is the standard sum term expressed with variables A, B, C, and D fora 1011 of the Kamaugh map? 3. What is the standard product term expressed with variables A, B, C, and D fora 1 in cell 0010 of the Karnaugh map? (BER Five-variaBLe KARNAUGH MAPS ‘Boolean functions with five variables can be simplified using a 32-cell Karnaugh map. Actually, two 4-variable maps (16 cells each) are used to construct a S-variable map. You “already know the cell adjacencies within each ofthe 4-variable maps and how to form groups ‘of cells containing 1s to simplify an SOP expression. All you need to lear for five variables is the cell adjacencies between the two 4-variable maps and how to group those adjacent Is,226 = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION > Figure 4-42 ‘A Sevariable Kamaugh map. After completing this section, you should be able to = Determine cell adjacencies in a S-variable map ® Form maximum cell groupings in a ‘variable map = Minimize S-variable Boolean expressions using the Karnaugh map A Kamaugh map for five variables (ABCDE) can be constructed using two 4-variable ‘maps with which you are already familiar. Each map contains 16 cells with all combina- tions of variables B, C, D, and E. One map is for A = Oand the other is for A = 1, as shown in Figure 4-42. be pe Se oa oR OP el COME LL w w a1 o u u 0 0 a=0 ast Cell Adjacencies ‘You already know how to determine adjacent cells within the 4-variable map. The best way to visualize cell adjacencies between the two 16-cell maps isto imagine thatthe A = 0: map is placed on top of the A = I map. Each cell in the A = 0 map is adjacent tothe cell directly below it in the A = 1 map. ‘To illustrate, an example with four groups is shown in Figure 443 with the maps in a3 dimensional arrangement. The 1s inthe yellow cells form an $-bit group (four in the A = 0 > FIGURE pe Istration of groupings of Isin oN adjacent cellsof a S-voriable map. o ‘oO of [aFIVE-VARIABLE KARNAUGH MAPS = 227 ‘map combined with fourin the A = 1 map). The Is in the orange cells form a 4-bit group. ‘The Is the light red cells form a 4-bit group only in the A = O map. The 1 in the gray cell in the A = 1 map is grouped with the 1 in the lower right light red cell in the A = O map to form a 2-bit group. Determining the Boolean Expression The original SOP Boolean expression that is plotted on the Karnaugh map in Figure 4-43 contains seventeen 5-variable terms be- ccause there are seventeen 1s on the map. As you know, only the variables that do not change from uncomplemented to complemented or vice versa within a group remain in the expression for that group. The simplified expression taken from the map is devel- oped as follows ‘The term forthe yellow group is DE. = The term forthe orange group is BCI ‘The term forthe light red group is ABD. ‘The term forthe gray cell grouped withthe red cell is BC DE. Combining these terms into the simplified SOP expression yields X = DE + BCE + ABD + BCDE [examote 4-34 | ‘Use a Kamaugh map to minimize the following standard SOP 5-variable expression: X = ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE | + ABCDE + AB + ABCDE + ABCDE + ABCDE + ABCDE Solution Map the SOP expression. Figure 444 shows the groupings and their corresponding terms. Combining the terms yields the following minimized SOP expression: X + ADE + BCD + BCE + ACDE > FIGURE 4-44 DE Ta po ao AN mo w Po afi a1 u u 0 » Related Problem Minimize the following expression: 'BCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE228 = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION, SECTION | Treview 1. Why does a 5-variable Karmaugh map require 32 cells? 2, What isthe expression represented by 2 5-variable Karaugh map in which each cell contains a 1? GRBBBA viii (optional) Colons and semicolons must be used appropriately in all VHDL programs. ‘This optional section provides a brief introduction to VHDL and is not meant to teach the ‘complete structure and syntax of the language. For more detailed information and instruction, refer tothe footnote. Hardware description languages (HDLs) are tools for logic, ‘design entry, called text entry, that are used to implement logic designs in programmable logic devices. Although VHDL provides multiple ways to describe a logic cireuit, only the simplest and most direct programming examples of text entry are discussed here. Afier completing this section, you should be able to, State the essential elements of VHDL ® Write a simple VHDL program ‘The V in VHDL¥ stands for VHSIC (Very High Speed Integrated Circuit) and the HDL, of course, stands for hardware description language. As mentioned, VHDL. is a standard language adopted by the IEEE (Institute of Electrical and Electronics Engineers) and is des- ignated IEEE Std, 1076-1993, VHDL is a complex and comprehensive language and using ito its full potential involves a lot of effort and experience. VHDL provides three basic approaches to describing a digital circuit using software: behavioral, data flow, and structural, We will restrict this discussion to the data flow ap- proach in which you write Boolean-type statements to describe & logic circuit. Keep in mind that VHDL, as well as the other HDL, isa tool for implementing digital designs and is, therefore, a means (0 an end and not an end in itself, Itis relatively easy to write programs to describe simple logic circuits in VHDL. The logi- cal operators are the following VHDL keywords: and, oF, not, nand, nor, xor, aid xnor, The ‘two essential elements in any VHDL program are the entity and the architecture, and they must bbe used together. The entity scribes a given logic function in tetms of its external inputs and ‘outputs, called ports. The arehitecture describes the internal operation of the logic function. nits simplest form, the entity element consists of three statements: The first statement assigns a name (oa logic function; the second statement, called the port statement which is indented, specifies the inputs and outputs; and the third statement is the end statement. AI- though you would probably not write a VHDL program for a single gate, itis instructive 0 start with a simple example such as an AND gate. The VHDL entity declaration for a 2input AND gate is entity AND_Gate? is port (A, B: in bit; X: out bit) ‘end entity AND_Gate2; ‘The blue boldface terms are VHDL keywords; the other terms are identifiers that you assign; and the parentheses, colons, and semicolons are required VHDL syntax. As you can see, A and B are specified as input bts and X is specified as an output bit. The port identifiers A, Band X as well asthe entity name AND_Gate? are user-defined and can be renamed. Asin all HDLs, the placement of colons and semicolons is crucial and must be strictly adhered to ‘The VHDL. architecture element of the program for the 2-input AND gate described by the entity is| ‘See Floyd, Thomas, 2003. Digie! Fundamenals wih VHDL. Prentice Hall; Pellerin, David and Taylor, Douglas 1997, VDL Made Easy! Prentice Hall Bhasker, ayaram. 199, A VEDI. Primer, Se Prentice HalVHDL = 229 architecture LogicFunction of AND_Gate2 is begin X = AandB; end architecture LogicFunction; Again, the VHDL keywords are blue boldface, and the semicolons and the assignment op- erator += are required syntax. The first statement of the architecture element must refer- cence the entity name. ‘The entity and the architecture are combined into a single VHDL program to describe an AND gate, as illustrated in Figure 4-45, < FIGURE 4-45 senlty AND Gat? is et i ot bh {AVHOL pogo fra Zope AND cnt AND Ga te wien aitecstancnss = 5 — | —* a ‘i arehiteture LoglFunton: Writing Bootean Expressions in VHDL. As you saw, the expression for a 2-input AND. gate, X= AB, is writen in VHDL as X A.and B;, Any Boolean expression can be writ- ten using VHDL keywords not, and, of, nand, nor, xor, and xnor. For example, the Boolean expression X =A + B+ Ciswrttenin VADLasX = Aor B orC;. The Boolean expression X = AB + CD can be written asthe VHDL statement X = (A and not B) or (not Cand D);, As another example, the VHDL statement for a-input NAND gate can be writen as X <= nof(A and B);oritcan be writen as X = Anand Bi [Pemeteess = Write a VHDL program to describe the logic circuit in Figure 4-46, > FiguRE 4. 6 cae Solution ‘This AND/OR logic cicuit is described in Boolean algebra as X=AB+ CD ‘The VHDL program follows. The entity name is AND_OR entity AND_OR is port (A, B, C, D: in bt; X: out bit); end entity AND_OR; architecture LogicFunction of AND_OR is begin X <= (Aaand B) or (Cand Dy; end architecture LogieFunction; | Related Problem Write the VHDL statement to describe the logic circuit if a NOR gate replaces the OR jeate in Figure 446,230 = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION [freren 4-12 REVIEW 1. What is an HDL? 2. Name the two estental design elements in a VHDL program. 3. What does the entity do? 4. What does the architecture do? Ena Ort Seven-segment displays are used in many | types of products. The tablet-counting and control system that was described in ae || These displays ae used with logic circuits | that decode a binary coded decimal (BCD) umber and activate the | See emcities ieere nk Aigital system application, we focus on a rminimum-gate design fortis to illustrate _an application of Boolean expresions ‘and the Karaugh map. Asan option, VHDL is ako applied. The 7Segnent Diplay tee eer fomat composed of ven elements or eee eed ae ee Ce cach othe te de rl st be Gipayed. Figure 448 tates this method of digtldpay for each ofthe ten igs by ong ord pent to represent one that ened. To | proce segnens bande we nerd; to produce 32 segments, 6 | pe anda id and soon, LED Displays One common type of segment diplay const of light-emitsing low-level voltage in onder actiate a given | seggnent. When LOW is applied toa seg- ‘ment input the LED i tuned on, and there ‘scat through tn Figure 4-49(6) the commen-cathode arangement require the chive to provide high-level voage to ac- thate a segment. When a HIGH i appli to a segment input the LED istumed on and there scare through URE Seven-segment display format showing arrangement of regments, | LCD Displays Another common type of 7-segment diplyi the liquid enstal dlspay (LED). LCDs operate by polar ing ight so that a nonactvated segment reflects incident light and thus appear invble against its background. An ati- vated segment does nt eflect incident light an thus appears dark, LCDs con- sume much les power than LEDs but diodes (LEDs) aranged as shown in Fine 4-49. Eochegment isan LED that emits light when there is curent trough it In Figure 440) the common-anede arange- rent requis the diving cuit to provide a oo ma AA Lt Ct mi] q ooo cr A FIGURE 4-48 Display of decimal digits with 2 7-segment device, FIGURE 4-49 wv ae eee ‘Anangements of segment LED « are f f * > . ® = a (@) Common anode (©) Common cathode‘cannot be een in the dark, while LEDs can Segment Logic Each segment i used for various decimal dls, but no one segment is wed for all ten digits. Therefore, each segment must be activated by its own decoding circuit that detects the occurrence of any ofthe ‘numbers ia which the segment i used. From Figures 4-47 and 4-48, the segments thatare required to be activated foreach dliplayed digit are determined and listed, in Table 4-9. ‘Truth Table forthe Segment Logic ‘The segment decoding logic requires four binary coded decimal (BCD) inputs and | seven cutputs, one foreach segment in | the display, as indicated inthe block dior ‘gram of Figure 4-50, The multiple-out= put trth table, shown in Table 4-10, actually seven truth tables in one and. ‘could be separated into a separate table for each segment. A | in the zegment > TABLE 4-9 ‘Active segment for each decimal diet. | = Ficure 4-50 ‘output columns ofthe table indicates an activated segment Since the BCD code doesnot include the binary values 1010, 1011, 1100, 1101, 1110, and 1111, these combinations will never appear on the inputs and can therefore be tented as “don't care” (X) conditions, sndicated in the wut table. To confor with the practic of mos IC | manufactures A represents the least siniticant bit and D represents the mest | sniliant bitin this particular application. | Boolean Expressions for the Segment Logie From the tuth table, a standard SOP oF POS expression can be written for cach segment. For example, the standard SOP expresion for segment ais DCBA + DCBA + DBA + DcBA + DCBA + DCBA + DCBA + DCBA and the standard SOP expresion for segment eis BA + abedef be abdeg abodg behe adhe wedelsy abe abodete abedtg 0 1 2 3 4 5 6 1 8 9 Block diagram of segment logic and display Tesexient ‘ecoding DIGITAL SYSTEM APPLICATION = Expressions for the other segments can be similarly developed. As you can se, the ‘epresion for segment a has eight product | tet: and the expresion for segment e has four product terms representing each of. ‘the BCD inputs that activate that segment: This means that the standard SOP implementation of egment-a logic requires an AND-OR circuit consisting of eight input AND gates and one B-input OR gate. The implementation of segment «logic requires four input AND gates ‘and one 4-input OR gote. In both cases, our inverters are roquited to produce the ‘complement ofeach variable ‘Karnaugh Map Minimization of the Segment Logic Let's begin by obtaining 2 minimum SOP expression for segment a. ‘A Kammaugh mop for segment ai shown in Figure 4-51 and the following steps re carried out: Step 1. The ts are mapped directly from Table 4-10, mi logic c Binary code decinal B segment display 231232. = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION TABLE 4-10 ‘Truth table for -segment logic Peay INPUTS ica A ‘npr = Tins sgt ivan) up =O mean sant sm ate th up = X men“ te Bean Stop 2. Allof the "don't cares"(X) are | cells are utilized to form the the terms to form the minimum placed on the map. largest groups pouibe, SOP expression, ‘Step 3. The Isare grouped as shown. | Step 4. Write the minimum product “Don't cars” and overlapping of term foreach group and sum Sided $OPepemioe DCHA + DCBA + DCRA + DCBA + DCRA + DRA + DEBRA + DCBA Gl “Ld * Kamaugh map minimization ofthe segment-a logic expresion, Keep in mind that “don’t cares” do not have to be included ina group, but inthis ‘case all of them are wed. Also, notice that the Is in the comer cell ate grouped with 2 "don'teate” using the “wrap around?” adjacency ofthe corner eel. FIGURE 4. ‘The minimum logic implementation for segment a ofthe 7-segment cplay.Minimum Implementation of Segment-a Logie The minimum SOP expresion taken fiom the Karnaueh map in Figure 4-52 forthe segment-a logic is DtBtA+CA This expression can be implemented with two Z-input AND gates, one 4= input OR gate and two inverters a show in Figure 4-52. Compare this to the standard SOP implementation for segment-a logic dicussed eater; you'll ce thatthe numberof gates and inverter: has been reduced from thirteen to five and, 5a result, the number of interconnections has been sigificantly reduced. The minimum logic for each of the remaining sx segments (b, «de, f, and g) can be obtained witha similar approach VHDL implementation (optional) ‘Allof the segment loge can be described by \VHOL for implementation in a programmable logic device. Segment-a loge can be described by the fllowing VHDL program: entity SEGLOGIC is port (A,B,C, Drin bit SEGa: out bit cond entity SEGLOGIC; architecture LogicFuneton of SEGLOGIC is begin SEGa <= (Aand C) or (not A ‘and not C) or Bor D; end architecture LogicFunction; SUMMARY = 233 System Auignment 1 Activity 1: Determine the minionuon logic for segment 5. = Activity 2: Determine the minimum logic for segment © Activity 3: Determine the minimum logic for segment 1 Activity 4: Determine the minimum logic for segment. Activity 5: Determine the minimum logic for segment ® Activity 6: Determine the miniowm logic for segment. | Optional Activity: Complete the VHDL. rogram forall seven segments by Jncluding each segment logic description inthe architecture. BUY "© Gate symbols and Boolean expressions for the outputs of an inserter and 2-input gates are shown in Figure 4-53, = Commutaive avs: A+ B= B+ A [>-« [>a AB = BA Associative laws: A+ (B+ C= (A+B) + ABC) = (ABYC = Distributive law: A(B-+ ©) = AB + AC = Booleanrules: 1. A+O=A TAA 2 Aviat BAA 3 A0=0 9 AA 4 ALeA 10, ASAB=A 8 A+A=A A+ AB=A+B 6 Ata=t 1, A+BYA+O)=A+BC = DeMorgan’s theorems: 4. The complement ofa product is equal to the sum of the compl product nents ofthe terms inthe234 = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION 2 The complement ofa sum is equal tothe product ofthe complements ofthe terms in the sum, xeY XY "= Karmaugh maps for 3 and 4 variables are shown in Figure 4-54. A S-variable map is formed, from two 4-variable maps. > Figure 4-54 a eS a eEeeEseerereer itt a0 ii ano o_o o w on o u " 0 0 “variable ‘earn "= The basic design element in VHDL is an enttyfarchiteture pat (ERT tar sc ctnertots term inthe chapter ae defined in the end-obook lon Complement The inverse or opposite of a number. In Boolean algebra, the inverse function, ex- pressed with a bar over a variable. The complement ofa {i 0, and vie vers, “Don’t care” A combination ofinpt literals that cannot oevur and canbe used as 1 or a0 ona Kar natgh map for simplification, ‘Karnaugh map An arrangement of cells representing the combinations of literals in a Boolean ex- pression and used fora systematic simplification ofthe expression. “Minimization The proces that result in an SOP or POS Boolean expression that contains the Fewest possible literals per term, Produet-of-sums (POS) A form of Boolean expression that is basically the ANDing of ORed terms. Product term The Boolean product of two or moe literals equivalent tan AND operation. ‘Sum-of-products (SOP) A form of Boolean expression that is basically the ORing of ANDed terms. ‘Sum term The Boolean sum of two oF more literals equivalent to an OR operation, Variable A symbol used to representa logical quantity that ean have a value of | or O, usually des- ignated by an italic Fete, ‘VHDDL A standard hardware description language. IEEE Std 1076-1993, EG eve are ttre end ofthe chapter. 1, The complement of a variable is always (0 ()1_— (equal tothe variable (A) the inverse ofthe variable 2 The Boolean expression A +B + Cis (a)asum term — (b)aliteal erm —(@) aproduet term —_(@) a complemented term 3. The Boolean expression ABCD is (a)asumterm (bya productterm (ea fiteral term —_(@) always 110. 1 2 1B 4 16, ”. 18, . a. Which ofthe following rules states that if one input of an AND g SELF-TEST = 235 ‘The domain ofthe expression ABCD + AB + CD + Bis (a)AandD — (b)Bonly — (@A,B.CandD —_(@) none of these . According to the commutative law of addition, (aap (Aqaba (A+ BHOAFB+C WAYB=B+A According tothe associative law of multiplication, (@)B~ BB W)ABO= ABC (A+B +A @B+BB+0) 1 According to the distributive law, (AB+O=AB+AC W)ABO)= ABC @AAFI)=A MATA ‘Which one of the following is nora valid rule of Boolean algebra? @A+I=1 W)A=A ]AA@A MAFOmA is always 1, the out is equal tothe other input? watt ata @AA=A MAT According to DeMorzan's theorems, the following equaltys) is (are) comect (@)AB=A4B ()KZ=F+V47Z (AFBFE=ABC — @hallofthese “The Boolean expression X = AB + CD represents (4) 0 ORs ANDed together (b)a4-input AND gate (O)WOANDs ORed together (@) an exclusive-OR An example ofa sum-of: products expression is (A+ BC + D) ()AB + AC + ABC (A+ B+ C(A+B+ ©) CAboth answers (a) and (6) ‘An example of a product-f-sums expression is GABF OFAC (A+ BIA+B +O) (A+B+ BC ——@)bothanswers (a) and (b) Anexample ofa standard SOP expression is (a) AB + ABC + ABD (by ABC + ACD (AB +AB+AB (A) ABCD + AB +A . A. 3.variable Karnaugh map has (a)cight cells (hy threceclIs(@)sixtooncolls_(€) four cells Ina 4-variable Kamaugh map, 2-variable proguet erm is produced by (a) a2-cell group of 1s (b) an 8- Freure SECTION 4- SECTION 4-2 SECTION 4-3 SECTION 4-4 Boolean Operations and Expressions 1 Using Boolean notation, write an expression that isa 1 whenever one or more of its variables (A.B, Gand D) are Is. ‘Write an expression that is a1 only if al fis variables (A,B, C, D, and E) are Is. 3. Write an expression that is a1 when one or more ofits variables (A,B, and C) are Os. 4. Evaluate the following operations: @O+O+1 I++ 1-0-0 @irt © 1-0-1 Hr-1+0-1-1 5. Find the values of the variables that make each product term I and each sum term 0. (a) aB (b) ABC) (@ A+B (A+ B+C (A+B+C A+R (ABC 6 Find the value of forall possible vals of the arable. @)X=A+HCHE X= (AFRIC (© X= abc +B @X=A+BA+H X= (A+ BCE +e) Laws and Rules of Boolean Algebra 7. eatify the law of Boolean algebra upon which each ofthe following equalities is based (a) AB + CD + ACD + B= B+ AB + ACD + CD (b) ABCD + ABC = DCBA + CBA (©) AB(CD + EF + Gil) = ABCD + ABEF + aBGH 8. Identify the Boolean rule(s) on which each ofthe following equalities is based: (a) AB+ CD + EF = AB + CD+ EF — (b) AAB + ABC + ABB = ABC (© ABC+ BO) +AC=ABQ+AC (A) AB(C + C) + AC = AB + AC (©) AB + ABC = AB (f) ABC + AB + ABCD = ABC + AB + D DeMorgan’s Theorems 9. Apply DeMorgan’s theorems to each expression: (@atB AB (AtBTC @) ABC (@AB+C) (AB+CD (ABT CD (hy (A+ BC+ D) 10. Apply DeMorgan’s theorems to each expression: (a) AB(C + D) (b) AB(CD + EF) (0 G+BHC#D)+ MCD (RBH CH D/ABCD) (@) AB(CD + EF\AB + CD) 1, Apply DeMorgan’s theorems othe following « © ( Boolean Analysis of Logic Circuits 12, Write the Boolean expression foreach of the logic sates in Figure 4-55. ri Pe SD: I= 5 © «bom > FIGURE SECTION 4-5 PROBLEMS = 237 13. Write the Boolean expression foreach ofthe logic cieuits in Figure 4-56, cig erly {= p= 14, Draw the logic circuit represented by each of the following expressions: (A+B+C (ABC (AB+C (Ad) AB+ CD 18, Draw the logic circuit represented by each expression: (@) AB + AB (b) AB EAB + ABC © ABC+D) AF BIC + DIB +O) 16. Construct ath table fr each of the following Boolean expressions: (A+B (b) AB (0) AB+ BC Marae © (A+jB+o ‘Simplification Using Boolean Algebra 17. Using Boolean algebra techigues, simplify the following expressions as muchas posible (a) A(A +B) (b) AG + AB) (©) BC + BC @) AA +48) (@) ABC + ABC + ABC 18, Using Boolean algebra, simplify the following expressions (@) (4+ BA+C) (b) AB + ABC + ABCD + At (©) AB + ABC +A (@) (A + AAR + ABC) (©) AB+ A+ BC+ AB 19. Using Boolean algebra, simplify cach expression: Ec OE Xl) a OEE) ABCD (©) (8+ BC\(B + BC\B+D) —(@) ABCD + AB(CD) + (BJD (© ancian + Cac + Ac) 20, Determine which of the logic circuits in Figure 4-57 are equivalent, oy ee n a i @ by a! rc) ©238 BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION. SECTION 4-6 Standard Forms of Boolean Expressions SECTION 4-7 21, Conver the following expressions to sum-of product (SOP) forms: ( (A+ BC+B) )(AFBEIC (A+ OMB +AE) 22 Convert the following expressions to sum-of product (SOP) forms: (a) AB + CD(AB + CD) (b) AB(BC + BD) (e) A+ BIAC + (B + CD) Define the domain of each SOP expression in Problem 21 and convert the expression to standard SOP form, ‘Convert each SOP expression in Problem 22 to standard SOP form Determine the binary value of each term in the standard SOP expressions from Problem 23. Determine the binary value ofeach tem in the standard SOP expressions from Problem 24. ‘Convert each standard SOP expression in Problem 23 to standard POS form, ‘Convert each standard SOP expression in Problem 24 to standard POS form, B BSRRE Boolean Expressions and Truth Tables 28. Develop a truth table for cach of the following standard SOP expression: (a) ABC + ABC + ABC (by XYZ + X¥2 + xvZ + NVZ + XYZ 30, Develop arth table foreach of the following standard SOP expression: (a) ABCD + ABCD + ABCD + ABCD (b) wxYZ + WXYZ + WXYZ + WXYZ + WXYZ. 31. Develop a truth table foreach of the SOP expressions (a) AB + ABC +AC + ABC (b) X + YZ + Wz + XYZ 32, Develop uh tble foreach a the stanard POS expressions (@) (A+B + (A+ B+ (A+B +0) () (A+ B+ C+ D(A+B+ C+ D(A+B+C+D\IA+B+C+D) 38, Develop a truth table foreach of the standard POS expressions: (@) A+ BA + OHA +B +O (b) (A+ BA +B + CB +C+DYA+B+C+D) 34. Foreich ruth able in Figure 4-58, derive a standard SOP and a standard POS expression Cy ® © @SECTION 4-8 SECTION 4-9 PROBLEMS = 239 ‘The Karnaugh Map 35, Draw a 3-varable Karnaugh map and label each cell according ois binary value. 136, Draw a 4-variable Karnaugh map and labo each cell according to its binary value 37. Write the standard product tem foreach cell in a 3-variable Kamaugh map. Karnaugh MAP SOP Minimization 38. Use a Karnaugh map to find the minimum SOP form for each expression: (a) ABC + ABC + ABC ) ace + 6) (©) A(BC + BC) + A(BC + BC) (A) ABC + ABC + ABC + ABC 239, Use a Karaugh map to simplify each expression toa minimum SOP form: (a) ABC + ABC + ABC + ABC (b) ACB + BB + 0) (©) DEF + DEF + DEF 40, Expand each expression ta standard SOP form (a) AB + ABC + ABC (by A+ ac (¢) ABCD + AcD + BED + ABCD (@) AB + ABCD + Cb + BCD + Anco 41. Minimize each expression in Problem 40 with a Kamaugh map. 42, Use a Kamaugh map to reduce each expression toa minimum SOP form: (a) A+ BC + cD (b) ABCD + ABCD + ABCD + ABCD (6) AB(CD + CD) + ABCD + CD) + ABCD (@ (4B + AB\(CD + CD) (©) AB+AB+CD + cD 43, Reduce the Function specified inthe truth table in Figure 4-59 to its minimum SOP form by using « Karnaugh map 444. Use the Karagh map method to implement the minimum SOP expression fo he logic function specified inthe uth table in Figure 4-0. earraar ey a eae ooo} i & 0000 : oor} 4 coor o1o| o & oo10 O11} 4 oot ‘ too] 4 o100 Tou | oro ito} o orto iit} Ges a 1000 1001 A FIGURE 4-59 Tou rol 1100 1101 1110 | ti i4 A FIGURE 4-60 45. Solve Problem 44 for situation in which the last six binary combinations are not allowed,240 = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION. SECTION 4-10 SECTION 4-11 SECTION 4-12 Karnaugh Map POS Minimization 46, Use a Kamaugh mp to find the minimum POS for each expression: (@) (A+ B+ CA +B+ OA +B +0) ) (KF + XH V+ HX+V +2) © AB+OR+OA+E+OA+B+O 47. Use a Karnaugh map to simply each expression to minimum POS form: (@ (A+B +C=D\A+B+C+ DA +B+ C+D) ) + HW + DE+P+Bwexey +z) 48, Forthe function spectid inthe truth table of Figure 4-59, determine the minimum POS expression using a Karnaugh map. 49._Determie the minimum POS expression for the fonction in the rth table of Figure 4-60 50. Convert each ofthe follwing POS expressions to minimum SOP expressions using & Kamaugh map: (@) (A+B +OA+B+C) ©) A+ BAH + OB + C+ NA+ B+C+D) Five-Variable Karnaugh Maps SL. Minimize the following SOP expression using a Karmaughh map ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE + ABCDE 52. Apply the Karnaugh map method to minimize the following SOP expression: A= VWXYZ + ViixYZ + VWRYZ + VWXYZ + vwxYZ + VIWRYZ + VWxvZ + VWXYZ + VWXYZ VHDL (optional) 2. Wi VHDL program forthe logic circuit in Figure 4-61 > FIGURE 4-61 S34, Write @ program in VHDL forthe expression Y= ABC + ABC + ABC + ABC Digital System Application 485. Ifyou are required to choose a type of digital display for low light condition, will you select LED or LCD 7-segment displays? Why? 186. Explain why the codes 1010, 1011, 1100, 1101, 1110, and 111 fll into the “don’t care” category in T-segment display applications. ‘57. For segment b, how many fewer gates and inverters does i take to implement the minimum ‘SOP expression than the standard SOP expression? 58. Repeat Problem 57 forthe logic for segments c through ¢ ‘Special Design Problems 59, ‘The logic for segment ain Figure 4-52 produces a HIGH output o activate the segment and so do the ciruits for each ofthe ether segments. Ifa type of T-segment display is used that requires a LOW to activate each segment, modify the segment logic accordingly.ANSWERS = 241 60, Redesign the logic for segment a using a minimum POS approach. Which is simpler, ‘minimum POS or the minimum SOP? G1. Repeat Problem 60 for segments b trough g (62, Summarize the results of your redesign effort in Problems 60 and 61 and recommend the best ‘design based on fewer ICs. Specify the types of ICs. Multisim Troubleshooting Practice a (3. Open file PO4-63, apply input signals, and observe the operation ofthe logic circuit Determine whether or not a fault exists. (64, Open file PO4-64, apply input signals, and observe the operation ofthe logic circuit. Determine whether or not a faut exists, 65. Open file PO4-65, apply input signals, and observe the operation ofthe logic circuit. Determine whether or not a fault exists, SECTION 4-1 Boolean Operations and Expressions La BA T+T+0=0+0+0-0 SECTION Laws and Rules of Boolean Algebra LA+@+C+D)=A+H+O+D 2 AB+C+D)=AB+AC+AD SECTION DeMorgan’s Theorems 1. (@) ABC +(D+E)=A+B+C+DE (AFBI @ 47B+C+DE=ABC+D+E SECTION 4-4 Boolean Analysis of Logic Cireuits 1. (C+DB+A 2. Abbreviated truth table: The expression isa when A ig I or when Band C are Is or when B tnd D are 1s. The expression is 0 forall other variable combinations. SECTION Simplification Using Boolean Algebra 1 @)A+ABH+ABC=A — (b) (A+ BC+ARC= CA +B (© ABC(BD + CDE) + AC = A(C + BDE) 2 (a) Original: 2 AND gates, | OR gate | inverter; Simplified: No gates (straight connection) () Original: 2OR gates, 2 AND gates, | inverter; Simplified: 1 OR gate, 1 AND gate, 1 inverter (©) Original: 5 AND gates, 2OR gates, inverters; Simplified: 2 AND gates, LOR gate, inverters SECTION 4-6 Standard Forms of Boolean Expressions 1. (@) SOP (b) standard POS —(¢) standard SOP__(@) POS 2 (@) ABCD + ABCD + ABCD + ABCD + ABCD + AuCD + ABCD + Ancd (6) Already standard 3. (b) Already standard AFB + CAFE + OMA 4 B+ OAL BE +O)242 = BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION SECTION 4-7 Boolean Expressions and Truth Tables LY=32 9 2010 —> WAZ 3. 100 — WH Xt +z SECTION 4-8 The Karnaugh Map 1. (a) upporlefcll: 000 (b) lowerright cell 101) lower lft el: 100, (@) upper ight cell: 001 2. (a) upper left cell: XYZ (b) lower right cell: XYZ (@) lower left cell: XPZ (@) upper right ce: XYZ 3. (a) upperleltcell0000 (b) lowerrightcell: 1010 (@) lower eft cel: 1000 (4) per sight ct: 0010 4. (a) upperlett cell: YZ —(b) lowervight elt: WHIZ —(@) lower left cell: WRTZ (4) upper right cei: WXYZ SECTION 4-9 Karnaugh Map SOP Minimization 1, Sell map for 3 variables; 16-ell map for 4 variables 2. AB + BC + ABC 3. (@) ABC + ABC + ABC + ABC () ABC + ABC + ABC + anc + ABC + ABC (©) ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD (@) ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD SECTION 4-10 Karnaugh Map POS Minimization 1. In mapping a POS expression, Os are paced in cells whose value makes the standard sum term ze10; and in mapping an SOF expression Is are placed in cells having the same values a the product terms 2. O in the 1011 cell: 3. Lin the 0010 cell: ABCD SECTION 4-11 Five-Variable Karnaugh Maps 1, There are 32 combinations of variables 2° = 32), 2, X= 1 because the function is | for all possible combinations of 5 variables SECTION 4-12 VHDL (optional) 1. ANDi hardware decison language for programmable Wg 2. Ent and arctitete 2. Th nity pili thine und tpt of gic fio. icra Secrest eyes ok gs eos 44 A+ B=Owhend = 1 and B= 0, 42 AB=JwhenA=OandB=0 43.07 44. WHXFY+Z 4S ARCDE 46 (A+B + 47 ABCD=A+B+C+D 4848 49CD 4410 ABC + Ac +48 4 A+B+T 412 ABC + AB + AC +AB + BC 413 WRYZ + WRYZ + WHYZ + WXYZ + WNYZ + WAYZ 414 O11, 101, 110,010, 111, YesANSWERS = 243 HIS (A+ E+ CAF B+ OA + B+ CMA+B+O) 416 010, 100,001, 111,011. Yes 4-17 SOP and POS expressions are equivalent 4418 SeeTable 4-11, 4419 See Table 4-12. vw : fi oy | C0 1 | 0 1 0 be eo ' o ce 0 1 O41 o ° i 1 ° Od 1 1 Oe 0 12 00 1 Ve oo 1 1 1 ee I 1 td ° ° teed 0 1 1 eo 1 ° Laced 1 ° 4-20 The SOP and POS expressions are equivalent, 4-21 See Figure 4-62 4.22 Sco Figure 4-63, 4-23 See Figure 4-64. 4-24 See Figure 4-65, 4-28 Noother ways 426 X= B+ AC + ACD + CD 4.27 X=D + ABC + BC + AB 428 O=xK+Y 4:29 = X¥Z+ wiz + Wiz 4-30. See Figure 4-66. 2 CF « CG aX 01 wo 0 uw aN oo o_o 0 o oof o \ a 1 o 1 afi] o 1 4 uf fi u 1 ufafafa]a wf fo 0 0 wofififafi a Figure 4-62 A FIGURE 4-63 A FIGURE 4-64 A FiGURE 4-65 mn 451 O= (KF N+ DErY+D as 110 ¥ : 482 O= HHT +2W+X+ W444 2WEEFY+2) mo |e 433 Q= 72+ 32+ Wr + iz 2 . 46 Y=DE+AE+BCE 4-35 X = (Aand B) nor (Cand D); u | SELF-TEST © ° L@ 20 306 40 &@ 6H 7 &O .@ Wd LO LY B® WO Ka BO a Figure 17. (@) 18) 19.) 20.06) 2)

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