PRODUCT BRIEF CHL8326/8 PRELIMINARY

DIGITAL MULTI-PHASE GPU BUCK CONTROLLER

FEATURES
 6-phase & 8-phase dual output PWM Controller
 Phases are flexibly assigned between Loops 1 & 2
 Intel® VR12, AMD® SVI/PVI/G34 & Memory modes
 Overclocking & Gaming Mode with Vmax setting
temperature sensing with VRHOT signal.
The CHL8326/8 also includes numerous features like
register diagnostics for fast design cycles and platform
differentiation, truly simplifying VRD design and enabling
fastest time-to-market with its “set-and-forget” methodology.

IRTN1

ISEN1

IRTN2

ISEN2

IRTN3

ISEN3

IRTN4

ISEN4

IRTN5

ISEN5

IRTN6

ISEN6
 Switching frequency from 200kHz to 1.2MHz per phase 48 47 46 45 44 43 42 41 40 39 38 37

 CHiL Efficiency Shaping Features including Variable RCSP 1 36 RCSP_L2

Gate Drive, Dynamic Phase Control RCSM 2 35 RCSM_L2

 Programmable 1-phase or 2-phase for Light Loads and VCC 3 34 VCC

CFP1 /
Active Diode Emulation for Very Light Loads VFIXEN_PSI2
4 33 VSEN_L2

 CHiL Adaptive Transient Algorithm (ATA) on both loops VSEN 5

CHL8326
32 VRTN_L2

minimizes output bulk capacitors and system cost VRTN 6

48 Pin 7x7 QFN
31 PWM6


RRES 7 30 PWM5
Designed for use with coupled inductors Top View
TSEN 8 29 PWM4

 Auto-Phase Detection with auto-compensation V18A 9 28 PWM3

 Per-Loop Fault Protection: OVP, UVP, OCP, OTP, CFP VR_READY1 /

PWRGD2
10 27 PWM2

 I2C/SMBus/PMBus system interface for telemetry of VR_READY_L212

/ PWROK 11 26 PWM1
49 GND
Temperature, Voltage, Current & Power for both loops VINSEN 12 25 VAR_GATE

 Non-Volatile Memory (NVM) for custom configuration 13 14 15 16 17 18 19 20 21 22 23 24

VR_HOT#1 /
VRHOT_ICRIT#2

SMB_DIO
GPO_A1 / CBOUT2

GPO_B_PSI1 /
VID[5]2

SV_ALERT1 / VID[4]2

SV_CLK1 / SVC_VID[3]2

SV_DIO1 / SVDVID[2]2

ENABLE

SMB_ALERT#

SMB_CLK

SV_ADDR_GPO_D1
/ VID[1]2
PM_ADDR_GPO_C1 /
PM_ADDRVID[0]2
 Compatible with CHiL ATL and 3.3V tri-state Drivers
 +3.3V supply voltage; 0ºC to 85ºC ambient operation
 Pb-Free, RoHS, 7x7 48 pin & 8x8 56 pin QFN packages

IRTN1

ISEN1

IRTN2

ISEN2

IRTN3

ISEN3

IRTN4

ISEN4

IRTN5

ISEN5

IRTN6

ISEN6
IRTN8

IRTN7
DESCRIPTION 56 55 54 53 52 51 50 49 48 47 46 45 44 43

The CHL8326/8 are dual-loop digital multi-phase buck ISEN8 1 42 ISEN7

controllers. The CHL8326 drives up to 6 phases and the RCSP 2 41 RCSP_L2

CHL8328 drives up to 8 phases. The CHL8326/8 is fully RCSM 3 40 RCSM_L2

Intel® VR12 and AMD® SVI/PVI compliant on both loops VCC 4 39 VCC

and provides a Vtt tracking function for DDR memory. CFP1 / 5 38 VSEN_L2
VFIXEN_PSI2

VSEN 6 37 VRTN_L2
NVM storage saves pins and enables a small package size. CHL8328
VRTN 7 36 PWM8
56 Pin 8x8 QFN
8 35
The CHL8326/8 includes the CHiL Efficiency Shaping RRES
Top View
PWM7

Technology to deliver exceptional efficiency at minimum TSEN 9 34 PWM6

cost across the entire load range. CHiL Variable Gate Drive V18A 10 33 PWM5

optimizes the MOSFET gate drive voltage based on real- VR_READY1 /

PWRGD2
11 32 PWM4

time load current. CHiL Dynamic Phase Control adds/drops VR_READY_L212

/ PWROK 12 31 PWM3

phases based upon load current. The CHL8326/8 can be GPO_B 13 30 PWM2
configured to enter 1-phase operation and active diode VINSEN 14
57 GND
29 PWM1
emulation mode automatically or by command.
15 16 17 18 19 20 21 22 23 24 25 26 27 28

CHiL’s unique Adaptive Transient Algorithm (ATA), based

TSEN2
VR_HOT#1 /
VRHOT_ICRIT#2

SMB_DIO
GPO_A1 / CBOUT2

PSI(MPoL)1 / VID[5]2

SV_ALERT1 / VID[4]2

SV_CLK1 / SVC_VID[3]2

SV_DIO1 / SVDVID[2]2

ENABLE

SMB_ALERT#

SMB_CLK

SV_ADDR_GPO_D1
/ VID[1]2
PM_ADDR_GPO_C1 /
PM_ADDR_VID[0]2

VAR_GATE

on proprietary non-linear digital PWM algorithms, minimizes 1

2
Intel/MPoL mode
AMD mode
output bulk capacitors. In addition, a coupled inductor mode,
with phases added/dropped in pairs, enables further
improvement in transient response and form factor.
Figure 1: CHL8326 & CHL8328 Packages
The I2C/PMBus interface can communicate with up to 16
CHL8326/8 based VR loops. Device configuration and fault APPLICATIONS
parameters are easily defined using the CHiL Intuitive
Power Designer (IPD) GUI and stored in on-chip NVM.  Intel® VR12 & AMD® SVI & PVI based systems
 DDR Memory with Vtt tracking
The CHL8326/8 provides extensive OVP, UVP, OCP and
OTP fault protection and includes thermistor based  Overclocked & Gaming platforms

Trademarks and registered trademarks are the property of the respective One Highwood Drive, Tewksbury, MA 01876
owners. Page 1 of 2 Tel: +1(978)-640-0011
PB0011 Rev. 0.05, June 10, 2010 www.chilsemi.com
© 2010 CHiL Semiconductor Corp. All rights reserved
 PRODUCT BRIEF CHL8326/8
DIGITAL MULTI-PHASE BUCK CONTROLLER

TYPICAL APPLICATIONS BLOCK DIAGRAM

12V

V
Boot CHL8510
Vcc HiGate V_CPU_L1
Rseries RCSP V_VGD HVCC Switch

V
LVCC
RTh CCS L
RCS PWM LoGate
GND O
Mode A
Rseries PWM1 D
RCSM ISEN1
+3.3V IRTN1
VCC 12V

V
Boot CHL8510
Vcc HiGate
V_VGD HVCC Switch

V
VSEN LVCC
PWM LoGate
VRTN GND Mode
PWM 2
RRES
ISEN2
IRTN2
TSEN 12V

V
RTh2

CHL8326/8 Boot CHL8510

Vcc HiGate
V_VGD HVCC Switch

V
V18A LVCC
PWM LoGate
GND Mode
PWM3
ISEN3
VR_RDY_L1 IRTN3
+12V Main
VR_RDY_L2 12V

V
RVIN_1
VINSEN Boot CHL8510
Vcc HiGate
RVIN_2 V_VGD HVCC Switch

V
LVCC
PWM LoGate
GND
Mode
PWM4
TSEN21 ISEN4
RTh2 IRTN4

PWM5
SV_ALERT# ISEN5
V

To/From SV_CLK IRTN5

V

CPU
SV_DIO
V

PWM6
ISEN6 Unused
VR_HOT# Phases
3.3V IRTN6

PWM71
CFP ISEN71
To/From GPO_A
IRTN71
System GPO_B1
PSI2

SMB_DIO
V

I2C or
SMB_CLK 12V
V
V

SMBus
SMB_ALERT
V

Boot CHL8510
Vcc HiGate V_CPU_L2
SV_ADDR V_VGD HVCC Switch
V

LVCC
PM_ADDR PWM LoGate L
1
GND Mode O
PWM8 A
D
ISEN81
RCSP_L2
Rseries IRTN81
CCS
RTh RCS

Rseries
RCSM_L2
12V
V

Boot CHL8510
Vcc HiGate
Notes HVCC Switch
VSEN_L2 LVCC
1
CHL8328 only VRTN_L2 VAR_GATE PWM LoGate V_VGD
GND
2 Mode
MPoL mode only GND
Only Intel/MPoL Mode pin names Optional Variable
shown Gate Drive Circuit

ORDERING INFORMATION

CHL832  -      Package Tape & Reel Qty Part Number

1
QFN 3000 CHL8326-00CRT
2
T: Tape & Reel QFN 3000 CHL8326-xxCRT
1
QFN 3000 CHL8328-00CRT
2
Package type QFN 3000 CHL8328-xxCRT
R : QFN
Notes
Operating Temperature 1 For unprogrammed/default parts, use
C: Commercial configuration file 00. Unprogrammed parts will not
Standard start up until programmed in order to insure a safe
Range
xx: Configuration file power up.
R : QFN 2 -xx indicates a customer specific configuration file.
Part
6: CHL8326
8: CHL8328 Page 2 of 2 PB0011
Rev. 0.05, June 10, 2010