Professional Documents
Culture Documents
Datasheet PIC18
Datasheet PIC18
Data Sheet
20-Pin Flash Microcontrollers
with nanoWatt XLP Technology
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
ISBN: 978-1-60932-280-9
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Comparators
Program Memory Data Memory
8-bit/16-bit
10-bit A/D
Channels
SR Latch
EUSART
Timers
MSSP
ECCP
Device Data Pins I/O(1)
SRAM
Bytes Words EEPROM
(bytes)
(bytes)
VDD 1 20 VSS
RA5/OSC1/CLKIN/T13CKI 2 19 RA0/AN0/CVREF/VREF-/C1IN+/INT0/PGD
RA4/AN3/OSC2/CLKOUT 3 18 RA1/AN1/C12IN0-/VREF+/INT1/PGC
PIC18F1XK22/
RA3/MCLR/VPP 4 17 RA2/AN2/C1OUT/T0CKI/INT2/SRQ
RC5/CCP1/P1A 5 16 RC0/AN4/C2IN+
LF1XK22
RC4/C2OUT/P1B/SRNQ 6 15 RC1/AN5/C12IN1-
RC3/AN7/C12IN3-/P1C/PGM 7 14 RC2/AN6/C12IN2-/P1D
RC6/AN8/SS 8 13 RB4/AN10/SDI/SDA
RC7/AN9/SDO 9 12 RB5/AN11/RX/DT
RB7/TX/CK 10 11 RB6/SCK/SCL
RA0/AN0/CVREF/VREF-/C1IN+/INT0/PGD
RA5/OSC1/CLKIN/T13CKI
RA4/AN3/OSC2/CLKOUT
VDD
VSS
20 19 18 17 16
RA3/MCLR/VPP 1 15 RA1/AN1/C12IN0-/VREF+/INT1/PGC
RC5/CCP1/P1A 2
-
14 RA2/AN2/C1OUT/T0CKI/INT2/SRQ
RC4/C2OUT/P1B/SRNQ 3
PIC18F1XK22/
13 RC0/AN4/C2IN+
RC3/AN7/C12IN3-/P1C/PGM 4 LF1XK22 12 RC1/AN5/C12IN1-
RC6/AN8/SS 5 11 RC2/AN6/C12IN2-/P1D
6 7 8 9 10
RB7/TX/CK
RB6/SCK/SCL
RB5/AN11/RX/DT
RC7/AN9/SDO
RB4/AN10/SDI/SDA
Comparator
20-Pin QFN
20-Pin DIL
Reference
Interrupts
SR Latch
EUSART
Analog
Pull-up
Timers
MSSP
ECCP
Basic
I/O
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include
literature number) you are using.
IR
8
Instruction State machine
Decode and control signals
Control
PRODH PRODL
PORTC
8 x 8 Multiply RC0
3 8 RC1
RC2
BITOP W RC3
Power-up 8 8 8
Internal RC4
OSC1(2) Oscillator Timer RC5
Block RC6
Oscillator 8 8
LFINTOSC RC7
(2) Start-up Timer
OSC2 Oscillator ALU<8>
Power-on
16 MHz Reset 8
Oscillator
MCLR(1)
Watchdog
Timer
Single-Supply
Precision FVR
VDD, VSS Programming Fail-Safe Band Gap
Clock Monitor Reference
Data
BOR EEPROM Timer0 Timer1 Timer2 Timer3
FVR FVR
ADC
CVREF Comparator ECCP1 MSSP EUSART 10-bit CVREF
QFN
DIL
RA0/AN0/CVREF/VREF-/C1IN+/INT0/PGD 19 16
RA0 I/O TTL Digital I/O
AN0 I Analog ADC channel 0
CVREF O Analog DAC reference voltage output
VREF- I Analog ADC and DAC reference voltage (low) input
C1IN+ I Analog Comparator C1 non-inverting input
INT0 I ST External interrupt 0
PGD I/O ST ICSP™ programming data pin
RA1/AN1/C12IN0-/VREF+/INT1/PGC 18 15
RA1 I/O TTL Digital I/O
AN1 I Analog ADC channel 1
C12IN0- 1 Analog Comparator C1 and C2 non-inverting input
VREF+ I Analog ADC and DAC reference voltage (high) input
INT1 I ST External interrupt 1
PGC I/O ST ICSP™ programming clock pin
RA2/AN2/C1OUT/T0CKI/INT2/SRQ 17 14
RA2 I/O ST Digital I/O
AN2 I Analog ADC channel 2
C1OUT — CMOS Comparator C1 output
T0CKI I ST Timer0 external clock input
INT2 I ST External interrupt 2
SRQ O CMOS SR latch output
RA3/MCLR/VPP 4 1
RA3 I ST Digital input
MCLR I ST Active-low Master Clear with internal pull-up
VPP P — High voltage programming input
RA4/AN3/OSC2/CLKOUT 3 20
RA4 I/O TTL Digital I/O
AN3 I Analog ADC channel 3
OSC2 O XTAL Oscillator crystal output. Connect to crystal or resonator
in Crystal Oscillator mode
CLKOUT O CMOS In RC mode, OSC2 pin outputs CLKOUT which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate
RA5/OSC1/CLKIN/T13CKI 2 19
RA5 I/O TTL Digital I/O
OSC1 I XTAL Oscillator crystal input or external clock input
ST buffer when configured in RC mode; analog other
wise
CLKIN I CMOS External clock source input. Always associated with the
pin function OSC1 (See related OSC1/CLKIN, OSC2,
CLKOUT pins
T13CKI I ST Timer0 and Timer3 external clock input
RB4/AN10/SDI/SDA 13 10
RB4 I/O TTL Digital I/O
AN10 I Analog ADC channel 10
SDI I ST SPI data in
SDA I/O ST I2C™ data I/O
RB5/AN11/RX/DT 12 9
RB5 I/O TLL Digital I/O
AN11 I Analog ADC channel 11
RX I ST EUSART asynchronous receive
DT I/O ST EUSART synchronous data (see related RX/TX)
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input I = Input
O = Output P = Power
XTAL= Crystal Oscillator
QFN
DIL
RB6/SCK/SCL 11 8
RB6 I/O TLL Digital I/O
SCK I/O ST Synchronous serial clock input/output for SPI mode
SCL I/O ST Synchronous serial clock input/output for I2C™ mode
RB7/TX/CK 10 7
RB7 I/O TLL Digital I/O
TX O CMOS EUSART asynchronous transmit
CK I/O ST EUSART synchronous clock (see related RX/DT)
RC0/AN4/C2IN+ 16 13
RC0 I/O ST Digital I/O
AN4 I Analog ADC channel 4
C2IN+ I Analog Comparator C2 non-inverting input
RC1/AN5/C12IN-/INT1 15 12
RC1 I/O ST Digital I/O
AN5 I Analog ADC channel 5
C12IN- I Analog Comparator C1 and C2 non-inverting input
INT1 I ST External interrupt 0
RC2/AN6/C12IN2-/P1D/INT2 14 11
RC2 I/O ST Digital I/O
AN6 I Analog ADC channel 6
C12IN2- I Analog Comparator C1 and C2 inverting input
P1D O CMOS Enhanced CCP1 PWM output
RC3/AN7/C12IN3-/P1C/PGM 7 4
RC3 I/O ST Digital I/O
AN7 I Analog ADC channel 7
C12IN3- I Analog Comparator C1 and C2 inverting input
P1C O CMOS Enhanced CCP1 PWM output
PGM I/O ST Low-Voltage ICSP Programming enable pin
RC4/C12OUT/P1B/SRQ 6 3
RC4 I/O ST Digital I/O
C12OUT O CMOS Comparator C1 and C2 output
P1B O CMOS Enhanced CCP1 PWM output
SRNQ O CMOS SR latch output
RC5/CCP1/P1A 5 2
RC5 I/O ST Digital I/O
CCP1 I/O ST Capture 1 input/Compare 1 output/PWM 1 output
P1A O CMOS Enhanced CCP1 PWM output
RC6/AN8/SS 8 5
RC6 I/O ST Digital I/O
AN8 I Analog ADC channel 8
SS I TTL SPI slave select input
RC7/AN9/SDO 9 6
RC7 I/O ST Digital I/O
AN9 I Analog ADC channel 9
SDO O CMOS SPI data out
VSS 20 17 P — Ground reference for logic and I/O pins
VDD 1 18 P — Positive supply for logic and I/O pins
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input I = Input
O = Output P = Power
XTAL= Crystal Oscillator
Primary
Oscillator, PIC18F1XK22/LF1XK22
External
and Timer1/Timer3
OSC1/T13CKI Secondary
Oscillator
Sleep
PCLKEN LP, XT, HS, RC, EC, IDLEN
PRI_SD 4 x PLL 1 Secondary Osc.
OSC2 0x Sleep
0
T1OSCEN FOSC<3:0> Peripherals
PLL_EN
PLLEN Internal Osc. System
MUX
1x
Clock
CPU
IRCF<2:0>
Sleep
16 MHz
8 MHz
Internal 110
Oscillator 4 MHz
Block 101
Postscaler
2 MHz
100 FOSC<3:0>
MUX
16 MHz Clock
1 MHz
HFINTOSC 011 Control SCS<1:0>
500 kHz
31 kHz 010
LFINTOSC 250 kHz
001
1 31 kHz
000
0
INTSRC
Fail-Safe
Clock
Watchdog
Timer Two-Speed
Start-up
LP Oscillator mode selects the lowest gain setting of the 2: Always verify oscillator performance over
internal inverter-amplifier. LP mode current consumption the VDD and temperature range that is
is the least of the three modes. This mode is best suited expected for the application.
to drive resonators with a low drive level specification, for 3: For oscillator design assistance, reference
example, tuning fork type crystals. the following Microchip Applications Notes:
XT Oscillator mode selects the intermediate gain • AN826, “Crystal Oscillator Basics and
setting of the internal inverter-amplifier. XT mode Crystal Selection for rfPIC® and PIC®
current consumption is the medium of the three modes. Devices” (DS00826)
This mode is best suited to drive resonators with a • AN849, “Basic PIC® Oscillator Design”
medium drive level specification. (DS00849)
HS Oscillator mode selects the highest gain setting of the • AN943, “Practical PIC® Oscillator
internal inverter-amplifier. HS mode current consumption Analysis and Design” (DS00943)
is the highest of the three modes. This mode is best • AN949, “Making Your Oscillator Work”
suited for resonators that require a high drive setting. (DS00949)
Figure 2-2 and Figure 2-3 show typical circuits for
quartz crystal and ceramic resonators, respectively.
VDD
PIC® MCU
REXT
OSC1/CLKIN Internal
Clock
CEXT
VSS
FOSC/4 or OSC2/CLKOUT(1)
I/O(2)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Old Clock
Start-up Time(1) Clock Sync Running
New Clock
System Clock
Old Clock
Start-up Time(1) Clock Sync Running
New Clock
System Clock
Note 1: Start-up time includes TOST (1024 TOSC) for external clocks, plus TPLL (approx. 2 ms) for HSPLL mode.
Sample Clock
System Oscillator
Clock Failure
Output
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
CONFIG1H IESO FCMEN PCLKEN PLL_EN FOSC3 FOSC2 FOSC1 FOSC0 263
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 257
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS HFIOFS SCS1 SCS0 258
OSCCON2 — — — — — PRI_SD HFIOFL LFIOFS 258
OSCTUNE INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 260
IPR2 OSCFIP C1IP C2IP EEIP BCLIP — TMR3IP — 260
PIE2 OSCFIE C1IE C2IE EEIE BCLIE — TMR3IE — 260
PIR2 OSCFIF C1IF C2IF EEIF BCLIF — TMR3IF — 260
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 258
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
Additional detailed information on the operation of the PIC18 devices have two interrupt vectors and one
Flash program memory is provided in Section 4.0 Reset vector. The Reset vector address is at 0000h
“Flash Program Memory”. Data EEPROM is and the interrupt vector addresses are at 0008h and
discussed separately in Section 5.0 “Data EEPROM 0018h.
Memory”. The program memory map for PIC18F1XK22/
LF1XK22 devices is shown in Figure 3-1. Memory
block details are shown in Figure 22-2.
FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F1XK22/LF1XK22 DEVICES
PC<20:0>
CALL,RCALL,RETURN 21
RETFIE,RETLW
Stack Level 1
Stack Level 31
PIC18F14K22/
LF14K22
1FFFFFh
200000h
11111
11110
Top-of-Stack Registers 11101 Stack Pointer
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
Q3 Phase
Clock
Q4
PC PC PC + 2 PC + 4
OSC2/CLKOUT
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC) Execute INST (PC)
Fetch INST (PC + 2) Execute INST (PC + 2)
Fetch INST (PC + 4)
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
3.2.4 TWO-WORD INSTRUCTIONS and used by the instruction sequence. If the first word
is skipped for some reason and the second word is
The standard PIC18 instruction set has four two-word
executed by itself, a NOP is executed instead. This is
instructions: CALL, MOVFF, GOTO and LSFR. In all
necessary for cases when the two-word instruction is
cases, the second word of the instruction always has
preceded by a conditional instruction that changes the
‘1111’ as its four Most Significant bits (MSb); the other
PC. Example 3-4 shows how this works.
12 bits are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction Note: See Section 3.6 “PIC18 Instruction
specifies a special form of NOP. If the instruction is Execution and the Extended Instruc-
executed in proper sequence – immediately after the tion Set” for information on two-word
first word – the data in the second word is accessed instructions in the extended instruction set.
When ‘a’ = 0:
BSR<3:0> Data Memory Map
The BSR is ignored and the
00h 000h Access Bank is used.
= 0000 Access RAM 05Fh
Bank 0 The first 96 bytes are
GPR 060h
FFh 0FFh general purpose RAM
00h 100h (from Bank 0).
= 0001
Bank 1 The second 160 bytes are
FFh 1FFh Special Function Registers
= 0010 00h 200h (from Bank 15).
Bank 2
FFh 2FFh When ‘a’ = 1:
= 0011 00h 300h
Bank 3 The BSR specifies the Bank
used by the instruction.
FFh 3FFh
00h 400h
= 0100 Bank 4
FFh 4FFh
= 0101 00h 500h
Bank 5
FFh 5FFh
= 0110 00h 600h
Bank 6
Access Bank
FFh 6FFh
= 0111 00h 700h 00h
Bank 7 Access RAM Low
5Fh
Unused
FFh 7FFh Access RAM High 60h
Read 00h 800h (SFRs)
= 1000 00h
Bank 8 FFh
FFh 8FFh
= 1001 00h 900h
Bank 9
FFh 9FFh
00h A00h
= 1010
Bank 10
FFh AFFh
= 1011 00h B00h
Bank 11
FFh BFFh
= 1100 00h C00h
Bank 12
FFh CFFh
= 1101 D00h
Bank 13 00h
FFh DFFh
00h E00h
= 1110
Bank 14
FFh EFFh
00h F00h
Unused
= 1111 F53h
Bank 15 SFR(1) F5Fh
F60h
FFh SFR FFFh
Note 1: SFRs occupying F53h to F5Fh address space are not in the virtual bank.
When ‘a’ = 0:
BSR<3:0> Data Memory Map
The BSR is ignored and the
00h 000h Access Bank is used.
= 0000 Access RAM 05Fh
Bank 0 The first 96 bytes are
GPR 060h
FFh 0FFh general purpose RAM
00h 100h (from Bank 0).
= 0001
Bank 1 GPR The second 160 bytes are
FFh 1FFh Special Function Registers
= 0010 00h 200h (from Bank 15).
Bank 2
FFh 2FFh When ‘a’ = 1:
= 0011 00h 300h
Bank 3 The BSR specifies the Bank
used by the instruction.
FFh 3FFh
00h 400h
= 0100 Bank 4
FFh 4FFh
= 0101 00h 500h
Bank 5
FFh 5FFh
= 0110 00h 600h
Bank 6
Access Bank
FFh 6FFh
= 0111 00h 700h 00h
Bank 7 Access RAM Low
5Fh
FFh 7FFh Access RAM High 60h
= 1000 00h 800h (SFRs)
Bank 8 FFh
Unused
FFh 8FFh
Read 00h
= 1001 00h 900h
Bank 9
FFh 9FFh
00h A00h
= 1010
Bank 10
FFh AFFh
= 1011 00h B00h
Bank 11
FFh BFFh
= 1100 00h C00h
Bank 12
FFh CFFh
= 1101 D00h
Bank 13 00h
FFh DFFh
00h E00h
= 1110
Bank 14
FFh EFFh
00h F00h
Unused
= 1111 F53h
Bank 15 SFR(1) F5Fh
F60h
FFh SFR FFFh
Note 1: SFRs occupying F53h to F5Fh address space are not in the virtual bank.
Bank 3
through
Bank 13
FFh
E00h
00h
Bank 14
F00h FFh
00h
Bank 15
FFFh FFh
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 259, 215
CCPR1H Capture/Compare/PWM Register 1, High Byte xxxx xxxx 259, 133
CCPR1L Capture/Compare/PWM Register 1, Low Byte xxxx xxxx 259, 133
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 259, 113
VREFCON2 — — — DAC1R4 DAC1R3 DAC1R2 DAC1R1 DAC1R0 ---0 0000 259, 246
VREFCON1 D1EN D1LPS DAC1OE --- D1PSS1 D1PSS0 — D1NSS 000- 00-0 259, 246
PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001 259, 130
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 0100 0-00 259, 190
PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 259, 129
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 259, 125
TMR3H Timer3 Register, High Byte xxxx xxxx 259, 109
TMR3L Timer3 Register, Low Byte xxxx xxxx 259, 109
T3CON RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0-00 0000 259, 109
SPBRGH EUSART Baud Rate Generator Register, High Byte 0000 0000 259, 191
SPBRG EUSART Baud Rate Generator Register, Low Byte 0000 0000 259, 191
RCREG EUSART Receive Register 0000 0000 259, 189
TXREG EUSART Transmit Register 0000 0000 259, 188
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 259, 188
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 259, 189
EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 259, 49,
59
EEDATA EEPROM Data Register 0000 0000 259, 49,
59
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 259, 49,
59
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 259, 49,
59
IPR2 OSCFIP C1IP C2IP EEIP BCLIP — TMR3IP — 1111 111- 260, 75
PIR2 OSCFIF C1IF C2IF EEIF BCLIF — TMR3IF — 0000 000- 260, 71
PIE2 OSCFIE C1IE C2IE EEIE BCLIE — TMR3IE — 0000 000- 260, 73
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP -111 1111 260, 74
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 260, 70
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 260, 72
OSCTUNE INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000 22, 260
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 260, 90
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx 260, 91
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 260, 90
PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- 260, 86
PORTA — — RA5 RA4 RA3 (2) RA2 RA1 RA0 --xx xxxx 260, 81
ANSELH — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 260, 95
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 260, 94
IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 260, 87
IOCA — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 260, 82
WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 260, 87
WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 257, 82
CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 1000 260, 227
CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 0000 0000 260, 228
CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 0000 1000 260, 228
SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 260, 241
SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 0000 0000 260, 240
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
000h
When ‘a’ = 0 and f 60h:
060h
The instruction executes in
Direct Forced mode. ‘f’ is inter- Bank 0
BSR
When ‘a’ = 1 (all values of f): 000h 00000000
FIGURE 3-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET
ADDRESSING
Example Situation:
ADDWF f, d, a 000h
FSR2H:FSR2L = 120h
Bank 0
Locations in the region
from the FSR2 pointer 100h
(120h) to the pointer plus Bank 1
120h
05Fh (17Fh) are mapped Window
17Fh 00h
to the bottom of the
Bank 1
Access RAM (000h-05Fh). 200h Bank 1 “Window”
Special File Registers at 5Fh
60h
F60h through FFFh are
mapped to 60h through Bank 2
FFh, as usual. SFRs
through
Bank 0 addresses below Bank 14
5Fh can still be addressed FFh
by using the BSR. Access Bank
F00h
Bank 15
F60h
SFRs
FFFh
Data Memory
Instruction: TBLRD*
Program Memory
Table Pointer(1)
Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Instruction: TBLWT*
Program Memory
(TBLPTR<MSBs>)
Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL
actually point to an address within the write block holding registers. The MSBs of the Table Pointer deter-
mine where the write block will eventually be written. The process for writing the holding registers to the
program memory array is discussed in Section 4.5 “Writing to Flash Program Memory”.
4.2 Control Registers The FREE bit allows the program memory erase oper-
ation. When FREE is set, an erase operation is initiated
Several control registers are used in conjunction with on the next WR command. When FREE is clear, only
the TBLRD and TBLWT instructions. These include the: writes are enabled.
• EECON1 register The WREN bit, when set, will allow a write operation.
• EECON2 register The WREN bit is clear on power-up.
• TABLAT register The WRERR bit is set by hardware when the WR bit is
• TBLPTR registers set and cleared when the internal programming timer
expires and the write operation is complete.
4.2.1 EECON1 AND EECON2 REGISTERS
Note: During normal operation, the WRERR is
The EECON1 register (Register 4-1) is the control read as ‘1’. This can indicate that a write
register for memory accesses. The EECON2 register is operation was prematurely terminated by
not a physical register; it is used exclusively in the a Reset, or a write operation was
memory write and erase sequences. Reading attempted improperly.
EECON2 will read all ‘0’s.
The EEPGD control bit determines if the access will be The WR control bit initiates write operations. The WR
a program or data EEPROM memory access. When bit cannot be cleared, only set, by firmware. Then WR
EEPGD is clear, any subsequent operations will bit is cleared by hardware at the completion of the write
operate on the data EEPROM memory. When EEPGD operation.
is set, any subsequent operations will operate on the Note: The EEIF interrupt flag bit of the PIR2
program memory. register is set when the write is complete.
The CFGS control bit determines if the access will be The EEIF flag stays set until cleared by
to the Configuration/Calibration registers or to program firmware.
memory/data EEPROM memory. When CFGS is set,
subsequent operations will operate on Configuration
registers regardless of EEPGD (see Section 22.0
“Special Features of the CPU”). When CFGS is clear,
memory selection access is determined by EEPGD.
Legend:
R = Readable bit W = Writable bit
S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.
TABLE 4-2: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example Operation on Table Pointer
TBLRD*
TBLPTR is not modified
TBLWT*
TBLRD*+
TBLPTR is incremented after the read/write
TBLWT*+
TBLRD*-
TBLPTR is decremented after the read/write
TBLWT*-
TBLRD+*
TBLPTR is incremented before the read/write
TBLWT+*
Program Memory
TABLAT
Write Register
8 8 8 8
Program Memory
Legend:
R = Readable bit W = Writable bit
S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.
6.2 Operation
Example 6-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 6-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the argu-
ments, each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
Wake-up if in
Idle or Sleep modes
TMR0IF
TMR0IE
TMR0IP
(1)
RABIF
RABIE
RABIP
INT0IF
INT0IE
Interrupt to CPU
INT1IF Vector to Location
INT1IE
INT1IP 0008h
SSPIF
SSPIE INT2IF
SSPIP INT2IE
INT2IP
ADIF GIEH/GIE
ADIE
ADIP IPEN
RCIF IPEN
RCIE GIEL/PEIE
RCIP
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
SSPIF
SSPIE
SSPIP
Interrupt to CPU
TMR0IF Vector to Location
TMR0IE 0018h
ADIF TMR0IP
ADIE (1)
ADIP RABIF
RABIE
RCIF RABIP GIEH/GIE
RCIE GIEL/PEIE
RCIP
INT1IF
INT1IE
INT1IP
Additional Peripheral Interrupts
INT2IF
INT2IE
INT2IP
Note 1: The RABIF interrupt also requires the individual pin IOCA and IOCB enable.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: A mismatch condition will continue to set the RABIF bit. Reading PORTA and PORTB will end the
mismatch condition and allow the bit to be cleared.
2: RA and RB port change interrupts also require the individual pin IOCA and IOCB enable.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The PSPIF bit is unimplemented on 28-pin devices and will read as ‘0’.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
RD TRIS
Q D
ENEN
RD Port
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0).
Otherwise, RA3 reads as ‘0’. This bit is read-only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 LATB<7:4>: RB<7:4> Port I/O Output Latch Register bits
bit 3-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 LATC<7:0>: RB<7:0> Port I/O Output Latch Register bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The slew rate of RA4 defaults to standard rate when the pin is used as CLKOUT.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
FOSC/4 0
0
Sync with Set
1 Internal TMR0L TMR0IF
Programmable Clocks on Overflow
T0CKI pin 1
Prescaler
T0SE (2 TCY Delay)
8
T0CS 3
T0PS<2:0>
8
PSA Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FOSC/4 0
0
Sync with Set
1 Internal TMR0
TMR0L High Byte TMR0IF
T0CKI pin Programmable 1 Clocks on Overflow
Prescaler 8
T0SE (2 TCY Delay)
T0CS 3 Read TMR0L
T0PS<2:0>
Write TMR0L
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
OSC1/T13CKI 1
Prescaler Synchronize
FOSC/4 0
1, 2, 4, 8 Detect
Internal
Clock 0
OSC2 2
Sleep Input
TMR1CS Timer1
INTOSC On/Off
Without CLKOUT
T1OSCEN(1)
T1CKPS<1:0>
T1SYNC
TMR1ON
TMR1 Set
Clear TMR1 TMR1L TMR1IF
High Byte
(CCP Special Event Trigger) on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
TMR1 Set
Clear TMR1 TMR1L TMR1IF
High Byte
(CCP Special Event Trigger) on Overflow
8
Read TMR1L
Write TMR1L
8
8
TMR1H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
4 1:1 to 1:16
T2OUTPS<3:0> Set TMR2IF
Postscaler
2
T2CKPS<1:0> TMR2 Output
(to PWM or MSSP)
TMR2/PR2
Reset Match
1:1, 1:4, 1:16
FOSC/4 TMR2 Comparator PR2
Prescaler
8 8
8
Internal Data Bus
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
T3CKPS<1:0>
T3SYNC
TMR3ON
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Read TMR1L
Write TMR1L
8
8
TMR3H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
The event is selected by the mode select bits, 13.2.4 CCP PRESCALER
CCP1M<3:0> of the CCP1CON register. When a cap-
There are four prescaler settings in Capture mode; they
ture is made, the interrupt request flag bit, CCP1IF, is
are specified as part of the operating mode selected by
set; it must be cleared by software. If another capture
the mode select bits (CCP1M<3:0>). Whenever the
occurs before the value in register CCPR1 is read, the
CCP module is turned off or Capture mode is disabled,
old captured value is overwritten by the new captured
the prescaler counter is cleared. This means that any
value.
Reset will clear the prescaler counter.
13.2.1 CCP PIN CONFIGURATION Switching from one capture prescaler to another may
In Capture mode, the appropriate CCP1 pin should be generate an interrupt. Also, the prescaler counter will
configured as an input by setting the corresponding not be cleared; therefore, the first capture may be from
TRIS direction bit. a non-zero prescaler. Example 13-1 shows the
recommended method for switching between capture
Note: If the CCP1 pin is configured as an output, prescalers. This example also clears the prescaler
a write to the port can cause a capture counter and will not generate the “false” interrupt.
condition.
EXAMPLE 13-1: CHANGING BETWEEN
13.2.2 TIMER1/TIMER3 MODE SELECTION CAPTURE PRESCALERS
The timers that are to be used with the capture feature CLRF CCP1CON ; Turn CCP module off
(Timer1 and/or Timer3) must be running in Timer mode MOVLW NEW_CAPT_PS ; Load WREG with the
or Synchronized Counter mode. In Asynchronous Coun- ; new prescaler mode
ter mode, the capture operation may not work. The timer ; value and CCP ON
MOVWF CCP1CON ; Load CCP1CON with
; this value
TMR3H TMR3L
Set CCP1IF
T3CCP1 TMR3
CCP1 pin Enable
Prescaler and CCPR1H CCPR1L
1, 4, 16 Edge Detect
TMR1
T3CCP1 Enable
4 TMR1H TMR1L
CCP1CON<3:0>
4
Q1:Q4
0 TMR1H TMR1L
Compare Output S Q
Comparator
Match Logic
R
TRIS
4 Output Enable
CCPR1H CCPR1L
CCP1CON<3:0>
FIGURE 13-3: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
DC1B<1:0> P1M<1:0> CCP1M<3:0>
Duty Cycle Registers
2 4
CCPR1L
CCP1/P1A CCP1/P1A
TRIS
CCPR1H (Slave)
P1B P1B
Output TRIS
Comparator R Q
Controller
P1C P1C
TMR2 (1)
S TRIS
P1D P1D
Comparator
Clear Timer2, TRIS
toggle PWM pin and
latch duty cycle
PR2 PWM1CON
Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit
time base.
Note 1: The TRIS register value for each PWM output must be configured appropriately.
2: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.
TABLE 13-2: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
ECCP Mode P1M<1:0> CCP1/P1A P1B P1C P1D
(1)
Single 00 Yes Yes(1) Yes(1) Yes(1)
Half-Bridge 10 Yes Yes No No
Full-Bridge, Forward 01 Yes Yes Yes Yes
Full-Bridge, Reverse 11 Yes Yes Yes Yes
Note 1: Outputs are enabled by pulse steering in Single mode. See Register 13-4.
P1A Active
P1D Modulated
P1A Inactive
P1D Inactive
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 13.4.6 “Programmable Dead-Band Delay
Mode”).
Pulse PR2+1
P1M<1:0> Signal 0
Width
Period
P1A Modulated
Delay(1) Delay(1)
10 (Half-Bridge) P1B Modulated
P1A Active
P1D Modulated
P1A Inactive
P1D Inactive
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 13.4.6 “Programmable Dead-Band Delay
Mode”).
FET
Driver +
P1A
-
Load
FET
Driver
+
P1B
-
V+
FET FET
Driver Driver
P1A
Load
FET FET
Driver Driver
P1B
FET QA QC FET
Driver Driver
P1A
Load
P1B
FET FET
Driver Driver
P1C
QB QD
V-
P1D
P1B(2)
P1C(2)
P1D(2)
(1) (1)
Reverse Mode
Period
Pulse Width
P1A(2)
P1B(2)
P1C(2)
P1D(2)
(1) (1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signal is shown as active-high.
P1A (Active-High)
P1B (Active-High)
Pulse Width
P1C (Active-High)
(2)
P1D (Active-High)
Pulse Width
Note 1: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The
modulated P1B and P1D signals are inactive at this time. The length of this time is (1/FOSC) TMR2 prescale
value.
P1A
P1B
PW
P1C
P1D PW
TON
External Switch C
TOFF
External Switch D
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
ECCPASE bit
PWM Activity
Normal PWM
ECCPASE
Cleared by
Start of Shutdown Shutdown Firmware PWM
PWM Period Event Occurs Event Clears Resumes
PWM Period
Shutdown Event
ECCPASE bit
PWM Activity
Normal PWM
FET
Driver +
P1A V
-
Load
FET
Driver
+
P1B V
-
V-
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> = 11 and
P1M<1:0> = 00.
PORT Data
0
TRIS
STRB
PORT Data 0
TRIS
STRC
1 P1C pin
CCP1M1
PORT Data 0
TRIS
STRD
PORT Data 0
TRIS
PWM Period
PWM
STRn
P1n = PWM
PWM
STRn
P1n = PWM
TABLE 13-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
Reset
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values
on page
CCPR1H Capture/Compare/PWM Register 1, High Byte 259
CCPR1L Capture/Compare/PWM Register 1, Low Byte 259
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 259
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 259
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 257
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 260
IPR2 OSCFIP C1IP C2IP EEIP BCLIP — TMR3IP — 260
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 260
PIE2 OSCFIE C1IE C2IE EEIE BCLIE — TMR3IE — 260
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 260
PIR2 OSCFIF C1IF C2IF EEIF BCLIF — TMR3IF — 260
PR2 Timer2 Period Register 258
PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 259
RCON IPEN SBOREN — RI TO PD POR BOR 258
TMR1H Timer1 Register, High Byte 258
TMR1L Timer1 Register, Low Byte 258
TMR2 Timer2 Register 258
TMR3H Timer3 Register, High Byte 259
TMR3L Timer3 Register, Low Byte 259
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 260
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 258
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 258
T3CON RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 259
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
SDI/SDA
SSPSR Reg
SDO bit 0 Shift
Clock
SS SS Control
Enable
Edge
Select
2
Clock Select
SSPM<3:0>
SCK/SCL
4 (TMR22Output)
Edge
Select Prescaler TOSC
4, 16, 64
TRIS bit
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Polarity of clock state is set by the CKP bit of the SSPCON1 register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
2: When enabled, these pins must be properly configured as input or output.
3: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.
Slave Select
General I/O SS
Processor 1 (optional) Processor 2
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI bit 0
(SMP = 0) bit 7 bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
SSPMSK Reg
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
Addr Match
receives a complete byte, it is transferred to SSPBUF
Match Detect
and the SSPIF interrupt is set.
SSPADD Reg During transmission, the SSPBUF is not
double-buffered. A write to SSPBUF will write to both
Start and Set, Reset SSPBUF and SSPSR.
Stop bit Detect S, P bits
(SSPSTAT Reg)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, these bits may not
be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
DS41365D-page 150
Receiving Address R/W = 0 Receiving Data ACK Receiving Data ACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF
Bus master
(PIR1<3>) terminates
transfer
PIC18F1XK22/LF1XK22
BF (SSPSTAT<0>)
Preliminary
Cleared by software
SSPBUF is read
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
SSPIF (PIR1<3>)
Bus master
terminates software
BF (SSPSTAT<0>)
Cleared by software Cleared by software
From SSPIF ISR From SSPIF ISR
SSPBUF is written by software SSPBUF is written by software
Preliminary
SSPBUF is read by software
CKP
DS41365D-page 151
FIGURE 14-10:
DS41365D-page 152
Clock is held low until Clock is held low until
update of SSPADD has update of SSPADD has
taken place taken place
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Bus master
terminates
SSPIF transfer
(PIR1<3>)
Cleared by software Cleared by software Cleared by software
Cleared by software
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
SSPOV is set
Preliminary
because SSPBUF is
still full. ACK is not sent.
UA (SSPSTAT<1>)
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S Sr P
SSPIF
BF
SSPBUF is written with Dummy read of SSPBUF Dummy read of SSPBUF Write of SSPBUF Completion of
Preliminary
contents of SSPSR to clear BF flag to clear BF flag Dummy read of SSPBUF data transmission
UA to clear BF flag clears BF flag
DS41365D-page 153
PIC18F1XK22/LF1XK22
14.3.3.4 SSP Mask Register This register must be initiated prior to setting
2 SSPM<3:0> bits to select the I2C Slave mode (7-bit or
An SSP Mask (SSPMSK) register is available in I C
10-bit address).
Slave mode as a mask for the value held in the
SSPSR register during an address comparison The SSP Mask register is active during:
operation. A zero (‘0’) bit in the SSPMSK register has • 7-bit Address mode: address compare of A<7:1>.
the effect of making the corresponding bit in the
• 10-bit Address mode: address compare of A<7:0>
SSPSR register a “don’t care”.
only. The SSP mask has no effect during the
This register is reset to all ‘1’s upon any Reset reception of the first (high) byte of the address.
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The MSK0 bit is used only in 10-bit Slave mode. In all other modes, this bit has no effect.
REGISTER 14-7: SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Master mode:
bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care.” Bit pat-
tern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are
compared by hardware and are not affected by the value in this register.
bit 2-1 ADD<9:8>: Two Most Significant bits of 10-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care.”
10-Bit Slave mode — Least Significant Address Byte:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA DX DX – 1
SCL
Master device
CKP asserts clock
Master device
deasserts clock
WR
SSPCON1
DS41365D-page 158
Clock is not held low
because buffer full bit is
clear prior to falling edge Clock is held low until Clock is not held low
of 9th clock CKP is set to ‘1’ because ACK = 1
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF
Bus master
(PIR1<3>) terminates
transfer
PIC18F1XK22/LF1XK22
BF (SSPSTAT<0>)
Preliminary
Cleared by software
SSPBUF is read
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
CKP
CKP
If BF is cleared written
prior to the falling to ‘1’ in
edge of the 9th clock, software
CKP will not be reset BF is set after falling
to ‘0’ and no clock edge of the 9th clock,
stretching will occur CKP is reset to ‘0’ and
clock stretching occurs
I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
SSPIF
Bus master
(PIR1<3>) terminates
Cleared by software Cleared by software Cleared by software transfer
Cleared by software
BF (SSPSTAT<0>)
SSPOV is set
Preliminary
because SSPBUF is
still full. ACK is not sent.
UA (SSPSTAT<1>)
DS41365D-page 159
PIC18F1XK22/LF1XK22
14.3.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is
SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
The addressing procedure for the I2C bus is such that
SSPIF interrupt flag bit is set.
the first byte after the Start condition usually
determines which device will be the slave addressed by When the interrupt is serviced, the source for the
the master. The exception is the general call address interrupt can be checked by reading the contents of the
which can address all devices. When this address is SSPBUF. The value can be used to determine if the
used, all devices should, in theory, respond with an address was device specific or a general call address.
Acknowledge. In 10-bit mode, the SSPADD is required to be updated
The general call address is one of eight addresses for the second half of the address to match and the UA
reserved for specific purposes by the I2C protocol. It bit of the SSPSTAT register is set. If the general call
consists of all ‘0’s with R/W = 0. address is sampled when the GCEN bit is set, while the
slave is configured in 10-bit Address mode, then the
The general call address is recognized when the
second half of the address is not necessary, the UA bit
GCEN bit of the SSPCON2 is set. Following a Start bit
will not be set and the slave will begin receiving data
detect, 8 bits are shifted into the SSPSR and the
after the Acknowledge (Figure 14-15).
address is compared against the SSPADD. It is also
compared to the general call address and fixed in
hardware.
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPIF
BF (SSPSTAT<0>)
Cleared by software
SSPBUF is read
SSPOV (SSPCON1<6>) ‘0’
GCEN (SSPCON2<7>)
‘1’
Internal SSPM<3:0>
Data Bus SSPADD<6:0>
Read Write
SSPBUF Baud
Rate
Generator
SDA Shift
Clock Arbitrate/WCOL Detect
SDA In Clock
SSPSR
(hold off clock source)
MSb LSb
Receive Enable
Acknowledge
Generate
SCL
SSPM<3:0> SSPADD<7:0>
SDA DX DX – 1
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
SCL
TBRG
S
Sr = Repeated Start
DS41365D-page 168
Write SSPCON2<0> SEN = 1 ACKSTAT in
Start condition begins SSPCON2 = 1
From slave, clear ACKSTAT bit SSPCON2<6>
SEN = 0
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0
of 10-bit Address ACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
Cleared by software
Preliminary
BF (SSPSTAT<0>)
PEN
R/W
I 2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
begin Start condition ACK from Master Set ACKEN, start Acknowledge sequence
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSPCON2<3> (RCEN = 1)
PEN bit = 1
Write to SSPBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave R/W = 0 Receiving Data from Slave Receiving Data from Slave
Bus master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSPIF at end
of receive Set SSPIF interrupt
Set SSPIF interrupt at end of Acknow-
Set SSPIF interrupt ledge sequence
at end of receive at end of Acknowledge
SSPIF sequence
Set P bit
Cleared by software Cleared by software Cleared by software Cleared by software (SSPSTAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU software and SSPIF
responds to SSPIF
BF
Preliminary
(SSPSTAT<0>) Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPOV
ACKEN
RCEN
I 2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
Master configured as a receiver RCEN cleared ACK from Master RCEN cleared
by programming SSPCON2<3> (RCEN = 1) automatically SDA = ACKDT = 0 automatically
PIC18F1XK22/LF1XK22
DS41365D-page 169
PIC18F1XK22/LF1XK22
14.3.12 ACKNOWLEDGE SEQUENCE 14.3.13 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDA pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable
Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSPCON2 register. At the end of a
SSPCON2 register. When this bit is set, the SCL pin is receive/transmit, the SCL line is held low after the
pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set,
are presented on the SDA pin. If the user wishes to gen- the master will assert the SDA line low. When the SDA
erate an Acknowledge, then the ACKDT bit should be line is sampled low, the Baud Rate Generator is
cleared. If not, the user should set the ACKDT bit before reloaded and counts down to ‘0’. When the Baud Rate
starting an Acknowledge sequence. The Baud Rate Generator times out, the SCL pin will be brought high
Generator then counts for one rollover period (TBRG) and one TBRG (Baud Rate Generator rollover count)
and the SCL pin is deasserted (pulled high). When the later, the SDA pin will be deasserted. When the SDA
SCL pin is sampled high (clock arbitration), the Baud pin is sampled high while SCL is high, the P bit of the
Rate Generator counts for TBRG. The SCL pin is then SSPSTAT register is set. A TBRG later, the PEN bit is
pulled low. Following this, the ACKEN bit is automatically cleared and the SSPIF bit is set (Figure 14-24).
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 14-23). 14.3.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
14.3.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the
If the user writes the SSPBUF when an Acknowledge contents of the buffer are unchanged (the write doesn’t
sequence is in progress, then WCOL is set and the occur).
contents of the buffer are unchanged (the write doesn’t
occur).
SCL 8 9
SSPIF
Cleared in
SSPIF set at software
the end of receive Cleared in
software SSPIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
SDA
BCLIF
SDA
SCL
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL = 1 SSP module reset into Idle state.
SEN
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
BCLIF SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared by software
SSPIF
TBRG TBRG
SDA
FIGURE 14-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSPIF
Less than TBRG
TBRG
SCL S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable START
sequence if SDA = 1, SCL = 1
BCLIF ‘0’
SSPIF
SDA = 0, SCL = 1, Interrupts cleared
set SSPIF by software
SDA
SCL
RSEN
BCLIF
Cleared by software
S ‘0’
SSPIF ‘0’
TBRG TBRG
SDA
SCL
S ‘0’
SSPIF
PEN
BCLIF
P ‘0’
SSPIF ‘0’
SDA
PEN
BCLIF
P ‘0’
SSPIF ‘0’
TXEN
TRMT SPEN
Baud Rate Generator FOSC
÷n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D
SYNC 1 X 0 0 0
SPBRGH SPBRG BRGH X 1 1 0 0
BRG16 X 1 0 1 0
BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPBRGH SPBRG BRGH X 1 1 0 0 FIFO
FERR RX9D RCREG Register
BRG16 X 1 0 1 0
8
Data Bus
RCIF Interrupt
RCIE
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RB7/TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Word 1
TRMT bit
Transmit Shift Reg
(Transmit Shift
Reg. Empty Flag)
Write to TXREG
Word 1 Word 2
BRG Output
(Shift Clock)
RB7/TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXIF bit 1 TCY Word 1 Word 2
(Interrupt Reg. Flag)
1 TCY
TRMT bit Word 1 Word 2
(Transmit Shift Transmit Shift Reg
Reg. Empty Flag) Transmit Shift Reg
• CREN = 1 Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
• SYNC = 0
to the EUSART receive FIFO and the RCIF interrupt
• SPEN = 1 flag bit of the PIR1 register is set. The top character in
All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the
their default state. RCREG register.
Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional
receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun
of the TXSTA register configures the EUSART for condition is cleared. See Section 15.1.2.6
asynchronous operation. Setting the SPEN bit of the “Receive Overrun Error” for more
RCSTA register enables the EUSART. The RX/DT I/O information on overrun errors.
pin must be configured as an input by setting the
corresponding TRIS control bit. If the RX/DT pin is 15.1.2.3 Receive Data Polarity
shared with an analog peripheral the analog I/O function The polarity of the receive data can be controlled with
must be disabled by clearing the corresponding ANSEL the DTRXP bit of the BAUDCON register. The default
bit. state of this bit is ‘0’ which selects high true receive idle
Note: When the SPEN bit is set the TX/CK I/O and data bits. Setting the DTRXP bit to ‘1’ will invert the
pin is automatically configured as an receive data resulting in low true idle and data bits. The
output, regardless of the state of the DTRXP bit controls receive data polarity only in
corresponding TRIS bit and whether or not Asynchronous mode. In Synchronous mode the
the EUSART transmitter is enabled. The DTRXP bit has a different function.
PORT latch is disconnected from the
output driver so it is not possible to use the
TX/CK pin as a general purpose output.
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
BAUD FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 12.000 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — — — —
9600 — — — 9600 0.00 119 9615 0.16 77 9600 0.00 71
10417 — — — 10378 -0.37 110 10417 0.00 71 10473 0.53 65
19.2k 19.23k 0.16 155 19.20k 0.00 59 19.23k 0.16 38 19.20k 0.00 35
57.6k 57.69k 0.16 51 57.60k 0.00 19 57.69k 0.16 12 57.60k 0.00 11
115.2k 115.38k 0.16 25 115.2k 0.00 9 — — — 115.2k 0.00 5
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
BAUD FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 12.000 MHz FOSC = 11.0592 MHz
RATE SPBRGH SPBRGH SPBRGH SPBRGH
Actual % Actual % Actual % Actual %
:SPBRG :SPBRG :SPBRG :SPBRG
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 9999 300.0 0.00 3839 300 0.00 2499 300.0 0.00 2303
1200 1200.1 0.00 2499 1200 0.00 959 1200 0.00 624 1200 0.00 575
2400 2400 0.00 1249 2400 0.00 479 2404 0.16 311 2400 0.00 287
9600 9615 0.16 311 9600 0.00 119 9615 0.16 77 9600 0.00 71
10417 10417 0.00 287 10378 -0.37 110 10417 0.00 71 10473 0.53 65
19.2k 19.23k 0.16 155 19.20k 0.00 59 19.23k 0.16 38 19.20k 0.00 35
57.6k 57.69k 0.16 51 57.60k 0.00 19 57.69k 0.16 12 57.60k 0.00 11
115.2k 115.38k 0.16 25 115.2k 0.00 9 — — — 115.2k 0.00 5
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRGH SPBRGH SPBRGH SPBRGH
Actual % Actual % Actual % Actual %
:SPBRG :SPBRG :SPBRG :SPBRG
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
BAUD FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 12.000 MHz FOSC = 11.0592 MHz
RATE SPBRGH SPBRGH SPBRGH SPBRGH
Actual % Actual % Actual % Actual %
:SPBRG :SPBRG :SPBRG :SPBRG
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300 0.00 39999 300.0 0.00 15359 300 0.00 9999 300.0 0.00 9215
1200 1200 0.00 9999 1200 0.00 3839 1200 0.00 2499 1200 0.00 2303
2400 2400 0.00 4999 2400 0.00 1919 2400 0.00 1249 2400 0.00 1151
9600 9600 0.00 1249 9600 0.00 479 9615 0.16 311 9600 0.00 287
10417 10417 0.00 1151 10425 0.08 441 10417 0.00 287 10433 0.16 264
19.2k 19.20k 0.00 624 19.20k 0.00 239 19.23k 0.16 155 19.20k 0.00 143
57.6k 57.69k 0.16 207 57.60k 0.00 79 57.69k 0.16 51 57.60k 0.00 47
115.2k 115.38k 0.16 103 115.2k 0.00 39 115.38k 0.16 25 115.2k 0.00 23
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRGH SPBRGH SPBRGH SPBRGH
Actual % Actual % Actual % Actual %
:SPBRG :SPBRG :SPBRG :SPBRG
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0.00 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —
BRG Clock
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
RCIF
Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’ ‘1’
TXEN bit
Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
RX/DT
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
NVCFG[1:0] = 00
AVSS
VREF- NVCFG[1:0] = 01
AVDD
PVCFG[1:0] = 00
VREF+ PVCFG[1:0] = 01
FVR PVCFG[1:0] = 10
AN0 0000
AN1 0001
AN2 0010
AN3 0011
AN4 0100
AN5 0101
AN6 0110
AN7 0111
ADC
AN8 1000
GO/DONE 10
AN9 1001
AN10 1010 0 = Left Justify
ADFM
AN11 1011 1 = Right Justify
Unused 1100 ADON 10
Unused 1101
VSS ADRESH ADRESL
DAC 1110
FVR 1111
CHS<3:0>
TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD) Device Frequency (FOSC)
ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 16-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 2 TAD
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Automatic
Acquisition Conversion starts Discharge
Time (Holding capacitor is disconnected from analog input)
Set GO bit
(Holding capacitor continues On the following cycle:
acquiring input) ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 5µs + T C + Temperature - 25°C 0.05µs/°C
1
V AP PLIE D 1 – ------------ = V CHOLD ;[1] VCHOLD charged to within 1/2 lsb
2047
–TC
----------
RC ;[2] VCHOLD charge response to VAPPLIED
V AP P LI ED 1 – e = V CHOLD
– Tc
---------
1
V AP P LIED 1 – e = V A P PLIE D 1 – ------------
RC
;combining [1] and [2]
2047
T C = – C HOLD R IC + R SS + R S ln(1/2047)
= – 13.5pF 1k + 700 + 10k ln(0.0004885)
= 1.20 µs
Therefore:
T ACQ = 5µs + 1.20µs + 50°C- 25°C 0.05µs/°C
= 7.45µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
VDD
Sampling
Switch
VT = 0.6V
Rs ANx RIC 1k SS Rss
Discharge VSS/VREF-
Switch
3.5V
Legend: CPIN = Input Capacitance 3.0V
VT = Threshold Voltage
VDD
2.5V
I LEAKAGE = Leakage current at the pin due to
various junctions 2.0V
RIC = Interconnect Resistance 1.5V
SS = Sampling Switch
CHOLD = Sample/Hold Capacitance .1 1 10 100
Rss (k)
Note 1: See Section 25.0 “Electrical Specifications”.
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
ADC Output Code
Full-Scale
004h Transition
003h
002h
001h
000h Analog Input Voltage
1/2 LSB ideal
C1CH<1:0>
2 To
D Q Data Bus
Q1
C12IN0- 0 EN
RD_CM1CON0
C12IN1- 1
MUX Set C1IF
D Q
C12IN2- 2
Q3*RD_CM1CON0
EN
C12IN3- 3 CL
NReset
C1ON(1)
C1R
C1VIN- -
C1IN+ 0 C1 C1OUT To PWM Logic
MUX C1VIN+
+
VREF 1
0 C1SP
MUX C1POL C1SYNC
FVR 1 C1VREF C1OE
0
C1RSEL
D Q 1 C1OUT
(4)
From TMR1L[0]
SYNCC1OUT
Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (FOSC).
3: Q1 is held high during Sleep mode.
4: Positive going pulse generated on both falling and rising edges of the bit.
To
D Q
Data Bus
Q1
EN
RD_CM2CON0
C2CH<1:0> Set C2IF
2 D Q
Q3*RD_CM2CON0
EN
C12IN0- 0 C2ON(1)
CL
C12IN1- 1 NRESET
MUX C2VIN-
C12IN2- 2 C2 C2OUT To PWM Logic
C2VIN+
C12IN3- 3 C2SP
C2SYNC
C2POL C20E
C2R
C2OUT pin
0
C2IN+ 0
MUX D Q 1
VREF 1 (4)
0 From TMR1L[0] SYNCC2OUT
MUX
FVR 1 C2VREF
C2RSEL
Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (FOSC).
3: Q1 is held high during Sleep mode.
4: Positive going pulse generated on both falling and rising edges of the bit.
The CxCH<1:0> bits of the CMxCON0 register direct CxVIN- > CxVIN+ 1 1
one of four analog input pins to the comparator CxVIN- < CxVIN+ 1 0
inverting input.
17.2.6 COMPARATOR SPEED SELECTION
Note: To use CxIN+ and C12INx- pins as analog
inputs, the appropriate bits must be set in The trade-off between speed or power can be opti-
the ANSEL register and the corresponding mized during program execution with the CxSP control
TRIS bits must also be set to disable the bit. The default state for this bit is ‘1’ which selects the
output drivers. normal speed mode. Device power consumption can
be optimized at the cost of slower comparator propaga-
17.2.3 COMPARATOR REFERENCE tion delay by clearing the CxSP bit to ‘0’.
SELECTION
17.3 Comparator Response Time
Setting the CxR bit of the CMxCON0 register directs an
internal voltage reference or an analog input pin to the The comparator output is indeterminate for a period of
non-inverting input of the comparator. See time after the change of an input source or the selection
Section 20.0 “VOLTAGE REFERENCES” for more of a new reference voltage. This period is referred to as
information on the Internal Voltage Reference module. the response time. The response time of the
comparator differs from the settling time of the voltage
17.2.4 COMPARATOR OUTPUT reference. Therefore, both of these times must be
SELECTION considered when determining the total response time
The output of the comparator can be monitored by to a comparator input change. See the Comparator and
reading either the CxOUT bit of the CMxCON0 register Voltage Reference Specifications in Section 25.0
or the MCxOUT bit of the CM2CON1 register. In order “Electrical Specifications” for more details.
to make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding port
TRIS bit = 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port
TRIS bit = 0.
VT 0.6V RIC
Rs < 10K
AIN
CPIN ILEAKAGE(1)
VA VT 0.6V
5 pF
Vss
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter PC PC + 2
OSC1
TOST(1) TPLL(1)
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4 PC + 6
Counter
Wake Event OSTS bit set
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Q1 Q2 Q3 Q4 Q1
OSC1
CPU Clock
Peripheral
Clock
Program PC PC + 2
Counter
FIGURE 18-4: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1 Q2 Q3 Q4
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program PC
Counter
Wake Event
TABLE 18-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source Clock Source Clock Ready Status
Exit Delay
before Wake-up after Wake-up Bit (OSCCON)
LP, XT, HS
Primary Device Clock HSPLL OSTS
TCSD(1)
(PRI_IDLE mode) EC, RC
HFINTOSC(2) IOSF
LP, XT, HS TOST(3)
HSPLL TOST + tPLL(3) OSTS
T1OSC or LFINTOSC(1)
EC, RC TCSD(1)
HFINTOSC(1) TIOBST(4) IOSF
LP, XT, HS TOST(4)
HSPLL TOST + tPLL(3) OSTS
HFINTOSC(2)
EC, RC TCSD(1)
HFINTOSC(1) None IOSF
LP, XT, HS TOST(3)
None HSPLL TOST + tPLL(3) OSTS
(Sleep mode) EC, RC TCSD(1)
HFINTOSC(1) TIOBST(4) IOSF
Note 1: TCSD is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other
required delays (see Section 18.4 “Idle Modes”). On Reset, HFINTOSC defaults to 1 MHz.
2: Includes both the HFINTOSC 16 MHz source and postscaler derived frequencies.
3: TOST is the Oscillator Start-up Timer. tPLL is the PLL Lock-out Timer (parameter F12).
4: Execution continues during the HFINTOSC stabilization period, TIOBST.
INT1
SRSPE S Q SRQ pin(3)
SRCLK
SRSCKE
SYNCC2OUT(4)
SRSC2E
SYNCC1OUT(4) SR
SRSC1E
Latch(1)
SRPR Pulse
Gen(2)
INT1
SRRPE R Q SRNQ pin(3)
SRCLK
SRRCKE SRLEN
SYNCC2OUT(4) SRNQEN
SRRC2E
SYNCC1OUT(4)
SRRC1E
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
The voltage reference module provides an internally 20.1.2 OUTPUT VOLTAGE SELECTION
generated voltage reference for the comparators and
The VREF voltage reference has 32 voltage level
the DAC module. The following features are available:
ranges. The 32 levels are set with the DAC1R<4:0>
• Independent from comparator operation bits of the VREFCON2 register.
• Single 32-level voltage ranges The VREF output voltage is determined by the following
• Output clamped to VSS equations:
• Ratiometric with VDD
• 1.024V Fixed Voltage Reference (FVR)
The VREFCON1 register (Register 20-2) controls the
Voltage Reference module shown in Figure 20-1.
V OUT = V SOURCE +
IF D1EN = 0 & D1LPS = 1 & DAC1R[4:0] = 00000:
V OUT = V SOURCE -
D1PSS<1:0> = 00
VDD DAC1R<4:0>
D1PSS<1:0> = 01
VREF+
D1PSS<1:0> = 10
FVR1 R
R 16-to-1 MUX
32 Steps
VREF
R
DAC1OE
R
D1EN CVREF pin
R
D1LPS
D1NSS = 1
VREF-
D1NSS = 0
FVR1S<1:0> 2
X1
X2 FVR
X4
FVR1EN +
1.024V Fixed
FVR1ST _ Reference
PIC18F1XK22/
LF1XK22
CVREF
R(1)
Module
+
Voltage CVREF Buffered CVREF Output
–
Reference
Output
Impedance
Note 1: R is dependent upon the voltage reference Configuration bits, CVR<3:0> and CVRR.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The output select bits are always right justified to ensure that any number of bits can be used without
affecting the register layout.
External Reset
MCLRE
MCLR
( )_IDLE
Sleep
WDT
Time-out
OST/PWRT
OST(2) 1024 Cycles
Chip_Reset
10-bit Ripple Counter R Q
OSC1
32 s
PWRT(2) 65.5 ms
LFINTOSC 11-bit Ripple Counter
Enable PWRT
Enable OST(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2)
HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC
EC, ECIO 66 ms(1) — —
RC, RCIO 66 ms(1) — —
INTIO1, INTIO2 66 ms(1) — —
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 21-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 21-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 21-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
PLL TIME-OUT
INTERNAL RESET
TABLE 21-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
Program RCON Register STKPTR Register
Condition
Counter SBOREN RI TO PD POR BOR STKOVF STKUNF
Power-on Reset 0000h 1 1 1 1 0 0 0 0
RESET Instruction 0000h u(2) 0 u u u u u u
(2)
Brown-out Reset 0000h u 1 1 1 u 0 u u
MCLR during Power-Managed 0000h u(2) u 1 u u u u u
Run Modes
MCLR during Power-Managed 0000h u(2) u 1 0 u u u u
Idle Modes and Sleep Mode
WDT Time-out during Full Power 0000h u(2) u 0 u u u u u
or Power-Managed Run Mode
MCLR during Full Power 0000h u(2) u u u u u u u
Execution
Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u
Stack Underflow Reset 0000h u(2) u u u u u u 1
(STVREN = 1)
Stack Underflow Error (not an 0000h u(2) u u u u u u 1
actual Reset, STVREN = 0)
WDT Time-out during PC + 2 u(2) u 0 0 u u u u
Power-Managed Idle or Sleep
Modes
Interrupt Exit from PC + 2(1) u(2) u u 0 u u u u
Power-Managed Modes
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN<1:0> Configuration bits = 01 and SBOREN = 1). Otherwise, the Reset state is ‘0’.
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
Note 1: See Section 26.1 “DC Characteristics: Supply Voltage” for specifications.
2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently
controlled.
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
Note 1: BKBUG is only used for ICD device. Otherwise, this bit is unimplemented and reads as ‘1’.
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode.
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
Legend:
R = Readable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed C = Clearable only bit
Note 1: These values for DEV<10:3> may be shared with other devices. The specific device is always identified
by using the entire DEV<10:0> bit sequence.
WDTPS<3:0> 4
Sleep
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
22.3 Program Verification and Figure 22-2 shows the program memory organization
Code Protection for 8, 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
The overall structure of the code protection on the locations of the bits are summarized in Table 22-3.
PIC18 Flash devices differs significantly from other
PIC® microcontroller devices.
The user program memory is divided into five blocks.
One of these is a boot block of 0.5K or 2K bytes,
depending on the device. The remainder of the mem-
ory is divided into individual blocks on binary boundar-
ies.
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Device
Address (from/to) 14K22 13K22
BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0
0000h Boot Block, 4 KB Boot Block, 2 KB Boot Block, 2 KB Boot Block, 1 KB CPB,
03FFh CPB, WRTB, EBTRB CPB, WRTB, EBTRB CPB, WRTB, EBTRB WRTB, EBTRB
0400h Block 0
07FFh 1.512 KB
0800h Block 0 Block 0 CP0, WRT0, EBTR0
0BFFh 6 KB 2 KB
0C00h CP0, WRT0, EBTR0 CP0, WRT0, EBTR0
0FFFh
1000h Block 0 Block 1 Block 1
1FFFh 4 KB 4 KB 4 KB
CP0, WRT0, EBTR0 CP1, WRT1, EBTR1 CP1, WRT1, EBTR1
2000h Block 1 Block 1 Reads all ‘0’s Reads all ‘0’s
3FFFh 8 KB 8 KB
CP1, WRT1, EBTR1 CP1, WRT1, EBTR1
4000h Reads all ‘0’s Reads all ‘0’s
4FFEh
5000h
5FFEh
6000h
6FFEh
7000h
7FFEh
8000h
8FFEh
9000h
9FFEh
A000h
AFFEh
B000h
BFFEh
C000h
CFFEh
D000h
DFFEh
E000h
EFFEh
F000h
FFFEh
H000h
HFFEh
Note: Refer to the test section for requirements on test memory mapping.
22.3.1 PROGRAM MEMORY instruction that executes from a location outside of that
CODE PROTECTION block is not allowed to read and will result in reading ‘0’s.
Figures 22-3 through 22-5 illustrate table write and table
The program memory may be read to or written from
read protection.
any location using the table read and table write
instructions. The device ID may be read with table Note: Code protection bits may only be written to
reads. The Configuration registers may be read and a ‘0’ from a ‘1’ state. It is not possible to
written with the table read and table write instructions. write a ‘1’ to a bit in the ‘0’ state. Code pro-
In normal execution mode, the CPn bits have no direct tection bits are only set to ‘1’ by a full chip
effect. CPn bits inhibit external reads and writes. A block erase or block erase function. The full chip
of user memory may be protected from table writes if the erase and block erase functions can only
WRTn Configuration bit is ‘0’. The EBTRn bits control be initiated via ICSP or an external
table reads. For a block of user memory with the EBTRn programmer.
bit cleared to ‘0’, a table READ instruction that executes
from within that block is allowed to read. A table read
TBLPTR = 0008FFh
WRT0, EBTR0 = 01
007FFFh
000000h
WRTB, EBTRB = 11
0007FFh
000800h
TBLPTR = 0008FFh
WRT0, EBTR0 = 10
001FFFh
002000h
PC = 003FFEh TBLRD* WRT1, EBTR1 = 11
003FFFh
004000h
WRT2, EBTR2 = 11
005FFFh
006000h
WRT3, EBTR3 = 11
007FFFh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
007FFFh
All bit-oriented instructions have three operands: The Instruction Set Summary, shown in Table 23-2,
lists the standard instructions recognized by the
1. The file register (specified by ‘f’) Microchip Assembler (MPASMTM).
2. The bit in the file register (specified by ‘b’)
Section 23.1.1 “Standard Instruction Set” provides
3. The accessed memory (specified by ‘a’) a description of each instruction.
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register
designator ‘f’ represents the number of the file in which
the bit is located.
Literal operations
15 8 7 0
OPCODE k (literal) MOVLW 7Fh
Control operations
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal) GOTO Label
15 12 11 0
1111 n<19:8> (literal)
15 8 7 0
OPCODE S n<7:0> (literal) CALL MYFUNC
15 12 11 0
1111 n<19:8> (literal)
S = Fast bit
15 11 10 0
OPCODE n<10:0> (literal) BRA MYFUNC
15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2
ADDWFC f, d, a Add WREG and CARRY bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1, 2
CLRF f, a Clear f 1 0110 101a ffff ffff Z 2
COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2
CPFSEQ f, a Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None 4
CPFSGT f, a Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None 4
CPFSLT f, a Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2
DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4
DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2
INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4
INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2
IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2
MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1
MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None
fd (destination) 2nd word 1111 ffff ffff ffff
MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None
MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2
NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N
RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2
RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N
RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N
RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N
SETF f, a Set f 1 0110 100a ffff ffff None 1, 2
SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N
borrow
SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N
borrow
SWAPF f, d, a Swap nibbles in f 1 0011 10da ffff ffff None 4
TSTFSZ f, a Test f, skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2
XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
BIT-ORIENTED OPERATIONS
BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2
BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2
BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4
BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4
BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2
CONTROL OPERATIONS
BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None
BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None
BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None
BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None
BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None
BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None
BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None
BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None
BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None
CALL k, s Call subroutine 1st word 2 1110 110s kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD
DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C
GOTO k Go to address 1st word 2 1110 1111 kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
NOP — No Operation 1 0000 0000 0000 0000 None
NOP — No Operation 1 1111 xxxx xxxx xxxx None 4
POP — Pop top of return stack (TOS) 1 0000 0000 0000 0110 None
PUSH — Push top of return stack (TOS) 1 0000 0000 0000 0101 None
RCALL n Relative Call 2 1101 1nnn nnnn nnnn None
RESET Software device Reset 1 0000 0000 1111 1111 All
RETFIE s Return from interrupt enable 2 0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None
RETURN s Return from Subroutine 2 0000 0000 0001 001s None
SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
LITERAL OPERATIONS
ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N
ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N
IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N
LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None
to FSR(f) 1st word 1111 0000 kkkk kkkk
MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None
MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None
MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None
RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None
SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N
XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD* Table Read 2 0000 0000 0000 1000 None
TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None
TBLRD*- Table Read with post-decrement 0000 0000 0000 1010 None
TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None
TBLWT* Table Write 2 0000 0000 0000 1100 None
TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None
TBLWT*- Table Write with post-decrement 0000 0000 0000 1110 None
TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write to
register ‘f’ Data destination
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set
Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a}
Operands: 0 f 255 Operands: 0 f 255
0b7 0b<7
a [0,1] a [0,1]
Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1
Status Affected: None Status Affected: None
Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff
Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the the next instruction fetched during the
current instruction execution is discarded current instruction execution is discarded
and a NOP is executed instead, making and a NOP is executed instead, making
this a two-cycle instruction. this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default). GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in set is enabled, this instruction operates
Indexed Literal Offset Addressing in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). mode whenever f 95 (5Fh).
See Section 23.2.3 “Byte-Oriented and See Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details. Literal Offset Mode” for details.
Words: 1 Words: 1
Cycles: 1(2) Cycles: 1(2)
Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed
by a 2-word instruction. by a 2-word instruction.
Q Cycle Activity: Q Cycle Activity:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read Process No Decode Read Process No
register ‘f’ Data operation register ‘f’ Data operation
If skip: If skip:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
No No No No No No No No
operation operation operation operation operation operation operation operation
If skip and followed by 2-word instruction: If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
No No No No No No No No
operation operation operation operation operation operation operation operation
No No No No No No No No
operation operation operation operation operation operation operation operation
CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W
Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a}
Operands: 0 f 255 Operands: 0 f 255
a [0,1] a [0,1]
Operation: (f) –W), Operation: (f) –W),
skip if (f) > (W) skip if (f) < (W)
(unsigned comparison) (unsigned comparison)
Status Affected: None Status Affected: None
Encoding: 0110 010a ffff ffff
Encoding: 0110 000a ffff ffff
Description: Compares the contents of data memory
Description: Compares the contents of data memory
location ‘f’ to the contents of the W by
location ‘f’ to the contents of W by
performing an unsigned subtraction.
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
If the contents of ‘f’ are less than the
contents of WREG, then the fetched
contents of W, then the fetched
instruction is discarded and a NOP is
instruction is discarded and a NOP is
executed instead, making this a
executed instead, making this a
two-cycle instruction.
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates Words: 1
in Indexed Literal Offset Addressing Cycles: 1(2)
mode whenever f 95 (5Fh). See
Note: 3 cycles if skip and followed
Section 23.2.3 “Byte-Oriented and by a 2-word instruction.
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details. Q Cycle Activity:
Words: 1 Q1 Q2 Q3 Q4
Cycles: 1(2) Decode Read Process No
Note: 3 cycles if skip and followed register ‘f’ Data operation
by a 2-word instruction. If skip:
Q Cycle Activity: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 No No No No
Decode Read Process No operation operation operation operation
register ‘f’ Data operation If skip and followed by 2-word instruction:
If skip: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 No No No No
No No No No operation operation operation operation
operation operation operation operation No No No No
If skip and followed by 2-word instruction: operation operation operation operation
Q1 Q2 Q3 Q4
No No No No
Example: HERE CPFSLT REG, 1
operation operation operation operation NLESS :
No No No No LESS :
operation operation operation operation
Before Instruction
PC = Address (HERE)
Example: HERE CPFSGT REG, 0 W = ?
NGREATER : After Instruction
GREATER :
If REG < W;
Before Instruction PC = Address (LESS)
PC = Address (HERE) If REG W;
W = ? PC = Address (NLESS)
After Instruction
If REG W;
PC = Address (GREATER)
If REG W;
PC = Address (NGREATER)
Q1 Q2 Q3 Q4 Q Cycle Activity:
Decode Read Process Write to Q1 Q2 Q3 Q4
register ‘f’ Data destination Decode Read Process Write to
If skip: register ‘f’ Data destination
Q1 Q2 Q3 Q4 If skip:
No No No No Q1 Q2 Q3 Q4
operation operation operation operation No No No No
If skip and followed by 2-word instruction: operation operation operation operation
Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction:
No No No No Q1 Q2 Q3 Q4
operation operation operation operation No No No No
No No No No operation operation operation operation
operation operation operation operation No No No No
operation operation operation operation
Example: HERE DECFSZ CNT, 1, 1
GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0
CONTINUE ZERO :
NZERO :
Before Instruction
PC = Address (HERE) Before Instruction
After Instruction TEMP = ?
CNT = CNT - 1 After Instruction
If CNT = 0; TEMP = TEMP – 1,
PC = Address (CONTINUE) If TEMP = 0;
If CNT 0; PC = Address (ZERO)
PC = Address (HERE + 2) If TEMP 0;
PC = Address (NZERO)
POP Pop Top of Return Stack PUSH Push Top of Return Stack
Syntax: POP Syntax: PUSH
Operands: None Operands: None
Operation: (TOS) bit bucket Operation: (PC + 2) TOS
Status Affected: None Status Affected: None
Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101
Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of
stack and is discarded. The TOS value the return stack. The previous TOS
then becomes the previous value that value is pushed down on the stack.
was pushed onto the return stack. This instruction allows implementing a
This instruction is provided to enable software stack by modifying TOS and
the user to properly manage the return then pushing it onto the return stack.
stack to incorporate a software stack.
Words: 1
Words: 1
Cycles: 1
Cycles: 1 Q Cycle Activity:
Q Cycle Activity: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Decode PUSH No No
Decode No POP TOS No PC + 2 onto operation operation
operation value operation return stack
RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry
Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}}
Operands: 0 f 255 Operands: 0 f 255
d [0,1] d [0,1]
a [0,1] a [0,1]
Operation: (f<n>) dest<n + 1>, Operation: (f<n>) dest<n – 1>,
(f<7>) dest<0> (f<0>) C,
Status Affected: N, Z (C) dest<7>
Status Affected: C, N, Z
Encoding: 0100 01da ffff ffff
Encoding: 0011 00da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated
is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the CARRY
stored back in register ‘f’ (default). flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘a’ is ‘0’, the Access Bank is selected. If ‘d’ is ‘1’, the result is placed back in
If ‘a’ is ‘1’, the BSR is used to select the register ‘f’ (default).
GPR bank (default). If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘1’, the BSR is used to select the
set is enabled, this instruction operates GPR bank (default).
in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction
mode whenever f 95 (5Fh). See set is enabled, this instruction operates
Section 23.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing
Bit-Oriented Instructions in Indexed mode whenever f 95 (5Fh). See
Literal Offset Mode” for details. Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
register f
Literal Offset Mode” for details.
Words: 1 C register f
Cycles: 1
Words: 1
Q Cycle Activity:
Cycles: 1
Q1 Q2 Q3 Q4
Decode Read Process Write to Q Cycle Activity:
register ‘f’ Data destination Q1 Q2 Q3 Q4
Decode Read Process Write to
Example: RLNCF REG, 1, 0 register ‘f’ Data destination
Before Instruction
REG = 1010 1011 Example: RRCF REG, 0, 0
After Instruction Before Instruction
REG = 0101 0111 REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 0111 0011
C = 0
ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return
Syntax: ADDFSR f, k Syntax: ADDULNK k
Operands: 0 k 63 Operands: 0 k 63
f [ 0, 1, 2 ] Operation: FSR2 + k FSR2,
Operation: FSR(f) + k FSR(f) (TOS) PC
Status Affected: None Status Affected: None
Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk
Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then
Words: 1 executed by loading the PC with the
Cycles: 1 TOS.
The instruction takes two cycles to
Q Cycle Activity:
execute; a NOP is performed during
Q1 Q2 Q3 Q4 the second cycle.
Decode Read Process Write to This may be thought of as a special
literal ‘k’ Data FSR case of the ADDFSR instruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
Example: ADDFSR 2, 23h Words: 1
Before Instruction Cycles: 2
FSR2 = 03FFh
After Instruction
Q Cycle Activity:
FSR2 = 0422h
Q1 Q2 Q3 Q4
Decode Read Process Write to
literal ‘k’ Data FSR
No No No No
Operation Operation Operation Operation
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2
Syntax: MOVSS [zs], [zd] Syntax: PUSHL k
Operands: 0 zs 127 Operands: 0k 255
0 zd 127
Operation: k (FSR2),
Operation: ((FSR2) + zs) ((FSR2) + zd) FSR2 – 1 FSR2
Status Affected: None
Status Affected: None
Encoding:
Encoding: 1110 1010 kkkk kkkk
1st word (source) 1110 1011 1zzz zzzzs
2nd word (dest.) 1111 xxxx xzzz zzzzd Description: The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2. FSR2
Description The contents of the source register are
is decremented by 1 after the operation.
moved to the destination register. The
This instruction allows users to push values
addresses of the source and destination
onto a software stack.
registers are determined by adding the
7-bit literal offsets ‘zs’ or ‘zd’, Words: 1
respectively, to the value of FSR2. Both
Cycles: 1
registers can be located anywhere in
the 4096-byte data memory space Q Cycle Activity:
(000h to FFFh). Q1 Q2 Q3 Q4
The MOVSS instruction cannot use the Decode Read ‘k’ Process Write to
PCL, TOSU, TOSH or TOSL as the data destination
destination register.
If the resultant source address points to
an indirect addressing register, the Example: PUSHL 08h
value returned will be 00h. If the
resultant destination address points to Before Instruction
an indirect addressing register, the FSR2H:FSR2L = 01ECh
Memory (01ECh) = 00h
instruction will execute as a NOP.
Words: 2 After Instruction
Cycles: 2 FSR2H:FSR2L = 01EBh
Memory (01ECh) = 08h
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Determine Determine Read
source addr source addr source reg
Decode Determine Determine Write
dest addr dest addr to dest reg
SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return
Syntax: SUBFSR f, k Syntax: SUBULNK k
Operands: 0 k 63 Operands: 0 k 63
f [ 0, 1, 2 ] Operation: FSR2 – k FSR2
Operation: FSR(f) – k FSRf (TOS) PC
Status Affected: None Status Affected: None
Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk
Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the
the contents of the FSR specified by contents of the FSR2. A RETURN is then
‘f’. executed by loading the PC with the TOS.
Words: 1 The instruction takes two cycles to
execute; a NOP is performed during the
Cycles: 1
second cycle.
Q Cycle Activity: This may be thought of as a special case of
Q1 Q2 Q3 Q4 the SUBFSR instruction, where f = 3 (binary
Decode Read Process Write to ‘11’); it operates only on FSR2.
register ‘f’ Data destination Words: 1
Cycles: 2
Q Cycle Activity:
Example: SUBFSR 2, 23h
Before Instruction Q1 Q2 Q3 Q4
FSR2 = 03FFh Decode Read Process Write to
register ‘f’ Data destination
After Instruction
FSR2 = 03DCh No No No No
Operation Operation Operation Operation
5.5
3.6
VDD (V)
2.7
1.8
0 10 20 40 48 64
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 25-2 for each Oscillator mode’s supported frequencies.
5.5
3.6
VDD (V)
2.7
1.8
0 10 20 40 48 64
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 25-2 for each Oscillator mode’s supported frequencies.
3.6
VDD (V)
2.7
1.8
0 10 20 40 48 64
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 25-2 for each Oscillator mode’s supported frequencies.
3.6
VDD (V)
2.7
1.8
0 10 20 40 48 64
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 25-2 for each Oscillator mode’s supported frequencies.
125
± 5%
85
3%
Temperature (°C)
60
25 ± 2%
0
-20 ± 5%
-40
1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VDD
VPOR
VPORR
VSS
NPOR
POR REARM
VSS
TVLOW(2) TPOR(3)
— 20 45 63 A 5.0
Power-down Module Current
D028 — .46 1.3 9.5 A 1.8 LPWDT Current(1)
— .74 2.25 10.5 A 3.0
D028 — 20 44 60 A 1.8 LPWDT Current(1)
— 21 46 63 A 3.0
— 22 48 65 A 5.0
D029 — 12 20 28 A 1.8 FVR Current (3)
— 14 22 30 A 3.0
D029 — 30 60 75 A 1.8 FVR Current(3)
— 50 70 85 A 3.0
— 70 105 135 A 5.0
D030 — 12 21 23 A 3.0 BOR Current(1, 3)
D030 — 30 55 80 A 3.0 BOR Current(1, 3)
— 64 100 120 A 5.0
D031 — .65 — — A 1.8 T1OSC Current(1)
— 1.8 — — A 3.0
D031 — 18 42 57 A 1.8 T1OSC Current(1)
— 20 44 61 A 3.0
— 22 46 64 A 5.0
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled.
4: A/D oscillator source is FRC.
— 22 46 64 A 5.0
D033 — 20 30 35 A 1.8 Comparator Current, low power
— 22 32 35 A 3.0 C1 and C2 enabled
TH01 JA Thermal Resistance Junction to Ambient 62.4 C/W 20-pin PDIP package
85.2 C/W 20-pin SOIC package
108.1 C/W 20-pin SSOP package
40 C/W 20-pin QFN 4x4mm package
TH02 JC Thermal Resistance Junction to Case 31.4 C/W 20-pin PDIP package
24 C/W 20-pin SOIC package
24 C/W 20-pin SSOP package
2.5 C/W 20-pin QFN 4x4mm package
TH03 TJMAX Maximum Junction Temperature 150 C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/O I/O Power Dissipation — W PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)
Legend: TBD = To Be Determined
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature.
3: TJ = Junction Temperature.
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O PORT t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
Pin CL
VSS
Q4 Q1 Q2 Q3 Q4 Q1
OSC1/CLKIN
OS02
OS04 OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
FOSC
OS11 OS12
OS20
CLKOUT OS21
OS19 OS16 OS18
OS13 OS17
I/O pin
(Input)
OS15 OS14
I/O pin Old Value New Value
(Output)
OS18, OS19
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31/
34 31A
34
I/O pins
VDD
VBOR and VHYST
VBOR
TBORREJ
37
Reset
33(1)
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. 2ms
delay if PWRTE = 0.
T0CKI
40 41
42
T1CKI
45 46
47 49
TMR0 or
TMR1
CC01 CC02
CC03
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK 132
ADIF TCY
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
Param
Sym. Characteristics Min. Typ. Max. Units Comments
No.
CM01 VIOFF Input Offset Voltage — ±7.5 ±50 mV High Power Mode
— — ±80 mV Low Power Mode
CM02 VICM Input Common Mode Voltage 0 — VDD V
CM03 CMRR Common Mode Rejection Ratio 55 — — dB
CM04 TRESP Response Time — 150 400 ns Note 1
CM05 TMC2OV Comparator Mode Change to — — 10 s
Output Valid*
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions
from VSS to VDD.
Param
Sym. Characteristics Min. Typ. Max. Units Comments
No.
DAC01* CLSB Step Size(2) — VDD/32 — V
DAC02* CACC Absolute Accuracy — — 1/2 LSb
DAC03* CR Unit Resistor Value (R) — TBD —
DAC04* CST Settling Time(1) — — 10 s
* These parameters are characterized but not tested.
Legend: TBD = To Be Determined
Note 1: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’.
Param
Sym. Characteristics Min. Typ. Max. Units Comments
No.
D003 VADFVR Fixed Voltage Reference Voltage for -6 — 4 % 1.024V, VDD 1.8V, 85°C
ADC, Initial Accuracy -7 — 4 1.024V, VDD 1.8V, 125°C
-7 — 6 2.048V, VDD 2.5V, 85°C
-8 — 6 2.048V, VDD 2.5V, 125°C
-7 — 4 4.096V, VDD 4.75V, 85°C
-8 — 4 4.096V, VDD 4.75V, 125°C
D003C* TCVFVR Temperature Coefficient, Fixed Volt- — -130 — ppm/°C
age Reference
D003D* VFVR/ Line Regulation, Fixed Voltage Ref- — 0.270 — %/V
VIN erence
D004* SVDD VDD Rise Rate to ensure internal 0.05 — — V/ms See Section 6.1 “Power-on
Power-on Reset signal Reset (POR)” for details.
* These parameters are characterized but not tested.
CK
US121 US121
DT
US120 US122
CK
US125
DT
US126
SS
SP70
SCK
(CKP = 0)
SP71 SP72
SP78 SP79
SCK
(CKP = 1)
SP79 SP78
SP80
SP75, SP76
SP74
SP73
SS
SP81
SCK
(CKP = 0)
SP71 SP72
SP79
SP73
SCK
(CKP = 1)
SP80
SP78
SP75, SP76
SP74
SS
SP70
SCK SP83
(CKP = 0)
SP71 SP72
SP78 SP79
SCK
(CKP = 1)
SP79 SP78
SP80
SP74
SP73
SP82
SS
SP70
SCK SP83
(CKP = 0)
SP71 SP72
SCK
(CKP = 1)
SP80
SP77
SP75, SP76
SDI
MSb In bit 6 - - - -1 LSb In
SP74
SCL
SP91 SP93
SP90 SP92
SDA
Start Stop
Condition Condition
SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated
Setup time 400 kHz mode 600 — — Start condition
SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first
Hold time 400 kHz mode 600 — — clock pulse is generated
SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
* These parameters are characterized but not tested.
SCL
SP90
SP106
SP107
SP91 SP92
SDA
In
SP110
SP109
SP109
SDA
Out
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Wake-up on Break ............................................................ 196
Watchdog Timer (WDT) ............................................ 261, 271
Associated Registers ................................................ 272
Control Register ........................................................ 272
Programming Considerations ................................... 271
Specifications............................................................ 354
WCOL ....................................................... 165, 166, 167, 170
WCOL Status Flag .................................... 165, 166, 167, 170
WDTCON Register ........................................................... 272
WPUA Register ................................................................... 82
WPUB Register ................................................................... 87
WWW Address.................................................................. 385
WWW, On-Line Support ....................................................... 7
X
XORLW ............................................................................. 317
XORWF............................................................................. 318
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01/05/10