Hierarchy of I/O Control Devices

2 Port (A,B),
8155 No
Bidirectional
I/O + Timer HS mode (C)
4 mode timer

8253/54 8255 2 Port (A,B)

6 mode timer A is Bidirectional
Timer I/O HS mode (C)
Extra controls

8259 8251
8237
Interrupt controller Serial I/O USART
DMA controller
controller
• Asynchronous Communication
• 8251 USART Architecture
• USART Registers
• Programming UART
• RS 232 Port
• Interfacing CRT Monitor using a UART and RS-
232 port
 Data
• Serial Transmission
– Cheaper
– Slower
• Parallel
– Faster Parallel Serial
– Data skew
– Limited to small distances

Synchronous ASynchronous
 Transmission Gaps

Sender a Data Data Data Receiver

Asynchronous transmission
CLK

Sender Data Data Data Data Data Receiver

Synchronous transmission
• Character oriented
• Each character carried start bit and stop bits
• When No data are being transmitted
– Receiver stay at logic 1 called mark, logic 0 is Space
• Framing:
– Transmission begins with one start bit (low/0)
– Followed by DATA (8bit) and
– Stop bits (1 or 2 bits of logic high)
1 start Asynchronous transmission 1 or 2 Stop
bit Source data bit

1 0 0 0 1 1 1 0
LSB MSB

Start Bit Time Start Bits

8 bit Data
• Serial Input Data (SID)
• Serial Output Data (SOD)
– Instruction SIM is necessary to output data
– Interpretations (ACC contents)
D7 D6 D5 D4 D3 D2 D1 D0
SOD SDE (0/1 X For interrupts
Dis/Ena SOD)

MVI A, 80 ; Set D7 in the ACC=1

RAR ;Set D6 =1 and bring carry into D7
SIM ; output D7
• Transmit an ASCII Char stored in Register B

MVI B ASCIIDatabyte ; get data byte in B

MVI C,0BH ; set up counter for 11 bits
XRA A ; reset carry to 0
NXTbit: MVI A,80H ;set D7=1 in ACC
RAR ;bring Carry in D7 and set D6=1
SIM ;output D7
CALL DELAYBittime ;wait for fixed time (BWT)
STC ;set Carry 1
MOV A,B ;Place ASIII car in acc
RAR ; place ASCII D0 in Carry
;and shift 1 in D7
MOV B,A ;Save B
DCR C
JNZ NXTbit
RET
• Programmable chip 8251
• Requirement of HW control serial I/O
– An input/output port are required for interfacing
– Converts data bits in to Parallel to serial & vice
versa
– Data transfer to be synchronized between I/O
– USART (Universal Synchronous Asynchronous
Receiver and Transmitter )
• Writing a program compatible with all different serial
communication protocols is difficult and it is an
inefficient use of microprocessor.
• UART: Universal Asynchronous Receiver/Transmitter
chip.
• USART: Universal Synchronous/Asynchronous
Receiver/Transmitter chip.
• The microprocessor sends/receives the data to the
UART in parallel, while with I/O, the UART
transmits/receive data serially.
• 8251 functions are integrated into standard PC
interface chip.
 status
CPU (8 bit)
xmit/
8251
rcv
data serial
(8 bit) port

• UART/USART
• 8251 USART
• 8250/16450 UART is a newer version of 8251.
• 16550 is the latest version UART.
D7-D0 Data Bus Transmit
Buffer Buffer TXD
I
n
t
RESET TXRDY
R/W e
CLK Transmit
C/Db
Control r TXE
RDb Control
n TXC
WRb Logic
CSb a
l
DSRb
DTRb Modem L Receive RXD
CTSb Control Buffer
RTSb
i
n
e

Receive RXRDY
Control RXC
SYBDET/BD
CSb C/Db RDb WRb Meaning
1 X X X Data Bus Tri-state
0 X 1 1 Data Bus Tri-state
0 1 0 1 Status  CPU
0 1 1 0 Control Word CPU
0 0 0 1 Data  CPU (accept data
from Data Buffer)
0 0 1 0 Data  CPU (Out put data
to Data buffer)
 I
n Transmitter
D7-D0 Data Buffer t
register e
r
C/Db=0 n
RDb or WRb a
Control l
Register
RESET C/Db=1 16 bit D
CLK R/W WRb=0
C/Db a
Control t
RDb Receiver
Logic C/Db=1 a
WRb
RDb=0 Status
CSb
Register
B
8 bit
u
s
 I Out put
n TxD
Register
t Transmitter
D0 Data e Buffer TxCb
Buffer r Register Transmitter
Register n TxRDY
Control Logic
D7 a TxE
l

D
a Input
t Register RxD
a Receiver
Buffer
B Register
Receiver RxCb
u Control Logic
s RxRDY
 D7 D6 D5 D4 D3 D2 D1 D0
Framing Control
# of Stop bits
Character length Baud Rate
00: invalid
01: 1 bit Parity Control 00: 5 bits 00: Syn. Mode
10: 1.5 bits X0=No Parity 01: 6 bits 01: x1 clock
11: 2 bits 01: Even 10: 7 bits 10: x16 clock
11: Odd 11: 8 bits 11: x64 clock
 EH IR RTS ER SBRK RxE DTR TxE

TxE: transmit enable (0/1 Enable Disable)

DTR: data terminal ready (1=ENABLE DTR)
RxE: receiver enable (1/0=EN/DISABLE)
SBPRK: send break character 1= force TxD low
ER: error reset (Reset Flags: Parity ,Over run,
Framing Error of Status Word)
RTS: request to send (1= Enable Request to send)
IR: internal reset (Reset 8251 to mode)
EH: enter hunt mode (1=search for Sync Character)
 SYN Tx
DSR FE OE PE RxRDY TxRDY
DET EMPTY
TxRDY transmit ready (DB Buffer is empty)
RxRDY receiver ready
TxEMPTY transmitter empty
PE parity error (1=when PE detected)
OE overrun error
FE framing error (Aynsc only, Valid stop bit
not detected)
SYNDET sync. character detected
DSR data set ready (DSR set at 0 level)
 RS-232 Cable

Transmit 2 Receive
2
Data Data
Terminal Communication
Equipment 3 Equipment
3
Receive Transmit
(DTE) (DCE)
CPU 7 I/O
7
3V +9V +9V +3V
0.2V -9V -9V -0.2V

• RS232: Data transmitted as Voltage to terminal

– 20KBps, 50Mters only
– Improved to RS 422A (9 pine), RS 423A (15 pin-VGA)
• Modem (Data transmitted by Frequency)
 D7 D6 D5 D4 D3 D2 D1 D0
Mode 1 1 0 0 1 0 1 0 CAH
Word
Two Stop bits No parity 7 bit characters Baud=TxC/16
=153.6k/16
=9600

D7 D6 D5 D4 D3 D2 D1 D0
COMMAND X 0 X 1 X 0 X 1 11H
WORD ERR Receive Transmit
Reset Disable Enable

D7 D6 D5 D4 D3 D2 D1 D0
X X X X X X X 1 01H
STATUS
Transmit
Ready