IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO.
1, JANUARY 2001
1-V 9-Bit Pipelined Switched-Opamp ADC
Mikko Waltari, Student Member, IEEE, and Kari A. I. Halonen
Abstract—A 9-bit 1.0-V pipelined analog-to-digital converter
has been designed using the switched-opamp technique. The de-
veloped low-voltage circuit blocks are a multiplying analog-to-dig-
ital converter (MADC), an improved common-mode feedback cir-
cuit for a switched opamp, and a fully differential comparator. The
input signal for the converter is brought in using a novel passive
interface circuit. The prototype chip, implemented in a 0.5- m
CMOS technology, has differential nonlinearity and integral non-
linearity of 0.6 and 0.9 LSB, respectively, and achieves 50.0-dB
SNDR at 5-MHz clock rate. As the supply voltage is raised to 1.5 V,
the clock frequency can be increased to 14 MHz. The power con-
sumption from a 1.0-V supply is 1.6 mW.
Index Terms—Analog-to-digital conversion, CMOS analog inte-
grated circuits, comparators, low power, low voltage, operational
amplifiers, switched-opamp circuits.
I. INTRODUCTION
T HE GROWING market of portable devices and the tech-
nology scaling are driving the supply voltages of digital
circuits down to 1.2 V by 2004 and to 0.9 V by 2008, according
to the Semiconductor Industry Association’s roadmap [1]. At
the same time, the migration toward system-on-a-chip (SoC)
adds pressure on the analog circuits to follow that trend. Its ben-
efits to the circuit performance, however, are questionable, be-
cause decreasing the supply voltage of the analog circuits meets
challenges such as reduced signal-to-noise ratio due to the de-
creased signal swing and the limited number of low-voltage-ca-
pable circuit topologies. In addition to the low-voltage prob-
lems, things like substrate noise and a long design cycle may
keep the most of the analog blocks off the digital die for a
long time. The A/D and D/A interface, however, is often ad-
vantageous to integrate together with the digital subsystem and
hence its implementation has to comply with the technology
constraints.
CMOS analog-to-digital converters (ADCs) implemented
in current mode techniques have been demonstrated to be
capable of operating with supply voltages of 1.5 V and below
[2], [3]. The current-mode circuits, however, seem to have
limited linearity especially in higher signal frequencies. The
switched capacitor (SC) technique, which inherently has a
good linearity, has been widely employed in pipelined ADCs
operating on supply voltages above 2.5 V, but the insufficient
switch overdrive prevents using it for low-voltage applications
in its standard form. Fortunately, there are at least three dif-
ferent approaches to overcome the switch driving problem. The
first is to use low transistors as switches, which, however,
Manuscript received March 10, 2000; revised July 7, 2000. This work was
supported by the Technology Development Centre of Finland (TEKES) and
Nokia Mobile Phones, Inc.
The authors are with the Electronic Circuit Design Laboratory, Helsinki Uni-
versity of Technology, 02150 Espoo, Finland.
Publisher Item Identifier S 0018-9200(01)00441-3.
0018–9200/01$10.00 © 2001 IEEE
129
requires a special technology and may suffer from leakage
of the stored charge. Locally boosting the switch-transistor
gate voltage above the supply with a charge-pump circuit has
been used, e.g., in [4]. Long-term reliability problems, due
to exceeding the technology specifications for the maximum
voltage, have formerly been associated with these circuits,
but recently a bootstrapped switch which does not violate
the process constraints has been used to implement a 1.5-V
pipelined ADC [5].
The third low-voltage SC technique is the switched-opamp
(SO) technique. It is based on the observation that in the con-
ventional SC circuits, the switches suffering from insufficient
voltage overdrive are connected to the output of an opamp; all
the other switches operate around a constant voltage level that
can be adjusted to be suitable for the switches. In the SO circuits,
the problematic switches are removed and their function is real-
ized by allowing to “switch off” the opamp, i.e., allowing to turn
its output stage into a high-impedance state. The resultant cir-
cuits are capable of sub-1-V operation. The SO technique was
first introduced in [6] and further developed in [7] by making
the circuit fully differential and separating the input and output
common-mode levels. The reported SO circuits include filters
[6], [7], modulators [8], [9], and a pipelined ADC [10]. It
is not obvious whether the SO technique or the switch boosting
is a better method to achieve the low-voltage operation with SC
circuits, since both of them increase the circuit complexity and
the internal capacitive loads.
This paper describes a switched-opamp implementation
of a pipelined ADC. The overall converter architecture is
similar to the authors’ previous work [10], but most of the
circuit blocks have been redesigned to achieve more robust and
less power-consuming realization. The prototype circuit also
features a high-speed front-end interface implemented with a
passive circuit.
II. PIPELINE ARCHITECTURE
The ADC is realized with the standard 1.5-bits-per-stage
pipeline architecture [11] where the 0.5-b redundancy in each
stage is used for digital correction to relax the requirement
for the comparator offsets. A block diagram of the 9-b ADC
is shown in Fig. 1. Each pipeline stage performs a coarse (in
this case, three level) A/D conversion for its input signal and
passes the amplified quantization error to the next stage. The
quantization error (or residue) is formed by converting the
quantization result back to the analog form and subtracting it
from the input signal. The residue formation and its precise
amplification are performed by a multiplying digital-to-analog
converter (MDAC).
The operation of the pipeline stage consists of two phases,
each lasting half a clock cycle. In the first phase, the MDAC
130
Fig. 1. Block diagram of the realized ADC.
samples the input signal and the sub-ADC does the A/D conver-
sion. During the second phase, the MDAC generates and ampli-
fies the residue yielding the input signal for the next stage. The
successive stages operate in opposite phases and thus the con-
version of a sample traverses two stages in a clock cycle.
There is a total of seven stages like the one whose block di-
agram is shown in the inset of Fig. 1. Since the last stage does
not need to generate a residue, it is implemented as a 2-b flash
ADC consisting of three comparators and few logic gates. The
external signal is taken into the pipeline through an input stage,
which is described in Section V.
III. MULTIPLYING DIGITAL-TO-ANALOG CONVERTER
The developed fully differential SO MDAC is shown in Fig. 2.
In contrast to its SC counterpart, the feedback capacitors are
permanently connected around the amplifier and the input ca-
pacitors to the output of the preceding stage. Due to this, the
maximum achievable feedback factor for the MDAC in a 1.5-
bits-per-stage architecture is 1/4 while being 1/2 in the SC real-
ization, which makes the SO circuit inherently slower than the
SC one.
To understand the circuit operation, let us first have a look
at the dc common-mode voltage levels in the circuit. The vir-
tual ground at the opamp input is set to , which is a suit-
able operating point for an opamp with nMOS input transistors.
The voltage level is kept unchanged when switching to the sam-
pling phase by shorting the opamp inputs to . To maximize
the voltage swing, the signal at the opamp output is centered in
the middle of the supply rails. During the sampling phase, the
opamp output is in a high-impedance state and pulled to by
the attached switches. As a result, there is change in the
voltage level when switching from one phase to the other. Since
the MDAC input is connected to the output of the preceding
stage, its voltage levels follow a similar pattern, but in the op-
posite phase.
In the sampling phase—when the clock is high—the inputs
are sampled to the -valued input capacitors. At the same time,
the signal voltages on the reference and the feedback capaci-
tors are reset. When entering into the amplification phase, the
switches at the opamp inputs and outputs are opened. Slightly
later, the preceding stage pulls the MDAC inputs to . With
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 1, JANUARY 2001
Fig. 2. Fully differential switched-opamp MDAC.
the aid of the virtual ground, the sampled signal charge in the
input capacitors is transferred into the feedback capacitors, re-
sulting an output voltage that is the input voltage multiplied by
the capacitor ratio.
The DAC function is realized with the -valued capacitors
that are connected to either or according to the
two-bit binary code produced by the stage’s sub ADC. The DAC
output, which is added to the sampled voltage, has three possible
output values: , , and . The first two are achieved
by connecting both the capacitors to the same reference voltage,
while to get the zero they are connected to the opposite volt-
ages. The advantage of this two-capacitor DAC compared to
a DAC with a single -valued capacitor [10] is the fact that
the common-mode level for the zero code is the same as for the
other codes. This eliminates the extra switched capacitor usually
needed in SO circuits to compensate the common-mode level
change between the two operating modes.
The minimum supply voltage for the MDAC depends on the
gate–source voltage needed to properly turn on the switch tran-
sistors and the values of the reference voltages. The reference
voltages in turn determine the full-scale signal amplitude which
is equal to the signal swing at the opamp output. This requires
that the reference levels have to be set at least a saturation
voltage apart from the supply rails.
IV. OPAMP
To get any signal swing from a low-voltage opamp, it has
to have a rail-to-rail output stage, which excludes such popular
single-stage opamp topologies as the folded cascode. Thus, typ-
ically the opamps employed in low-voltage SC circuits rely on
the traditional Miller topology [6], [8], [10] or a folded input
stage followed by a rail-to-rail output stage [5], [7]. The opamp
employed in this design and shown in Fig. 3 is based on the latter
architecture. Cascode compensation and an nMOS input stage
are used in order to maximize the bandwidth. Achieving the re-
quired phase margin is relatively easy since the feedback factor
in the MDAC configuration is 1/4.
The minimum supply voltage for the amplifier is .
Biasing all the transistors in the moderate inversion region
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 1, JANUARY 2001
Fig. 3. Designed two-stage switched-opamp.
Fig. 4. Common-mode feedback circuit.
allows to squeeze this minimum below 1 V in the technology
used.
What makes the amplifier a switched-opamp is the switch
S1 between the output stage pMOS current sources and .
Opening the switch allows external circuitry to pull the amplifier
output to . circuit, which is due to the lack of a series switch. When the SO
The common-mode feedback in a two-stage amplifier is al-
ways more complicated than in a single-stage one. This is due
to the fact that the common-mode voltage sensed at the output
of the amplifier cannot be directly applied to the gate of any
current source transistor in the first stage since it has the wrong
polarity. In [12], the need for an inverter circuit is avoided by
designing the input stage in such a way that it does not require
a common-mode feedback. Here the common-mode feedback
is realized by controlling the first-stage bias current with a pair
of pMOS transistors (M10 and M11) connected to the cascode
nodes. This configuration slightly degrades the amplifier noise
properties which, however, is not critical in this design.
The common-mode feedback (CMFB) is implemented with
the passive circuit shown in Fig. 4. The common-mode voltage
at the amplifier output is sensed with the capacitive divider con-
sisting of capacitors C1 and C2. During the amplifier-off phase,
its outputs are pulled to , while during the amplification
phase the desired output common-mode level is in the middle
of the supply rails. This change in the common-mode voltage
is compensated in the CMFB circuit by injecting a correcting
charge with the switched capacitor C3, equal in value to C1 and
C2, when switching to the amplifying phase. Since the CMFB
signal is applied to the gate of a pMOS transistor its nominal
value—the bias voltage —is close to and thus the switch
S1 can be implemented with an nMOS transistor. To speed
131
Fig. 5. Active input circuit used in [10].
Fig. 6. Half of the proposed differential input interface and part of the first
pipeline stage.
up the opamp recovery from the off-state, the output stage’s
common-mode slewing current is momentarily increased by
decreasing the bias voltage in the beginning of the amplifi-
cation phase. This is realized by injecting a current pulse into
the bias circuit with a switched capacitor.
V. INPUT STAGE
A major problem in SO circuits is getting the signal into the
technique is utilized in bandpass circuits (either filters or
modulators) the problem can be avoided by using dc decoupling.
One solution is to use a reduced signal swing as is done in [9].
It is, however, preferable to have a large signal swing and find a
substitute for the series switch.
Two solutions based on an active circuit are proposed in [13]
and [10]. The latter circuit is shown in Fig. 5. It is a feedback
amplifier whose gain is set by the ratio of resistors R1 and R2.
The resistor R3 and the constant voltage source, implemented
as an SC circuit, are used to bring the node where the switches
are attached close to ground, which is needed to guarantee a
sufficient overdrive for the switches. The problem in the active
solutions is the limited amplifier performance, which is seen as
decreased linearity and speed.
The proposed passive input interface and a part of the first
ADC stage are shown in Fig. 6. The circuit consists of the tran-
sistors M1, M2, and M3, the resistor R and the capacitor C,
while the capacitors Cs and Cfb, the opamp, and the transistor
M4 belong to the MDAC of the first pipeline stage. The circuit is
based on the idea that, since the input of the first pipeline stage
is purely capacitive during the sampling, using a decoupling ca-
pacitor causes only loss of the dc level. If the voltage on the
decoupling capacitor is reset every clock cycle, the dc level can
be restored. Next, the operation of the circuit is explained and
the aspects affecting on the component values are discussed.
132
During the sampling, the switch transistors M1, M2, and M3
are open while the right-hand terminal of the capacitor Cs is
shorted to with M4. The voltage at the node n2, which is
connected to the input of the first pipeline stage, follows
with an attenuation determined by the ratio of Cs and C. This
attenuation can be made small by selecting C large compared to
Cs, and furthermore, its effect to the overall ADC gain can be
compensated by properly adjusting the value of Cs in the first
pipeline stage. The sample phase lasts only one quarter of the
clock period, since the first quarter after the hold phase is re-
served for resetting the voltage on the capacitor C. This quarter
period tracking time does not limit the conversion rate, since the
maximum clock rate is dictated by the opamp settling time.
In the hold phase, the nodes n1 and n2 are shorted to
ground with the transistors M1 and M2. Consequently, to the
first pipeline stage, the circuit looks just like an output of an
other MDAC. Since there is no open series switch between
and the MDAC input, there is some signal feedthrough
from the ADC input during the hold phase. The input signal
is first attenuated by the resistive divider consisting of the
resistor R and the on-resistance of the switch transistor M1
and further reduced by the high-pass filter formed of C and
the on-resistance of the switch transistor M2. To adequately
suppress the feedthrough the value of the resistor R has to
be maximized and the transistor M1 and M2 must be made
wide to minimize their on-resistance. On the other hand, the
sizes of M1 and M2 cannot be made arbitrarily large, since
they add nonlinear parasitic capacitances to nodes n1 and n2,
which produces harmonic distortion during the sampling. The
sampling time constant is proportional to the value of R and
limiting the maximum value of it.
After the hold phase, the voltage on the capacitor C is reset
by shunting its terminals with the transistor M3. The node n1 is
kept connected to the ground, giving a proper voltage level for
the n-type reset switch. Since the node n2 follows the node n1
during the reset, an attenuated version of the input voltage will
be sampled in the node n2. If this is a problem, the first pipeline
stage can be modified by adding a series switch between Cs and
the opamp input to disconnect Cs during the reset phase.
The values used for C, Cs, and R are 5 pF, 0.44 pF, and 1.5 k ,
respectively. A total harmonic distortion of 70 dBc is predicted
by a simulation made using a 5-MHz clock rate and a 1.7-MHz
sinusoidal input signal with a 1.2-V differential amplitude.
VI. COMPARATOR
In the 1.5-bits-per-stage pipeline architecture, there is one
redundant quantization level in each sub-ADC which together
with the digital correction permits ( 150 mV in this
design) inaccuracy in the comparator decisions. Consequently,
the comparator can be a fairly simple dynamic circuit. Since the
analog signal path is fully differential, it is desirable that the
comparator has a fully differential input, which prevents the use
of conventional single-ended comparator topologies where the
signal is applied to one input pin and the reference voltage to the
other. One possibility to realize a fully differential comparator
is to employ a charge summation circuit. The implementation
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 1, JANUARY 2001
Fig. 7. Fully differential comparator.
used, e.g., in [5] consists of a latch stage preceded by coupling
capacitors that are precharged to the reference voltages during
the reset phase. In the acquisition phase, the latch input experi-
ences a voltage that is the sum of the input and the reference; as
a result, the comparator decision level is equal to the reference
voltage. The implementation used here, shown in Fig. 7, relies
on the same type of architecture.
Due to the switched-opamp implementation of the MDAC,
the input capacitors cannot be disconnected from the output
of the previous pipeline stage. Thus another pair of capacitors
is needed for adding the reference voltages. During the reset
phase, the previous converter stage pulls the input capacitors to
and the inputs of the latch are reset to . At the same
time, the reference capacitors are connected to . When the
driving pipeline stage starts its amplification phase, the reset
switches of the comparator are released and the resistor string
to which the reference capacitors are attached is connected be-
tween the global positive and negative reference voltages. The
resistor string, which is common for all the comparators in the
same pipeline stage, provides voltages and ,
setting the comparator decision level accordingly. There are two
reasons why the quarter reference is realized with a resistor
chain instead of simply scaling the reference capacitor values.
First, when using equal size input and reference capacitors the
common-mode voltage level in the latch input is automatically
set to . Otherwise, an extra pair of capacitors would have
been needed for correcting the voltage level. The second reason
is the desire to keep the capacitors as small as possible. The
capacitor value would have been too small to implement
without increasing the absolute value of the unit capacitor C.
The dynamic latch consists of an n-type input pair and a
cross-coupled pMOS load with reset switches in parallel. The
clock signal controls a switch between the common-source node
of the input pair and the ground. Although the ADC employs
the digital correction, careful balancing of the load capacitance
in the complementary outputs is needed to guarantee an offset
within the tolerable range.
The digital error correction makes it possible to latch the com-
parator before the output of the driving stage is fully settled. This
is utilized to make sure that the A/D conversion result is ready
at the time when the MDAC begins the amplification. The com-
parators are synchronized with the MDAC by adding a digital
latch stage after them.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 1, JANUARY 2001 133

Fig. 8. Photograph of the prototype chip.

Fig. 10. SNDR versus the signal amplitude. At the 1.0-V supply voltage, the
clock rate is 5 MHz and the signal frequency 200 kHz. The 1.5-V curve is
obtained with 14-MHz clock and 1.5-MHz signal.

Fig. 9. Measured DNL and INL.

VII. EXPERIMENTAL RESULTS

The prototype chip is implemented in a 0.5- m triple-metal
double-poly CMOS technology having 610 mV for both
nMOS and pMOS transistors. A photo of the die with an active
area of 1.3 mm is shown in Fig. 8. The prototype is packaged
in a 44-pin CLCC package and the measurements are performed
using a test board made of 2-layer PCB and having a socket for
the chip.
The operation of the circuit is verified with a supply voltage
range from 0.95 to 1.6 V. All the results given are obtained with
the 1.0-V supply unless otherwise specified. The reference volt- Fig. 11. Spectrum measured at 5-MHz clock rate using 1.0-V supply voltage.
The signal is a 1.5-MHz full-scale sine wave.
ages are set 600 mV apart and symmetrically between the supply
rails resulting a 600 mV differential input signal range.
The ADC performance is limited by the static nonlineari-
The measured differential nonlinearity (DNL) and integral
ties since the SNDR is virtually constant up to 6-MHz clock
nonlinearity (INL) curves, presented in Fig. 9, show maximum
frequency, after which there is a sudden collapse in the signal
DNL and INL of 0.6 and 0.9 LSB, respectively. The signal-to-
quality indicating timing problems in the digital circuitry. When
noise-plus-distortion ratio (SNDR) versus the input signal am-
the supply voltage is increased to 1.5 V, the same phenomenon
plitude measured at 1.0 and 1.5 V supply voltages and 5 and
is observed at 14.5-MHz clock frequency. The power consump-
14 MHz respective clock rates is shown in Fig. 10. In both cases,
tion from a 1.0-V supply at the 5.0-MS/s sampling rate is 1.6
the peak SNDR is obtained with the full-scale signal amplitude
mW. In addition to increasing the supply voltage to 1.5 V, the
and has a value of 50.0 dB which corresponds to 8.0 effective
bias current has to be tripled to achieve the 14-MS/s sampling
bits.
rate. This increases the power consumption to 8.2 mW which is
Fig. 11 shows a spectrum where a 1.5-MHz full-scale sine
still very low compared to the 36 mW achieved in [5] with the
wave is sampled at 5.0 MS/s, the supply voltage being 1.0 V. Re-
same supply voltage and sampling rate. The measured perfor-
spectively, a 14-MS/s spectrum obtained with the 1.5-V supply
mance is summarized in Table I.
is presented in Fig. 12. With the low supply voltage, the spu-
rious-free dynamic range (SFDR) is limited by the second har-
VIII. CONCLUSION
monic and it is 59.5 dB. The level of the harmonic is raised as
the bias current is increased along with the supply voltage, re- The switched-opamp technique has been utilized to realize a
ducing the SFDR to 55.3 dB at 1.5 V. 9-b 5-MS/s pipelined ADC that requires only a 1.0-V supply
134 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 1, JANUARY 2001

work features a number of new circuit structures. How to bring

the external signal into a switched-opamp circuit has been a
major problem lacking a good solution. In the designed proto-
type, this problem is solved using a novel passive circuit. The
measurements demonstrate that the SO technique previously
considered as an immature and performance-limited technique
can be used to realize low-voltage ADCs providing well-
matched performance with the other low-voltage realizations.

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