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• LC1:
Li is incremented before each event is issued at process pi:
Li = Li +1
• LC2:
a. Pi sends a message m, it piggybacks on m the value t = Li
b. On receiving (m,t), a process pj computes Lj=max(Lj,t)
and then applies LC1 before timestamping the event
receive(m).
Lamport timestamps for the events
1 2
p1
a b m1
3 4
Physical
p2
c d time
m2
1 5
p3
e f
a →1 b and c →2 d a →e and e → a
b → c and d → f concurrent a || e
combing them, a → f
Problem with logical clock ?
It can be easily shown that:
• If e->e’ then L(e) < L(e’).
• However, the converse is not true. If L(e) < L(e’), then we
cannot infer that e->e’. E.g b and e
• L(b)>L(e) but b||e
• How to solve this problem?
1 2
p1
a b m1
3 4
Physical
p2
time
c d m2
1 5
p3
e f
Vector Clocks
(1,0,0) (2,0,0)
p1 • Events a and
a b m1 f
V(a)<V(f)
(2,1,0) (2,2,0)
Physical implies a->f
p2
c d time
m2 •Events c and e
V(c) ≤ V(e)
(0,0,1) (2,2,2) V(e) ≤ V(c)
p3
implies c||e
e f
• Logical clocks
• Vector clocks
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