Section 8.

3 Sequential PLDs 581

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The D-flip-flop model can be augmented to include asynchronous inputs
and a complemented output as in the 74x74 discrete flip-flop, as shown in
Table 8-7. This more detailed functional model shows the non-complementary
behavior of the Q and QN outputs when preset and clear are asserted simul-
taneously. However, it does not include timing behavior such as propagation

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delay and setup and hold times, which are beyond the scope of the VHDL
coverage in this book.
Larger registers can of course be modeled by defining the data inputs and
outputs to be vectors, and additional functions can also be included. For
example, Table 8-8 models a 16-bit register with three-state outputs and clock-

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enable, output-enable, and clear inputs. An internal signal vector IQ is used to
hold the flip-flop outputs, and three-state outputs are defined and enabled as in
Section 5.6.4.

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SYNTHESIS
RESTRICTIONS
In Table 8-8, the first elsif statement theoretically could have included all of the
conditions needed to assign D to IQ. That is, it could have read “elsif (CLK'event)
and (CLK='1') and (CLKEN='1') then ...” instead of using a nested if statement
to check CLKEN. However, it was written as shown for a very pragmatic reason.

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Only a subset of the VHDL language can be synthesized by the VHDL
compiler that was used to prepare this chapter; this is true of any VHDL compiler
today. In particular, use of the “ event” attribute is limited to the form shown in the
example, and a few others, for detecting simple edge-triggered behavior. This gets
mapped into edge-triggered D flip-flops during synthesis. The nested IF statement

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that checks CLKEN in the example leads to the synthesis of multiplexer logic on the
D inputs of these flip-flops.

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8.3 Sequential PLDs
8.3.1 Bipolar Sequential PLDs
The PAL16R8, shown in Figure 8-17, is representative of the first generation of PAL16R8

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sequential PLDs, which used bipolar (TTL) technology. This device has eight
primary inputs, eight outputs, and common clock and output-enable inputs, and
fits in a 20-pin package.
The PAL16R8’s AND-OR array is exactly the same as the one found in the
PAL16L8 combinational PLD. However, the PAL16R8 has edge-triggered D

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flip-flops between the AND -OR array and its eight outputs, O1–O8. All of the
flip-flops are connected to a common clock input, CLK, and change state on the
rising edge of the clock. Each flip-flop drives an output pin through a 3-state
buffer; the buffers have a common output-enable signal, OE_L. Notice that, like

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582 Chapter 8 Sequential Logic Design Practices

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the combinational output pins of a PAL16L8, the registered output pins of the
PAL16R8 contain the complement of the signal produced by the AND-OR array.
The possible inputs to the PAL16R8’s AND-OR array are eight primary
inputs (I1–I8) and the eight D flip-flop outputs. The connection from the D flip-
flop outputs into the AND-OR array makes it easy to design shift registers,

DO NOT COPY counters, and general state machines. Unlike the PAL16L8’s combinational
outputs, the PAL16R8’s D-flip-flop outputs are available to the AND-OR array
whether or not the O1–O8 three-state drivers are enabled. Thus, the internal flip-
flops can go to a next state that is a function of the current state even when the
O1–O8 outputs are disabled.

DO NOT COPY Many applications require combinational as well as sequential PLD

outputs. The manufacturers of bipolar PLDs addressed this need by providing a
few variants of the PAL16R8 that omitted the D flip-flops on some output pins,
and instead provided input and output capability identical to that of the
PAL16L8’s bidirectional pins. For example, Figure 8-18 is the logic diagram of

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PAL16R6 the PAL16R6, which has only six registered outputs. Two pins, IO1 and IO8, are
bidirectional, serving both as inputs and as combinational outputs with separate
3-state enables, just like the PAL16L8’s bidirectional pins. Thus, the possible
inputs to the PAL16R6’s AND-OR array are the eight primary inputs (I1–I8), the

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six D-flip-flop outputs, and the two bidirectional pins (IO1, IO8).
PAL16L8
PAL16R4 Table 8-9 shows eight standard bipolar PLDs with differing numbers and
PAL16R8 types of inputs and outputs. All of the PAL16xx parts in the table use the same
PAL20L8 AND-OR array, where each output has eight AND gates, each with 16 variables
PAL20R4 and their complements as possible inputs. The PAL20xx parts use a similar

DO NOT COPY Ta b l e 8 - 9 Characteristics of standard bipolar PLDs.

Inputs to AND array

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Bidirectional
Part Package AND-gate Primary combinational Registered Combinational
number pins inputs inputs outputs outputs outputs

PAL16L8 20 16 10 6 0 2

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PAL16R4 20 16 8 4 4 0
PAL16R6 20 16 8 2 6 0
PAL16R8 20 16 8 0 8 0
PAL20L8 24 20 14 6 0 2

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PAL20R6
PAL20R8
24
24
24
20
20
20
12
12
12
4
2
0
4
6
8
0
0
0

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 Section 8.3 Sequential PLDs 583

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(1)
CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

0
1
2
3
(19)
4
D Q O1
5
6
Q

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7

(2)
I1
8
9
10
11
(18)
12
D Q O2
13
14

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15
Q
(3)
I2
16
17
18
19
(17)
20
D Q O3
21

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22
23
Q
(4)
I3
24
25
26
27
(16)
28
D Q O4
29

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30
31
Q
(5)
I4
32
33
34
35
(15)
36
D Q O5

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37
38
39
Q
(6)
I5
40
41
42
43
(14)
44
D Q O6

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45
46
47
Q
(7)
I6
48
49
50
51
(13)
52
D Q O7

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53
54
55
Q
(8)
I7
56
57
58
59
(13)
D Q O8

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60
61
62
63
Q
(9) (11)
I8 OE_L

Figure 8-17 PAL16R8 logic diagram.

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584 Chapter 8 Sequential Logic Design Practices

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(1)
CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

0
1
2
3 (19)
4 IO1
5
6

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7

(2)
I1
8
9
10
11
(18)
12
D Q O2
13
14

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15
Q
(3)
I2
16
17
18
19
(17)
20
D Q O3
21

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22
23
Q
(4)
I3
24
25
26
27
(16)
28
D Q O4
29

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30
31
Q
(5)
I4
32
33
34
35
(15)
36
D Q O5

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37
38
39
Q
(6)
I5
40
41
42
43
(14)
44
D Q O6

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45
46
47
Q
(7)
I6
48
49
50
51
(13)
52
D Q O7

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53
54
55
Q
(8)
I7
56
57
58
59 (12)

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60 IO8
61
62
63

(9) (11)
I8 OE_L

Figure 8-18 PAL16R6 logic diagram.

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 Section 8.3 Sequential PLDs 585

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PAL16L8 PAL16R4 PAL16R6 PAL16R8
1 1 1 1
I1 CLK CLK CLK
2 19 2 19 2 19 2 19
I2 O1 I1 IO1 I1 IO1 I1 O1
3 18 3 18 3 18 3 18
I3 IO2 I2 IO2 I2 O2 I2 O2
4 17 4 17 4 17 4 17
I4 IO3 I3 O3 I3 O3 I3 O3

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5 16 5 16 5 16 5 16
I5 IO4 I4 O4 I4 O4 I4 O4
6 15 6 15 6 15 6 15
I6 IO5 I5 O5 I5 O5 I5 O5
7 14 7 14 7 14 7 14
I7 IO6 I6 O6 I6 O6 I6 O6
8 13 8 13 8 13 8 13
I8 IO7 I7 IO7 I7 O7 I7 O7
9 12 9 12 9 12 9 12
I9 O8 I8 IO8 I8 IO8 I8 O8

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11 11 11 11
I10 OE OE OE

PAL20L8 PAL20R4 PAL20R6 PAL20R8

1 1 1 1
I1 CLK CLK CLK

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2 2 2 2
I2 I1 I1 I1
3 3 3 3
I3 I2 I2 I2
4 22 4 22 4 22 4 22
I4 O1 I3 IO1 I3 IO1 I3 O1
5 21 5 21 5 21 5 21
I5 IO2 I4 IO2 I4 O2 I4 O2
6 20 6 20 6 20 6 20
I6 IO3 I5 O3 I5 O3 I5 O3
7 19 7 19 7 19 7 19

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I7 IO4 I6 O4 I6 O4 I6 O4
8 18 8 18 8 18 8 18
I8 IO5 I7 O5 I7 O5 I7 O5
9 17 9 17 9 17 9 17
I9 IO6 I8 O6 I8 O6 I8 O6
10 16 10 16 10 16 10 16
I10 IO7 I9 IO7 I9 O7 I9 O7
11 15 11 15 11 15 11 15
I11 O8 I10 IO8 I10 IO8 I10 O8
13 14 14 14

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I12 I11 I11 I11
14 23 23 23
I13 I12 I12 I12
23 13 13 13
I14 OE OE OE

Figure 8-19 Logic symbols for bipolar combinational and sequential PLDs.

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AND-OR array with 20 variables and their complements as possible inputs.
Figure 8-19 shows logic symbols for all of the PLDs in the table.

8.3.2 Sequential GAL Devices

PAL20R6
PAL20R8

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The GAL16V8 electrically erasable PLD was introduced in Section 5.3.3. Two
“architecture-control” fuses are used to select among three basic configurations
of this device. Section 5.3.3 described the 16V8C (“complex”) configuration,
shown in Figure 5-27 on page 307, a structure similar to that of a bipolar
16V8C

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combinational PAL device, the PAL16L8. The 16V8S (“simple”) configuration 16V8S
provides a slightly different combinational logic capability (see box on
page 587).
The third configuration, called the 16V8R, allows a flip-flop to be provided 16V8R
on any or all of the outputs. Figure 8-20 shows the structure of the device when

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586 Chapter 8 Sequential Logic Design Practices

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(1)
CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

0
1
2
3 (19)
4 D Q O1
5
6
7 Q

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(2)
I1

8
9
10
11 (18)
12 D Q O2
13
14
Q

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15

I2 (3)

16
17
18
19 (17)
20 D Q O3
21
22

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23 Q
I3
(4)

24
25
26
27 (16)
28 D Q O4
29

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30
31 Q
(5)
I4

32
33
34
35 (15)
36 D Q O5
37

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38
39 Q
(6)
I5

40
41
42
43 (14)
44 D Q O6

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45
46
47 Q
(7)
I6

48
49
50
51 (13)
52 D Q O7

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53
54
55 Q
(8)
I7

56
57
58
59 (12)
D Q

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60
61
O8
62
63 Q
I8 (9)
(11)
OE_L

Figure 8-20 Logic diagram for the 16V8 in the “registered” configuration.

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 Section 8.3 Sequential PLDs 587

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OE CLK
Registered
output logic macrocell OE CLK
Combinational
output logic macrocell

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D Q

Q
(a) (b)

Figure 8-21 Output logic macrocells for the 16V8R: (a) registered; (b) combinational.

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flip-flops are provided on all outputs. Notice that all of the flip-flops are
controlled by a common clock signal on pin 1, as in the bipolar devices of the
preceding subsection. Likewise, all of the output buffers are controlled by a
common output-enable signal on pin 11.

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The circuitry inside each dotted box in Figure 8-20 is called an output logic output logic macrocell
macrocell. The 16V8R is much more flexible than a PAL16R8 because each
macrocell may be individually configured to bypass the flip-flop, that is, to
produce a combinational output. Figure 8-21 shows the two macrocell config-
urations that are possible in the 16V8R; (a) is registered and (b) is

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combinational. Thus, it is possible to program the device to have any set of
registered and combinational outputs, up to eight total.
The 20V8 is similar to the 16V8, but comes in a 24-pin package with four
extra input-only pins. Each AND gate in the 20V8 has 20 inputs, hence the “20”
in “20V8.”
20V8

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THE “SIMPLE”
16V8S
The “simple” 16V8S configuration of the GAL16V8 is not often used, because its
capabilities are mostly a subset of the 16V8C’s. Instead of an AND term, the 16V8S

DO NOT COPY uses one fuse per output to control whether the output buffers are enabled. That is,
each output pin may be programmed either to be always enabled or to be always dis-
abled (except pins 15 and 16, which are always enabled). All of the output pins
(except 15 and 16) are available as inputs to the AND array regardless of whether the
output buffer is enabled.

DO NOT COPY The only advantage of a 16V8S compared to a 16V8C is that it has eight, not
seven, AND terms as inputs to the OR gate on each output. The 16V8S architecture
was designed mainly for emulation of certain now-obsolete bipolar PAL devices,
some of which either had eight product terms per output or had inputs on pins 12 and
19, which are not inputs in the 16V8C configuration. With appropropriate program-

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ming, the 16V8S can be used as a pin-for-pin compatible replacement for these
devices, which included the PAL10H8, PAL12H6, PAL14H4, PAL16H2,
PAL10L8, PAL12L6, PAL14L4, and PAL16L2.

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588 Chapter 8 Sequential Logic Design Practices

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clock (to all macrocells)
(1)
I1/CLK asynchronous reset
(to all macrocells)

8 (23)
Output IO1
logic

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macrocell

10 (22)
Output IO2
logic
(2) macrocell
I2

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(3)
12
Output
logic
macrocell
(21)
IO3

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14 (20)
Output IO4
logic
(4) macrocell
I4

16 (19)
Output IO5

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logic
(5) macrocell
I5
Programmable
AND Array 16 (18)
Output IO6
(132 x 44) logic
(6) macrocell

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I6

14 (17)
Output IO7
logic
(7) macrocell
I7

DO NOT COPY I8
(8)
12

10
Output
logic
macrocell
(16)

(15)
IO8

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Output IO9
logic
(9) macrocell
I9

8 (14)
Output IO10
logic

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(10) macrocell
I10

Figure 8-22 synchronous preset

(to all macrocells)
(11) (13)
Logic diagram for I11 I12
the 22V10.

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 Section 8.3 Sequential PLDs 589

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The 22V10, whose basic structure is shown in Figure 8-22, also comes in a 22V10
24-pin package, but is somewhat more flexible than the 20V8. The 22V10 does
not have “architecture control” bits like the 16V8’s and 20V8’s, but it can realize
any function that is realizable with a 20V8, and more. It has more product terms,
two more general-purpose inputs, and better output-enable control than the

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20V8. Key differences are summarized below:
• Each output logic macrocell is configurable to have a register or not, as in
the 20V8R architecture. However, the macrocells are different from the
16V8’s and 20V8’s, as shown in Figure 8-23.

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• A single product term controls the output buffer, regardless of whether the
registered or the combinational configuration is selected for a macrocell.
• Every output has at least eight product terms available, regardless of
whether the registered or the combinational configuration is selected. Even
more product terms are available on the inner pins, with 16 available on

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each of the two innermost pins. (“Innermost” is with respect to the right-
hand side of the Figure 8-22, which also matches the arrangement of these
pins on a 24-pin dual-inline package.)
• The clock signal on pin 1 is also available as a combinational input to any

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product term.
• A single product term is available to generate a global, asynchronous reset
signal that resets all internal flip-flops to 0.
• A single product term is available to generate a global, synchronous preset

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signal that sets all internal flip-flops to 1 on the rising edge of the clock.
• Like the 16V8 and 20V8, the 22V10 has programmable output polarity.
However, in the registered configuration, the polarity change is made at the
output, rather than the input, of the D flip-flop. This affects the details of
programming when the polarity is changed but does not affect the overall

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capability of the 22V10 (i.e., whether a given function can be realized). In
fact, the difference in polarity-change location is transparent when you use
a PLD programming language such as ABEL.

Figure 8-23 Output logic macrocells for the 22V10: (a) registered; (b) combinational.
(a)

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SP
CLK
AR
Registered
output logic macrocell
(b)
SP
CLK
AR
Combinational
output logic macrocell

8–16

DO NOT COPY D Q

Q
8–16

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590 Chapter 8 Sequential Logic Design Practices

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GAL16V8C GAL16V8R GAL20V8C GAL20V8R GAL22V10
1 1 1 1 1
I1 CLK I1 CLK CLK/I1
2 19 2 19 2 2 2 23
I2 O1 I1 IO1 I2 I1 I2 IO1
3 18 3 18 3 3 3 22
I3 IO2 I2 IO2 I3 I2 I3 IO2
4 17 4 17 4 22 4 22 4 21
I4 IO3 I3 IO3 I4 O1 I3 IO1 I4 IO3

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5 16 5 16 5 21 5 21 5 20
I5 IO4 I4 IO4 I5 IO2 I4 IO2 I5 IO4
6 15 6 15 6 20 6 20 6 19
I6 IO5 I5 IO5 I6 IO3 I5 IO3 I6 IO5
7 14 7 14 7 19 7 19 7 18
I7 IO6 I6 IO6 I7 IO4 I6 IO4 I7 IO6
8 13 8 13 8 18 8 18 8 17
I8 IO7 I7 IO7 I8 IO5 I7 IO5 I8 IO7
9 12 9 12 9 17 9 17 9 16
I9 O8 I8 IO8 I9 IO6 I8 IO6 I9 IO8
11 11 10 16 10 16 10 15

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I10 OE I10 IO7 I9 IO7 I10 IO9
11 15 11 15 11 14
I11 O8 I10 IO8 I11 IO10
13 14 13
I12 I11 I12
14 23
I13 I12
23 13
I14 OE

DO NOT COPY Figure 8-24 Logic symbols for popular GAL devices.

For most of the 1990s, the 16V8, 20V8, and 22V10 were the most popular
and cost-effective PLDs (but see the box on page 593). Figure 8-24 shows

DO NOT COPY generic logic symbols for these three devices. Most of the examples in the rest of
this chapter can fit into the smallest of the three devices, the 16V8.

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PALS? GALS? Lattice Semiconductor introduced GAL devices including the GAL16V8 and
GAL20V8 in the mid-1980s. Advanced Micro Devices later followed up with a pin-
compatible device which they call the PALCE16V8 (“C” is for CMOS, “E” is for
erasable). Several other manufacturers make differently numbered but compatible
devices as well. Rather than get caught up in the details of different manufacturers’
names, in this chapter we usually refer to commonly used GAL devices with their

DO NOT COPY generic names, 16V8, 20V8, and 22V10.

8.3.3 PLD Timing Specifications

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tPD
Several timing parameters are specified for combinational and sequential PLDs.
The most important ones are illustrated in Figure 8-25 and are explained below:
tPD This parameter applies to combinational outputs. It is the propagation
delay from a primary input pin, bidirectional pin, or “feedback” input to

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feedback input the combinational output. A feedback input is an internal input of the
AND-OR array that is driven by the registered output of an internal
macrocell.

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 Section 8.3 Sequential PLDs 591

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tCO This parameter applies to registered outputs. It is the propagation delay tCO
from the rising edge of CLK to a primary output.
tCF This parameter also applies to registered outputs. It is the propagation tCF
delay from the rising edge of CLK to a macrocell’s registered output that
conects back to a feedback input. If specified, tCF is normally less than

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tCO . However, some manufacturers do not specify tCF, in which case you
must assume that tCF = tCO .
tSU This parameter applies to primary, bidirectional, and feedback inputs
that proprogate to the D inputs of flip-flops. It is the setup time that the
tSU

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input signal must be stable before the rising edge of CLK.
tH This parameter also applies to signals that proprogate to the D inputs of tH
flip-flops. It is the hold time that the input signal must be stable after the
rising edge of CLK.
fmax This parameter applies to clocked operation. It is the highest frequency fmax

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at which the PLD can operate reliably, and is the reciprocal of the
minimum clock period. Two versions of this parameter can be derived
from the previous specifications, depending on whether the device is
operating with external feedback or internal feedback.

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External feedback refers to a circuit in which a registered PLD output is external feedback
connected to the input of another registered PLD with similar timing; for
proper operation, the sum of tCO for the first PLD and tSU for the second
must not exceed the clock period.
Internal feedback refers to a circuit in which a registered PLD output is fed internal feedback

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back to a register in the same PLD; in this case, the sum of tCF and tSU must
not exceed the clock period.
Each of the PLDs that we described in previous sections is available in
several different speed grades. The speed grade is usually indicated by a suffix

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on the part number, such as “16V8-10”; the suffix usually refers to the tPD

input or
feedback
tSU tH

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input or CLK CLK
feedback
tPD tCO tCF tSU
combinational registered registered
output output feedback

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1/ f max 1/fmax
(a) (b) (c)
(external feedback) (internal feedback)

Figure 8-25 PLD timing parameters.

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592 Chapter 8 Sequential Logic Design Practices

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Ta b l e 8 - 1 0 Timing specifications, in nanoseconds, of popular bipolar and CMOS PLDs.

Part numbers

PAL16L8, PAL16Rx, PAL20L8, PAL20Rx

Suffix

-5
tPD

5
tCO

4
tCF

–
tSU

4.5
tH

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PAL16L8, PAL16Rx, PAL20L8, PAL20Rx

PAL16L8, PAL16Rx, PAL20L8, PAL20Rx

PAL16L8, PAL16Rx, PAL20L8, PAL20Rx

-7

-10

B
7.5

10

15
6.5

12
–

–
7

10

15
0

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PAL16L8, PAL16Rx, PAL20L8, PAL20Rx

PAL16L8, PAL16Rx, PAL20L8, PAL20Rx

PALCE16V8, PALCE20V8
B-2

-5
25

25

5
15

15

4
–

–
25

25

3
0

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GAL16V8, GAL20V8

GAL16V8, GAL20V8

GAL16V8, GAL20V8
-7

-10

-15
7.5

10

15
5

7.5

10
3

8
5

7.5

12
0

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GAL16V8, GAL20V8

PALCE22V10

PALCE22V10
-25

-5

-7
25

7.5
12

4.5
10

–
15

4.5
0

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GAL22V10 -10 10 7 2.5 7 0

GAL22V10 -15 15 8 2.5 10 0

GAL22V10 -25 25 15 13 15 0

DO NOT COPY specification, in nanoseconds. Table 8-10 shows the timing of several popular
bipolar and CMOS PLDs. Note that only the tPD column applies to the combina-
tional outputs of a device, while the last four columns apply to registered
outputs. All of the timing specifications are worst-case numbers over the

DO NOT COPY commercial operating range.

When sequential PLDs are used in applications with critical timing, it’s
important to remember that they normally have longer setup times than discrete
edge-triggered registers in the same technology, owing to the delay of the AND-

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OR array on each D input. Conversely, under typical conditions, a PLD actually
has a negative hold-time requirement because of the delay through AND-OR
array. However, you can’t count on it having a negative hold time—the worst-
case specification is normally zero.

Copyright © 1999 by John F. Wakerly Copying Prohibited

 Section 8.4 Counters 593

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HOW MUCH
DOES IT COST?
Once you understand the capabilities of different PLDs, you might ask, “Why not
just always use the most capable PLD available?” For example, even if a circuit fits
in a 20-pin 16V8, why not specify the slightly larger, 24-pin 20V8 so that spare
inputs are available in case of trouble? And, once you’ve specified a 20V8, why not

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In the real world of product design and engineering, the constraint is cost.
Otherwise, the argument of the previous paragraph could be extended ad nauseum,
using CPLDs and FPGAs with even more capability (see \chapref{CPLDsFPGAs).
Like automobiles and fine wines, digital devices such as PLDs, CPLDs, and

DO NOT COPY FPGAs are not always priced proportionally to their capabilities and benefits. In
particular, the closer a device’s capability is to the “bleeding edge,” the higher the
premium you can expect to pay. Thus, when selecting a devices to realize a design,
you must evaluate many trade-offs. For example, a high-density, high-cost CPLD or
FPGA may allow a design to be realized in a single device whose internal functions

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are easily changed if need be. On the other hand, using two or more lower density
PLDs, CPLDs, or FPGAs may save component cost but increase board area and
power consumption, while making it harder to change the design later (since the
device interconnections must be fixed when the board is fabricated).
What this goes to show is that overall cost must always be considered along

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with design elegance and convenience to create a successful (i.e., profitable)
product. And minimizing the cost of a product usually involves a plethora of com-
mon-sense economic and engineering considerations that are far removed from the
turn-the-crank, algorithmic gate minimization methods of Chapter 4.

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8.4 Counters
The name counter is generally used for any clocked sequential circuit whose
state diagram contains a single cycle, as in Figure 8-26. The modulus of a
counter
modulus

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counter is the number of states in the cycle. A counter with m states is called a
modulo-m counter or, sometimes, a divide-by-m counter. A counter with a non-
power-of-2 modulus has extra states that are not used in normal operation.
modulo-m counter
divide-by-m counter

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Figure 8-26
S1 General structure
S3 of a counter’s state
diagram—a single
cycle.

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Sm

S4
S5

Copyright © 1999 by John F. Wakerly Copying Prohibited