S88 : ee a \ “TTL Logic Diagrams (Vec= +5 V Nom) 2 TTL Eca7aHitoo, ECGNCToO, ECG7aLSoo, | ECG74G1, ECG7ALS01 ECG74HO1 ECG? ican x | Ecarssot \ x bh 2a a Un i ecient wt Vo 50 Open | Hee Bute wir Heva 20 pen He rachgs Onn SonPogeia_| FH 1-314| TTL Logic Diagrams {cont’d) Diag. 13 Tin DIP See Fig. OS | lag. ECG7411, ECGTMHTI, ECGTAHCTH, Eca7#12, EcG74L312 EcG7Lst1, eco74si1 Te-Pin OP See Fig. 08 | Diag. 15 16-Fin O1P See Pg, 06 Eca7a13, Eco7aLst3 nye ‘tile input NANO Gate with Open Collect Output Triple input AND Gate ual d-input NANO Schmit Tagger! log. 18 16-Pin DIP See Fig. 08 | Diag. 17 ECG7414, ECG7ECTS, ECGTANCTE, ECG7#HCTI4, ECGTALS14 14-Pin DIP See Fig. 06 | Diag. 18 16-Pin DIP See Fig, O8 ECG7ALSIS, ECG7ES15 ecG7a16 PUTT Tepla 2-Ingut AND Gate with Open Collector Hox Schmitt Tagger Inverter Output Hex Inverter/ Buffer with HiVolt (18 V} Open Collector Output * Diag. 18 TW Pin DIP See Fig. 06 | Oing.20 = Vé-Pin DIP See Fig, 06 | Oleg. 21 T#Pin DIP S Eca717 EcG7420, ECG74C20, ECG74H20, ECG7A21, ECGTAH2, ECG7ALSZI 1 ECG7ALS20, ECG74S20, Fig. 08 Hex Buffer with Hivot 15 VI Open Cllactor Gutput al input AN Gate ual nau AND Gate E Ding. Tein di See a. 08 | Ong TePin OW Seep. 08 | Og. 26 "Pin DIP Sea Fi, 08 EcG7422, eca7sH22, ECGTLSZ2, econ ece7as " concn (val 4tnput MAND Gute with Open Cote | Expandate Dual Simaut NOR Gatewin | Output Ste Dus! s-nput NOR Gate with Sticde Package Outines See Page 1347 4315 -,~TTL Logic Diagrams (cont'd) Diag: 25 14-in DIP See Fig, 08 ECG7428, ECGTALS26 a (Quad 2input HV intertace NANO Gate with Open Colectar Qutput Diag, 26 16-Pin DIP See Fig, 08 ecG7427, eca7ats27 Tile nut NOR Gate iag.27 Eca7i2s, ecomisza 4-Pin DIP See Fig, OB ‘Quae 2nput NOR autter Diag. 28 ‘Pi DIP See Fig. 06 Eca7#20, ecaracan, ecc7sH30, EcG7a1 530, EcG74S30 Biinput NANO Gate Diag. 29 = 14-Pin OP Si Eca7sa2, eca7scx2, EOGTIHC," EcG7acrs2, eccia.s12 usd 2Input OR Gate brag, 30 1-Pin DIP See Fig, 08 Eca7433, eca7iism - ‘Qued 2nput NOR Butfer with Open Collector Output Diag. 31 EcG707, ecG7sLs7 T4Pin OP Sea Fg. 06 Quad 2nput NANO Buter Diag. 32. 14-Pin DIP See Fig, OF Eca7409, ECa7sLs38 if (Quad 24nput NANO Buffer with Open Caliectar Qutaut Diag. 33 ECG7439 14-Pin OP Sea Fig, 8 ‘Quad 2input NANO duitfer with Open Callector Output lag. 34 14-Fin O1P See Fig. 08 EcG7éao, EcG7aHs0, ECGTALSA, Eca7isa {Oval s:nput NAND Buiter Diag. 35 16-in DIP See Fig, 08 ecaraat wre ‘8CD-to-Dacimal ecoder/Orver for Gas Filed Tuboe Diag, 36 16-in OIF See Fig. Ecava2, ecantcaz, ECGTLSA? Uy eee 8C0-to-Oecimal Decoder 1-316 ee ile© TTL Logic Diagrams (cont'd) foes tog. 37 16-in OIF Sea Fig. 08 Ecarasa | Oiag. 38 eca7ss 16PinDiP Se Fig. 08 Diag. ecarais Excose-310-Decimal Decoder Excess.Gray-to-.Oecimal Decoder {8CD-10-Decimal Oscade Driver with’ Open Collector Output Diag. 40 eca7s46 16-Pin OP See Fig, 0B {8C0-t07-Segment Decoder/ Driver with Ht Yok (20 VI Open Callactor Guiput Diag. 1 16-Pin DIP See Fig. 08 Eco7ur, ecc7aisa7 Pexapreepcras orcad LL PLSLSLL aL BCD-to-7-Segrant Decade/Oriver with Hi Volt (15 Vi Open Collector Output Diag. 2 16-Pin O1P See Fig. 0 ECGT#A8, ECG7ACAH, ECGTALSHB 8C-to-7-Segmant Oacader/ Driver ‘Diog. «3 ECGTALSi9 Ta-Pin OP See Fig. OS BCD-t0-7-Segmant Decoder Driv with ‘Open Collector Output Diag. 4 JP DIP See Fig. 08 ECG7s80, ECG7¢HS0 ae Dual 2-Wide 2Input ANO/OR/Inver Gate (One Gate Expandable) Diag. 45 {See a0 Diog. 46) ECG7s51, ECG7AHSi, ECG74S51 14-Pia IP See Fig. 06 vel 2.-Wida 2-Input ANO/OR/Invert Gate Diag. 6 [See also Diag. 45), ECG7sLS51 Fin OP See Fig. DB Diag. 47 Win DIP Sea Fig. 06 Eca7aHs2 Dual 2-Wkle slqput, 2. Wide eput ANO/ OA/Invert Gate Diag. 48 14-Pin DIP Sea Fig, 08 {See ais Diag. «9) eca7asa Expandable wide opt 2 ‘ANO/OR Gate Eapondable 4.Wide 2-Input AND/OA,awert [ee Package Outlines See Page 147 1aTTk Logic Diagrams (cont'd) y a Expandable &Wide 2-2-2 Input AND/OR/ Inver Gate Diag. «8 1#-Pin DIP See Fig. 08 | ing. 60 1M-Fin DIP See Fig. 08 | Diag. St 1-Pin DIP See Fig, 08 {Sa also Diag. 48), {See also Diag. 51 and 521 s | AS also Diag! 0 and 52) ecorehsa caress ECGTHst 4:Wide 2nput ANO/OR/invert Gate 4-Wide 22-23 Input AND/OR/lavert Gate 4-Wide 32-23 input ANO/OR/Inert Gate Diag. 52 14 indIP See Fig, 08 | Ding. 52 Té-in DIP See Fig. 05 | lag. St Pia IP See Fig, 8 | (See also Diag. $0 and 511 [See also Diag. Sa) [See aso Diag, 5a) Eca7atss4 ECa7sHss ECGTALSSS Expandable 2Wie ¢-Input AND/OA Iver Cate 2.Wide 4:input ANO/OR/Invart Gate Diag, 55 EcG7ato, Eca7sH80 14in DIP See Fig, OF Dual input Expander Triple B.ingut Expander Diag. 5 | MP DIP See Fig. 06 | leg. 57 e-in OIF See Fig, D8 Ecavanay Ecavansz Wide 22:29 Input ANO/ON Expandec Diag. 58 | WSPinDIP See Fig, DB | Oiag. 58 14Fin DIP See Fig, 08 | Olan. 6 1HPin DIP See Fig, OB Ecarasss ECG7«S65 eca7a70 4+Wide 42-32 Input AND/OR/invert Gate 4.Wide 4.2:-2 inaut ANO/OR/Invert Gate ‘with Open Cofleetor Output Gated J-K Positive Edge Triggered Flip-Flop with Preset and Clase Package Outines See Page 347F TTL Logic Diagrams (cont'd) a Diag. 6 ecaraur H-Pin DIP Sea Fig, OF Gated JK M/S Flip-Flop with Peesat Dig, 62 eca7472, eca7su72 ‘VsPin DIP Sea Fig. OF Diag. 62 [ee aso Oiog, 64) EcG7473, ECG7aHTS 14Fin OI Fig, 08 Gated J-K M/S Flip-Flop with Preset and ‘lear ual JK M/S Flip-Flop with Clear Diag. 6 [See also Diag. 63) ECG7C73, ECGTALS73 . 16-Pin DIP Soe Fig. 5 Dual J-K Negative Edge Triggered Flip-Flop ‘ith Clase Diag. 65 14-Pia OP See Fig, 08 ECG7474, ECGTSCTS, ECGTAHTS, Eca7aLs7aa, Ecai4s74 ual “0” Flip-Flop with Pieset and Cleer ig. 8 ECG7A75, EcaTaLS7S 16-Pin OP Seu Fig. 08 ‘Bit Bistable Latch with Complomentary Outputs Diag. 67 (See also diag. 68) ECGI76, ECGTAHTS 16-Pin OP See Fig. OB Diag. 68 (See also Diag. 67) ECG/4C75, ECGTALS7EA 16-Fin OP Sea ig. 08 Dual JK M/S Fip-Fop with Preset and Clear Dual J-K Negative Edge Tiggered Flip-Flop with Prosetend Clear ~ Diag. 68 ECG?LST7 14-Pin OP Sea Fig. 06 Bit Bistoble Latch Ding. 70 (See atso Oiag. 70) ECG7aHTs Pin DIP See Fig, O8| Diag.71 {See also Diag. 70) Ecorais7a T4PinOIP See Fig, 08 Dot J. MAS Flip-Fos ith Prasets and 3 ‘Convnan Clack and Clear Dual J-K flogatis dos Teggetad Flip-Flop with Prasuts and a Corsenon Clock 8nd Clea Ae ALLL ital i et Gated Full Addor with Compomentary Sum ‘Outputs ij Peckage Outines See Paye 1-247 aaa§ NFTL‘Logic Diagrams (cont'd): Te F Diag. 73 T4Pin DIP Sea Fig. 06 | Diag. 74 T4-Pin DIP See Fig. 8 | ing. 75 16-Pin OIF See Fig. 08 ECG7461 eca7sea cG74sa, ECG7as87A 16-88 RAM (1641) 2-8 Binary Full Adder +t Fu Adder Diag. 78 16Fin giP See Fig. 08 | Diag. 77, 16-Pin DIP Sea Fig. 08 | Ding, 78 1-Pin DIP See Fig, OF ca7ass, eca7aLses ecaraces fai Eca7a85, ecGTanas, ECG7AHCar ECGTALSS6, ECGTSIB Bit Maghitude Comparator 3 4-Bit Magnitude Comparatoe ‘uad Exclusive OF Gat iag. 73 1&Pin OP See Fig. 06 | Diag. a0 16-Pin DIP Seaig. 08 | lag. 14-Pin OF Sea Fig. 08 Ecoranar «| scar : na | EcG7s90, EcaTiCe9, EcGTALSE0 FI whorl [nL faLfsL fe a ati 4-8ic Tee/Complement ZaroiOna Element | 64-8it RAM (16 x 4) " Decade Counter ' Diag. 2 14Pin DIP See Fig. 05 | Ding, 8 T4PinOIP See Fig. 06 | Diag. B& H-Pin DIP See Fig. 8 Ecavaat, ECG7aLSa1 wv | carga, ecoratsaa ECGTW3A, ECGTASM 1 Bit Serial Shit Register Divde-by: 12 Counter: 4-31 Binary Counter ee Package Outlines - See Page 1247 1-320481 Binary Counter 4-Bit Serial or orale! Shitt Register Diag. 85 14-Pin DIP See Fig, 08 | Diag. 16-Pin DIP Sea Fig. 08 | Oiag. 87 Fin DIP See Fig. OF eca7acs3, eca7aLs3 EcGr4s4, (See oso Diag. 88) 5 ECG7495, ECG74LS958 Bit Bicrectiona Parallel Shift Ragistar an a 4-BitBiivectional Paral Shift Register 5-Bit Sevia-n/Patalle-Out or Paraliatny ‘SevialOut Shift Register Diag. 09 14-Pin DIP See Fig. 08,| Ong. 69 1G-Fin DIP See Fig. 08 | Diag. 80 T6-Pin DIP See Fig. 08 | (Gee also Diag. 7) EcG7A96 f - ecorss7 > EcG7ices ‘Synchronous 6-Bit Binary Rate Muliplior Gated J-K Negative Ege Triggered Flp- Flop with Prasat Bie. 81 7 Pin Soe Fa D8 | lo. fe TePmOPSeaFe 08 | Omn.09 4 WP Di Se Fa OB Ecovanien aoe. | gearanoe ecavaes a . afl Gated JK Nogative Edge Triggered Fir Flop with Preset and Clear Duel JK Negative Ege Triggered FlipFlop with Clear 7 Diag. 94 16-Pin DIP See Fig. 08 EcG7sH08 . Dua! J-k Wagative Euge Trigganid Flip-Flop [Loe oer Package Quiles See Page 1047 Diag. 95 {See also Qiag. 96) ecaraio7 1éPin DIP See Fig, 05 Diag. 98 (See also Diag. 35)". EcG74ct07, ECG7sLS107 Té-Pin OP See Fig. OS Dus! J:K Neyetive Euge Trgured Fp Flap wth Clear | dual J-K M/S Fip-Fop with Clear 12215. TTL Logic Diagrams (cont'd) Diag. 97 coven TH-PinOIP Soe Fig. 08 Diag. 88 16-Pin DIP See Fig, OF ECG7A108, EcG7aNCI0s, ECGTALSTOOA unl J-K Negative Edge Triggered Flip-Flop with Clear el J-% Positive Edge Triggered, Flip-Flop with Praset and Clear Diag. 89 ecars7a H-Fin DIP See Fig, Os Gated J-K M/S Flip-Flop with Preset and lear Diag. 100 cava 18-Pin DIP See Fig. 08 DuslJ-K M/S Fip-Fiop with Preset and Cina , Diag. 101 T6-in OIF See Fig. 08 ECG7aLst12A, ECGrASHI2 isl J-K Negative Edge Triggered Fip-Fop with Preset end Clear : Diag. 102 14-Pin OIF Se Fig. 08 Ecartst, ecomst1a Dual J-K Negative Edge Triggered Fip-Flon with Preset Diag. 103 16-Pin DIP See Fig, 08 Ecovaisit, Ecorsit4 Dual J-K Negative Edge Triggered Flip-Flop ‘vith Presets and 2 Common Clack and Clear Diag, 104 Ecarsi21 14-Fin DIP See Fig, 08 Diag. 105 14-Pin DIP Sea Fig. 06 EcG74122, eccratsi22 Manestable Moltvirator LG etrggerable Moncstabe Moltviratar with Clear Disa, 108 16-Pin DIP See Fig, 08 ECG7H23, ECGrAHCI23, ECGTALST2I Dust Reulggersble Menostable Multvbrator with Clear Dieg. 107 eca7asi2g T6-Pin OIP Sex Fig. 08 Dual Voltage Controted Osciotor Diag. 108 16-Pin OP See Fig, 08 ECa7A125, ECG7aHCI25, ECaMLSTSA ‘Qued Bus Buer with 3-State Output (Active. Low 1.32 Peckage Outlines - See Page 127LTTL Logic Diagrams (cont'd) ag. 108 Ta Pin DIP Sea Fig. 08 ECG7H126, ECGTAHC26, ECGTALSTIE Quad Gus Bulfer with 3-State Output (Active High) Diag. 110 Eca7si28 1#Pin DIP See Fig. 06 ‘Quad 2tngit NOR 0 Ohm Line Orver (Quad 2-nput NANO Schmitt Trigger Diag. 111 Pin DIP See Fig. 08 ECG7HI, ECGIHCHHZ, ECGTLSIZ2 lag. 112 16 Pin OP See Fig. O8 EcGriists3, ecoasisa 13oput NAND Gate Oiag. 113 Eca7as134 T6Pin DIP See Fig. 08 2laput NANO Gate with 3-State Outpt Diag. 114 14-Pin DIP See Fig. 08 ECG74138, ECG7ALS TAS FOIE ‘Quad Exelysive OR Gate with Open Collector Output" Oiag. 115 16-Pin DIP See Fig. D8 EcoT#Ncr3a) ECG7ANCTI38, ECGTALST3E, ECG7ASII Se 2-Line-fo-8-Line Decoder/Damuiploxer Diag. 118 16-Pin OP See Fig. D8 ECG74HCI38, ECGPALST29 ual 2-Line-io-4-Line Decoder! Oemuliplexes Diag. 117 T4Pin DIP See Fig. OS Eca7ssio " Dual 4-Input NANO 50 Ohm Line Orver Diag. 18 eco7aiat Pockoge Outlines Swe Page 1237 T6-Piq DIP See Fig. DB | Diag. 119 eca7su2 TE-Pin DIP See Fig. OB ainicicnen BCD-tn-Dacinal Ducoule/ Oriver lor Cold Cathous Tubes CD Counter 4-Bit Late doe Jy/QC-to-7-Seyment Decoder! Oviver 1-323.-\ PTL Logie Diagrams (cont'd). : iag, 120 24-Pin DIP SeeFig, O16 | Olng. 72) 24-Pin OP See Fig. O15 ecarsisa cars sl Pan guntar!s-Blt Latch/BC0to7-Segment Decoder/Orivar win | CO Counter/4-Bt Latch/BCO-to7-Segmant Oecoder/Oriver with | Constant Curent Output ‘Open Calector Output a «| bing. 122 16 OP Seetig. OF | Dig. 12a “6-Fin IP See Fig 8 | Diag. 128 16-Fin OIF See i, 08 Eca7ss, ecanisus EcG7st7, consis? || ecortsua , ne OM me vag a Ls Lief fel fn] fel f+ ECGTALS151, ECGTASIST | S-Line-o-I-Line Oata Selector/Nutiplener G-Line-to--Line Data Selector/Muliplexer | “with Stebe Line-to-t-Line Oats Selector/ Multiplexer * VOing. 128 16Fin DIP Seo Fig. 08 | Diag. 129, 24-Pin DIP See Fig.015 | ing, 190 T6-Pin DIP See Fig. 08 ecorsiss, eccraners3, ecoraigisa, | Ecavaiss, ecd7scrs4, ECaTeHCISt ecG7nis5, eca7asiss ECG7aSis3 elspa Oval é:Line-o-1-Line Data Selector? Multiplexes ‘Unéto-8-Une Decader/Oemuliplexer | ual I-Lineto-tLine Decoder/Demuitipleser 5 Package Quitings - See Paga 1347 1-324TTL Logic Diagrams {cont'd} pene Diag. 131 ECG74356, ECG7ALSISS nfl STs TTC with Open Collector Output 16-PiaDiP See Fig. 08 Dus! I-Line-to-t-Line Deoder/ Demultiplexer Diag. 132 16-Fin DIP See Fig. 08 ECG7A57, ECGMCIS?, ECGTALSI57, ECG?4S1S7 gts ovine _enyis curt ee srnne ae av Hw Diag. 139 TE-Pin DIP See Fig. 08 ECG7A88, ECG7ALSISR, ECGTASTSS (Quad 2-Line-to--Line Deta Selector Mult ploxer with Non-lnvering Output to-i-Line Oata Seluctor! Mult loxer with Inverting Output Oiag. 134 ECG7A162, ECG7ALSIEVA ms fo with Qiwet Clear 16-Pin DIP See Fig, 08 at, son0 Presettable Synchronous Oueade Counter Diag. 135 16 Pin DIP See Fig, DB ECG74161, ECGTACI61, ECGTSHCTSI, ECGTANCTIGI, ECGTLSISIA Diag. 136, 16-Pin DIP See Fig. OB ECG74182, ECG7ALSI528 ron Preséttable Synchronous 48it Binary Counter with Direct Clear Presettable Synetranous Decade Counter with Syrehrenous Clear Oiag. 137 ECGHALSIBIA \ m TE-in DIP See Fig, 0B ECGTAIN, ECG7AHCTES, ECGTAHCTIER, Diag, 158 TéPin DIP See Fig. 08 ECG74164, ECG74C164, ECGTSHCISA, ECG7ALSI64 Diag. 129 16-Pin IP See Fig, 8 ECG7#165, ECGTAHCISS, ECGTALSTES ~ = Pradettable Synchronaus 4Bit Binary ae ‘Coonerwih Synchronous Chor an Saran Ponte Out Shite Rogier | &-8t Para n/ Serr Out Sie Reger Diag. 140, 16-Pin OP See Fig, 08 | Diag. 187 16Pin DIP See Fig. 08 | Diag. 142 16-Pin DIP See Fig. D8 ECG7«165, ECGTALSIE6 ECG7ALS1604, ECGTALSTEBA 8-8 Sesial or Parstub ln Revister | Presutable Syectuonows Decade Up! Down Counter Prasettable Synelwonous 4Bit Binary Upi Down Counter i ce Package Outlines - See Page 1-347 1325