Digital Logic Basics B

Digital Logic Basics
Rapid Reference and Refresher

With Examples
by Robert E Bridgewater
Digital Logic Basics
Rapid Reference and Refresher

With Examples
by Robert E Bridgewater
MoonDocs LLC
Anderson, Indiana USA
www.moondocs.com
Digital Logic Basics: Rapid Reference and Refresher
Copyright © 2005 R E Bridgewater
Published by MoonDocs LLC
www.moondocs.com
Anderson, Indiana USA

Contents
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Introduction and Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
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Number Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
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Ways to Represent Positive Numbers . . . . . . . . . . . . . . . . . . . 5
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Convert Base-10 Integer to Base-R Integer . . . . . . . . . . . . . . . . . 6
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Convert k-digit Base-R Integer to Base-10 Integer METHOD #1 . . . . . . . . . 7
Convert k-digit Base-R Integer to Base-10 Integer METHOD #2 . . . . . . . . . 7
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Binary Coded Decimal Number Representation . . . . . . . . . . . . . . 12
Arithmetic and Negative Numbers . . . . . . . . . . . . . . . . . . . . . . . . 15
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Adding Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Positive and Negative Numbers in Binary: Twoʼs-Complement Form . . . . . . 20
Procedure to Convert Signed Decimal Number to Twoʼs-Complement Binary . . . 22
Procedure to Convert Twoʼs-Complement Binary to Signed Decimal Number . . . 24
Addition Using Twoʼs-Complement Binary Numbers. . . . . . . . . . . . . 26
Subtraction Using Twoʼs Complement Binary Numbers . . . . . . . . . . . 28
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Binary Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . 31
Binary Division . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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Hexadecimal Addition . . . . . . . . . . . . . . . . . . . . . . . . 34
Hexadecimal Subtraction . . . . . . . . . . . . . . . . . . . . . . . 36
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Hexadecimal Multiplication . . . . . . . . . . . . . . . . . . . . . . 38
Addition of Binary-Coded Decimal Numbers. . . . . . . . . . . . . . . . 40
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The ASCII Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Boolean Algebra, Operations, and Logic Gates . . . . . . . . . . . . . 49
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Boolean Algebra Definitions . . . . . . . . . . . . . . . . . . . . . . 50
Boolean Algebra Laws, Rules, Properties. . . . . . . . . . . . . . . . . 51
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Basic Logic Gates and Operations . . . . . . . . . . . . . . . . . . . 52
Other Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Sum-of-Products (SOP) Form . . . . . . . . . . . . . . . . . . . . . 54
Product-of-Sums (POS) Form . . . . . . . . . . . . . . . . . . . . . 55
Switch Circuit Equivalent of AND Gate and OR Gate . . . . . . . . . . . . 56
A Look at DeMorganʼs Law . . . . . . . . . . . . . . . . . . . . . . 57
A Look at the Principle of Duality . . . . . . . . . . . . . . . . . . . . 58
Simplifying Expressions Using Boolean Algebra . . . . . . . . . . . . . . 59
ii Digital Logic Basics: Rapid Reference and Refresher

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Schematics To/From Logic Equations . . . . . . . . . . . . . . . . . . . . . 63
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The Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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Truth Table Structure. . . . . . . . . . . . . . . . . . . . . . . . . 68
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Forming SOP and POS Terms From Truth Table . . . . . . . . . . . . . . 69
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Making a Truth Table From a Function Written in Sum-of-Products (SOP) Form . . 70
Making a Truth Table From a Function Written in Product-of-Sums (POS) Form . . 72
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Making a Sum-of-Products (SOP) Form Expression From a Truth Table . . . . . 74
Making a Product-ofSums (POS) Form Expression From a Truth Table . . . . . 76
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The Karnaugh Map or K-Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
K-Map Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Making a Sum-of-Products (SOP) Form Expression from a K-Map . . . . . . . 82
Making a Product-of-Sums (POS) Form Expression from a K-Map . . . . . . . 83
K-Map Cell Grouping Methods for Sum-Of-Product (SOP) Terms . . . . . . . 84
K-Map Cell Grouping Patterns . . . . . . . . . . . . . . . . . . . . . 85
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Digital Logic Design Applications . . . . . . . . . . . . . . . . . . . . . . . . 89
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Design Example - Enable Circuits. . . . . . . . . . . . . . . . . . . . 90
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Design Example - Bank Alarm Application of AND Gate Enable . . . . . . . . 91
Design Example - XOR as Controlled Inverter / Complement Circuit . . . . . . 92
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Design Example - XNORs Used as Bit Pattern Comparator. . . . . . . . . . 92
Design Example - Full Adder Circuits . . . . . . . . . . . . . . . . . . 94
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Design Example - Half Adder Circuit. . . . . . . . . . . . . . . . . . . 96
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Design Example - Twoʼs-Complement Adder/Subtracter Circuit . . . . . . . . 98
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Design Example - Multiplexer . . . . . . . . . . . . . . . . . . . . . 100
Design Example - BCD Adder Circuit . . . . . . . . . . . . . . . . . . 102
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Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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Digital Logic Basics: Rapid Reference and Refresher iii
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iv Digital Logic Basics: Rapid Reference and Refresher
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Introduction and Purpose
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This simple purpose of this text is to concisely present essential digital logic topics and to
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present them with clarity. Some textbooks on the subject often omit levels of detail that
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could help the learner in examples and procedures. In some cases, an example showing
the beginning setup jumps to the result while leaving out crucial details that the student
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or reader might not yet grasp. Another situation is when a significant procedure may be
roughly described in two sentences and poorly described in such a way that it would only
apply to a special, simple case and would not be useful for larger, general situations.
This text aims to help the learner more quickly say “Aha! Now I get it.”
Refresher, Reference, and Introduction All in One
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It will help you to rapidly refresh your memory on definitions, concepts, and procedures.
If you have little or no knowledge of digital logic, it will also be useful as rapid
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introduction on its own. If you are taking an introductory course in digital electronics or
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digital logic, this will be a useful supplement because of the concise nature of the text.
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Topics are each covered in a few pages. Examples are presented on individual or facing
pages so there will be little need to flip back and forth between pages to recall what is
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being described. When you locate the general topic, the definitions, procedures, and
examples are all within just a few pages so it should be easy to find the definition,
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procedure, or example you need for reference.
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Whatʼs It All About?
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Boolean algebra defines digital or logic states (0 or 1) and operations (AND, OR, NOT).
Boolean algebra also defines properties, rules, laws, that govern the way logic states or
the variables that represent them are combined and manipulated.
Digital logic and Boolean algebra are related. Digital logic involves schematics and
circuits that can implement Boolean algebra operations, functions, and equations.
Digital Logic Basics: Rapid Reference and Refresher 1

Boolean algebra is a mathematics system or symbol/state manipulation system that
involves two (binary) states instead of numbers. These states are typically referred to
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using two numerals: 0 and 1. While two numerals are typically used as the symbols for
logic values, digital logic and Boolean algebra are ways to combine decisions involving
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two states for each of the various input conditions as well as each output result.
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Numeric values or alphanumeric characters can be represented by patterns of fixed-length
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groups of binary values. For example, the decimal number 1436 can be represented
using a pattern of binary values as 000010110011100. Depending on how a pattern is to
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be interpreted, it can represent numbers or it can represent characters to be displayed.
For example, the binary pattern 01101101 can represent then decimal number 109 for a
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calculation or measurement or it can represent the lower-case letter “m” to be displayed
on an information panel or as part of the electronic text of a document stored on a
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computer disk.
Logic equations and circuits can be developed to produce decisions or outcomes based on
binary state inputs. These include ways to perform electronic control functions for turning
things on or off based on inputs that are either on or off (or generally inputs and outputs
that appear in two different, binary states). Boolean equations and digital logic circuits
can also be developed in ways that will implement numeric calculations when working
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with binary patterns that are to be treated as number values. Ways to select or direct
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specific inputs to other parts of a circuit as intermediate results or outputs to another
system can also be designed.
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2 Digital Logic Basics: Rapid Reference and Refresher
The Scope and Whatʼs Inside
Basic digital logic is covered. Sequential or clocked circuits, encoders, decoders, and
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beyond are not included. This is because the objective is to give the reader a solid “leg
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up” in the essential, beginning concepts. Such a foundation will be invaluable when
studying more advanced topics in this subject. Specific topics covered here include:
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Number systems, representations, and decimal, binary, and hexadecimal conversion
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The ASCII code
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Logic gates, logic operations, and Boolean algebra
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Boolean algebra laws and properties
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Using Boolean algebra to simplify logic expressions
Schematics to/from logic equations
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Truth tables and Karnaugh maps (K-maps)
Creating truth tables and from Boolean algebra expressions
Using K-maps to derive the simplest Boolean algebra expressions for functions
Some classic design applications
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This was written to be used as a supplement in a college-level electronics course
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on introductory digital logic. The material was well received by the students who
appreciated the detail of the explanations and examples that supplemented or clarified
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steps of those in the textbook.
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The author has strived to use clear and detailed examples including the use of special
grouping or highlighting to draw attention to portions of descriptions or examples that are
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the focus of the current topic or step of the process.
Thanks
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Acknowledgement and thanks go to Mr. Obrin Griffin, Assistant Professor/Program
Chair of Electronics of Ivy Tech Community College of Indiana, Abid Din, Adjunct
Faculty, Nick Crockett, Mark Franks, Katherine Johnson, and Jeremy Moore, for their
encouragement, ideas, or just suffering through a semester with me as this text was
developed.

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Number Systems
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What comes after one?
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Ways to Represent Positive Numbers
A positive, fixed-point number in a base-R number system is written as

(N)R = (dn-1dn-2 . . . d2d1d0 . d-1d-2d-3 . . . d-k )R , where 0 ≤ di ≤ (R-1)R
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The corresponding decimal number is
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(N)10 = Cn-1Rn-1 + Cn-2Rn-2 + . . . + C1R1 + C0R0 + C-1R-1 + . . . + C-kR-k
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(N)10 = Cn-1Rn-1 + Cn-2Rn-2 + . . . + C1R + C0 + C-1R-1 + . . . + C-kR-k
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where 0 ≤ Ci ≤ (R-1)10
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Each di is a digit or symbol in the base-R number system, and each Ci is its equivalent
base-10 number obtained by using a table of correspondence similar to the one shown
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below. R denotes the radix, or base, of the number system and indicates how many
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symbols are used in its numeral alphabet.
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The whole-number part of each number is represented by digits with subscripts ≥ 0 and
the fractional part is represented by digits with subscripts < 0 (and shown here in red).
What we usually refer to as a “decimal point”, the period symbol or “point”, separates the
whole number part from the fractional part. The whole number part appears to the left of
that fractional separator and the fractional part appears to the right of the separator.

Table of Correspondence
Between Various Base Number Systems
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N10 N2 N3 N4 N5 N8 N16
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0 0 0 0 0 0 0
1 1 1 1 1 1 1
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2 10 2 2 2 2 2
3 11 10 3 3 3 3
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4 100 11 10 4 4 4
5 101 12 11 10 5 5
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6 110 20 12 11 6 6
7 111 21 13 12 7 7
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8 1000 22 20 13 10 8
9 1001 100 21 14 11 9
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10 1010 101 22 20 12 A
11 1011 102 23 21 13 B
12 1100 110 30 22 14 C
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13 1101 111 31 23 15 D
14 1110 112 32 24 16 E
15 1111 120 33 30 17 F
16 10000 121 100 31 20 10
Convert Base-10 Integer to Base-R Integer
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Step Procedure
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1 Set i = 1 and X0 = (N)10, the base-10 number to be converted.
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2 Divide Xi by R, the radix of the new number base.
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3 Set Xi+1 = ⎣ Xi / R⎦, the integer part of the division in step 2.
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4 Set ci = remainder resulting from division in step 2.
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5 If Xi+1 ≠ 0, then increment i by 1 and go back to step 2, otherwise proceed to step 6.
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6 Using a Table of Correspondence, convert the ciʼs to their proper base-R symbols, diʼs.
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STOP.
The base-R integer obtained is (N)R = (dn-1 dn-2 . . . d2 d1 d0)R
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Successive divisions are made beginning with the original number by the value of the
new base (R). From each division, the remainder is saved and converted to the base-R
symbol for that number and the whole-number part of the division result is used in the
next division step. This repeats until the whole-number part is zero. The new base-R
number is formed from the base-R symbols, right to left, in the order they were obtained.

Convert k-digit Base-R Integer to Base-10 Integer METHOD #1
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(N)R = (dk-1 dk-2 . . . d2 d1 d0)R
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Step Procedure
1 Convert each of the base-R digits, diʼs, to their base-10 equivalents, ciʼs .
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(N)R = (ck-1 ck-2 . . . c2 c1 c0)R
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2 Set i = 0 and X0 = 0.
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3 Increment i by 1.
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4 Calculate Xi = Xi-1 + ( ck-1 ) • Ri-1
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5 If i < k , go back to step 3, otherwise proceed to step 6.
6 STOP. The desired base-10 integer is (N)10 = Xk
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The decimal equivalent of the numeral from a weighted position in the original number
is multiplied it by the weight of the position (the base number raised to a power). Each of
these (ck-1) • Ri-1 results are summed to arrive at the equivalent base-10 value.
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Convert k-digit Base-R Integer to Base-10 Integer METHOD #2
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(N)R = (dk-1 dk-2 . . . d2 d1 d0)R
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Step Procedure
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1 Convert each of the base-R digits, diʼs, to their base-10 equivalents, ciʼs .
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(N)R = (ck-1 ck-2 . . . c2 c1 c0)R
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2 Set i = 0 and X0 = 0.
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3 Increment i by 1.
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4 Calculate Xi = R • Xi-1 + ck-1
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5 If i < k , go back to step 3, otherwise proceed to step 6.
6 STOP. The desired base-10 integer is (N)10 = Xk
Begin with a result of zero. Starting from the left a numeral of the original number is
converted to decimal and added to the result obtained so far. If more numerals remain,
multiply the result obtained so far by the value of the base number and proceed to the
next numeral, adding it to the result obtained so far and repeat this step, otherwise stop.

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Representations of Decimal Numbers 0-30
In Binary, Octal, Hexadecimal, and Binary-Coded Decimal
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N10 N2 Binary-Coded N2 grouped N8 N2 grouped N16
Decimal (BCD) as N8 as N16
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0 00000000 0000 0000 000 000 000 000 0000 0000 00
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1 00000001 0000 0001 000 000 001 001 0000 0001 01
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2 00000010 0000 0010 000 000 010 002 0000 0010 02
3 00000011 0000 0011 000 000 011 003 0000 0011 03
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4 00000100 0000 0100 000 000 100 004 0000 0100 04
5 00000101 0000 0101 000 000 101 005 0000 0101 05
6 00000110 0000 0110 000 000 110 006 0000 0110 06
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7 00000111 0000 0111 000 000 111 007 0000 0111 07
8 00001000 0000 1000 000 001 000 010 0000 1000 08
9 00001001 0000 1001 000 001 001 011 0000 1001 09
10 00001010 0001 0000 000 001 010 012 0000 1010 0A
11 00001011 0001 0001 000 001 011 013 0000 1011 0B
12 00001100 0001 0010 000 001 100 014 0000 1100 0C
13 00001101 0001 0011 000 001 101 015 0000 1101 0D
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14 00001110 0001 0100 000 001 110 016 0000 1110 0E
15 00001111 0001 0101 000 001 111 017 0000 1111 0F
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16 00010000 0001 0110 000 010 000 020 0001 0000 10
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17 00010001 0001 0111 000 010 001 021 0001 0001 11
18 00010010 0001 1000 000 010 010 022 0001 0010 12
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19 00010011 0001 1001 000 010 011 023 0001 0011 13
20 00010100 0010 0000 000 010 100 024 0001 0100 14
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21 00010101 0010 0001 000 010 101 025 0001 0101 15
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22 00010110 0010 0010 000 010 110 026 0001 0110 16
23 00010111 0010 0011 000 010 111 027 0001 0111 17
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24 00011000 0010 0100 000 011 000 030 0001 1000 18
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25 00011001 0010 0101 000 011 001 031 0001 1001 19
26 00011010 0010 0110 000 011 010 032 0001 1010 1A
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27 00011011 0010 0111 000 011 011 033 0001 1011 1B
28 00011100 0010 1000 000 011 100 034 0001 1100 1C
29 00011101 0010 1001 000 011 101 035 0001 1101 1D
30 00011110 0011 0000 000 011 110 036 0001 1110 1E

Examples - Converting FROM DECIMAL
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Convert the decimal number 5280 to hexadecimal (base 16)
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N10 = 528010 X0 = 5280 X0 / 16 = 5280 / 16 = 330 ,r=0 ∴ X1 = 330 c0 = 0 d0 = 0
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X1 / 16 = 330 / 16 = 20 , r = 10 ∴ X2 = 20 c1 = 10 d1 = A
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X2 / 16 = 20 / 16 = 1 ,r=4 ∴ X3 = 1 c2 = 4 d2 = 4
X3 / 16 = 1 / 16 = 0 ,r=1 ∴ X4 = 0 c3 = 1 d3 = 1
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STOP since last Xi = 0
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N10 = 528010 = N16 = d3 d2 d1 d0 = 14A016
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∴ 528010 = 14A016
Convert the decimal number 742 to octal (base 8)
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N10 = 74210 X0 = 742 X0 / 8 = 742 / 8 = 92 ,r=6 ∴ X1 = 92 c0 = 6 d0 = 6
X1 / 8 = 92 / 8 = 11 ,r=4 ∴ X2 = 11 c1 = 4 d1 = 4
X2 / 8 = 11 / 8 =1 ,r=3 ∴ X3 = 1 c2 = 3 d2 = 3
X3 / 8 = 1/8 =0 ,r=1 ∴ X4 = 0 c3 = 1 d3 = 1
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N10 = 74210 = N8 = d3 d2 d1 d0 = 13468
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∴ 74210 = 13468
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Convert the decimal number 742 to binary (base 2)
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N10 = 74210 X0 = 742 X0 / 2 = 742 / 2 = 371 ,r=0 ∴ X1 = 371 c0 = 0 d0 = 0
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X1 / 2 = 371 / 2 = 185 ,r=1 ∴ X2 = 185 c1 = 1 d1 = 1
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X2 / 2 = 185 / 2 = 185 ,r=1 ∴ X3 = 185 c2 = 1 d2 = 1
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X3 / 2 = 92 / 2 = 46 ,r=0 ∴ X4 = 46 c3 = 0 d3 = 0
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X4 / 2 = 46 / 2 = 23 ,r=0 ∴ X5 = 23 c4 = 0 d4 = 0
X5 / 2 = 23 / 2 = 11 ,r=1 ∴ X6 = 11 c5 = 1 d5 = 1
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X6 / 2 = 11 / 2 =5 ,r=1 ∴ X7 = 5 c6 = 1 d6 = 1
X7 / 2 = 5/2 =2 ,r=1 ∴ X8 = 2 c7 = 1 d7 = 1
X8 / 2 = 2/2 =1 ,r=0 ∴ X9 = 1 c8 = 0 d8 = 0
X9 / 2 = 1/2 =0 ,r=1 ∴ X10 = 0 c9 = 1 d9 = 1
N10 = 74210 = N2 = d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 = 10111001102
∴ 74210 = 10111001102

Examples - Converting TO DECIMAL Using Method #1
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Convert the base-16 number 3AF716 to decimal
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N16 = 3AF716 Base = 16 ... and the numerals are: 0 1 2 3 4 5 6 7 8 9 A B C D E F
Each numeral or symbol, di is in decimal range of 0 ≤ di ≤ 15
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The powers of the number base range from 3 down to 0
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using original numerals (N)10 = 316×163 + A16×162 + F16×161 + 716×160
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numerals converted to decimal (N)10 = 3×163 + 10×162 + 15×161 + 7×161
doing the calculations (N)10 = 3×4096 + 10×256 + 15×16 + 7×1
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(N)10 = 12288 + 2560 + 240 + 7
(N)10 = 15095
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Convert the base 8 number 407.158 to decimal
N8 = 407.158 Base = 8 ...and the numerals are: 0 1 2 3 4 5 6 7
The powers of the number base range from 2 down to -2
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using original numerals (N)10 = 48×82 + 08×81 + 78×80 + 18×8-1 + 58×8-2
numerals converted to decimal (N)10 = 4×82 + 0×81 + 7×80 + 1×8-1 + 5×8-2
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doing the calculations (N)10 = 4×64 + 0×8 + 7×1 + 1×(0.125) + 5×(0.015625)
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(N)10 = 256 + 0 + 7 + (0.125) + (0.078125)
(N)10 = 263.203125
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(N)10 = 263.203125
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Convert the base 2 number 10011.012 to decimal
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N2 = 10011.012 Base = 2 ...and the numerals are: 0 1
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The powers of the number base range from 4 down to -2
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using original numerals (N)10 = 12×24 + 02×23 + 02×22 + 12×21 + 12×20 + 02×2-1 + 12×2-2
numerals converted to decimal (N)10 = 1×24 + 02×23 + 02×22 + 1×21 + 1×20 + 0×2-1 + 1×2-2
doing the calculations (N)10 = 1×16 + 0×8 + 0×4 + 1×2 + 1×1 + 0×(0.5) + 1×(0.25)
(N)10 = 16 + 2 + 1 + (0.25)
(N)10 = 19.25
(N)10 = 19.25

Examples - Converting TO DECIMAL Using Method #2
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Convert the base-16 number 3AF716 to decimal
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N16 = 3AF716 Base = 16 ... and the numerals are: 0 1 2 3 4 5 6 7 8 9 A B C D E F
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original numerals, in order 3 A F 7
numerals converted to decimal 3 10 15 7
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doing the calculations X=3 more numerals remain
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X = 16×3 + 10 = 58 more numerals remain
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X = 16×943 + 7 = 15095 DONE no more numerals
N10 = 15095
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Convert the base 8 number 4078 to decimal
N8 = 4078 Base = 8 ...and the numerals are: 0 1 2 3 4 5 6 7
original numerals, in order 4 0 7
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numerals converted to decimal 4 0 7
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N10 = 263
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Convert the base 2 number 100112 to decimal
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N8 = 100112 Base = 2 ...and the numerals are: 0 1
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original numerals, in order 1 0 0 1 1
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numerals converted to decimal 1 0 0 1 1
X = 2×1 + 0 =2 more numerals remain
N10 = 19

Binary Coded Decimal Number Representation
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A combination of a decimal number representation and a binary number representation is
called “binary-coded decimal” or “BCD.”
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BCD numbers were already presented earlier in this chapter in a table. This section will
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offer more detail.
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The BCD number format basically involves each decimal numeral of a decimal number
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being represented by four bits. The four-bit BCD combinations represent decimal
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numbers in the range of zero through nine. A six-dignt decimal number is written as
twenty-four bits using BCD format. A sixteen bit BCD number will represent a four-digit
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decimal number.
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Examples of Decimal Numbers
Written in Binary-Coded-Decimal Format
Decimal Number Written as BCD

3 0011
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3
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17 0001 0111
1 7
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19 0001 1001
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1 9
20 0010 0000
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2 0
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475 0100 0111 0101
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4 7 5
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5280 0100 0010 1000 0000
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5 2 8 0
6000 0110 0000 0000 0000
6 0 0 0
Decimal numbers converted to BCD format and binary numbers converted to BCD
format can be used as inputs to displays for calculators or other numeric displays. It

is easier to convert a number to BCD and to prepare it for visual recognition using the
familiar seven-segment LED (light-emitting diode) or LCD (liquid crystal display) found
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on calculators and other electronics...even including some billboards that display fuel
prices for highway travelers to see!
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Arithmetic and Negative Numbers
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The previous chapter described ways to represent numbers. Attention was given to our
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everyday decimal numbers, binary, octal, and hexadecimal numbers. Specifically, positive
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number representations were addressed.
This chapter addresses a way to add two numbers and it can be applied to any number
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base. The detailed description of basic addition is useful in a chapter at the end of this
text in that a digital circuit is designed to add two four-bit binary numbers. That adder
circuit can be used with other adder circuits to add larger numbers.
This chapter also looks at ways to represent negative numbers in binary as well as
positive numbers, both in the same binary format.
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After all this, what good are numbers? What can we do with them?
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Arithmetic is the answer.
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This chapter shows examples of the arithmetic operations of addition, subtraction,
multiplication, and division in the various number bases. For each arithmetic operation
c
and for each number base, the process of arriving at a numeric result is essentially the
t
same. The only difference is the number of symbols involved in representing the range of
f
numerals in the different number systems.
d r a
Adding Numbers
y
Adding two numbers results in the arithmetic sum of those two numbers. Not surprising.
Each number is comprised of one or more numerals occupying positions having
p
magnitude weights of sequentially increasing powers of the number base. Adding two
o
numbers is broken down to adding individual numerals from each number in common,
weighted positions.
c
Adding the two numbers involves calculating the sums of the pairs of numerals, one from
t
each of the numbers, sharing common weighted positions. This begins with the position
f
having the lowest weight (the position farthest to the right) and continues to the next
ra
higher weighted position (to the left) until all weighted positions represented in the two
numbers have been processed. When the numerals of one number have been exhausted
and numerals remain in the other number, zeros are to be substituted for the missing
d
numerals.
The sum of any of the two numerals in a given weighted position is either less than
the magnitude of the number base or it is greater than or equal to the magnitude of
the number base. This sum in a given weighted position is always less than twice the
magnitude of the number base. If the sum is greater than or equal to the magnitude of
y
the number base, a value of 1 is “carried” over to the next higher weighted position and
p
is included in forming the sum for that weighted position. If the sum is less than the
magnitude of the number base, a value of “0” is effectively “carried” over to the next
o
higher weighted position.
c
To generalize the process of determining the sum assigned to a common weighted
t
position, the numeral occupying that position in each number is summed and the number
f
carried over (0 or 1) from the previous weighted position is also included to form the new
sum. From that sum, the numeral in the right-most position (least significant position) is
a
recorded as the numeral for the sum in that weighted position. The second numeral or left
r
numeral (most significant position) is carried over to the next higher weighted position.
d
In effect, every summing in a weighted position involves three “inputs”:
• the numeral from that position in one number,
• the numeral from that position in the other number,
• the carried value “into” that position (or zero for the very first summing) from the
previous positionʼs sum

Moreover, every summing in a weighted position involves two “outputs”:
• the resulting “sum” numeral
y
• the resulting “carry out” numeral
p
When adding two numbers, A and B, weʼll use S to represent the resulting number sum.
o
The number A and B have numerals AN-1…A3A2A1A0 and BN-1…B3B2B1B0 , respectively.
c
The resulting number sum, S, will have numerals CN-1SN-1SN-2…S3S2S1S0 . Note that CN-1 is
the last of the carry values and will either be 1 or a leading 0. For each weighted position,
t
k, the resulting sum numeral for that position is Sk and it is calculated as the sum of the
f
two numerals, Ak and Bk from the respective numbers and from the “carry” numeral, Ck-1
ra
calculated from the previous lower weighted position. The carry numeral, Ck, resulting
from the sum calculation of the given weighted position, k, is carried over to be included
in the sum calculation of numerals in the next higher (to the left) weighted position.
d
position (k) N N-1 3 2 1 0
C Carry in in CN-1 CN-2 … C2 C1 C0 0

A Addend in AN-1 … A3 A2 A1 A0
y
B Addend in + BN-1 … B3 B2 B1 B0
p
S Sum out CN-1 SN-1 … S3 S2 S1 S0
C out
o
Carry out CN-1 … C3 C2 C1 C0
c
Magnitude of sum of
weighted position CN-1 CN-1SN-1 … C3S3 C2S2 C1S1 C0S0
f t
When adding two numbers, for each weighted numeral position, k, Ak + Bk + Ck -1 = CkSk .
d r a
NOTE: The term CkSk represents a number made of two numerals, Ck and Sk , where the
Ck numeral is in a position to the left of the Sk numeral.
The excruciating detail included here for adding two numbers will be useful later in the
design and development of an adder logic circuit. Such detail will not be included in
subtraction, multiplication, or division.

Examples of Adding Two Numbers – Decimal
y
Calculate 17 + 20
p
position (k) 4 3 2 1 0
o
C Carry in in 0 0 0
c
A Addend in 1 7
B in + 2 0
t
Addend
f
S Sum out 0 3 7
a
C Carry out out 0 0
r
Magnitude of sum of
weighted position 03 07
d
Calculate 192 + 566
C Carry in in 1 0 0 0
A Addend in 1 9 2
y
B Addend in + 5 6 6
p
S Sum out 7 5 8
o
C Carry out out 0 1 0
Magnitude of sum of
c
weighted position 07 15 08
t
Calculate 948 + 83
a f
r
A in 9 4 8
d
Addend
B Addend in + 8 3
S Sum out 1 0 2 7
Magnitude of sum of

Examples of Adding Two Positive Numbers – Binary
y
Calculate 100012 + 101002 (equivalent to decimal addition 17 + 20 = 37)
p
position (k) 5 4 3 2 1 0
o
C Carry in in 1 0 0 0 0 0
c
A Addend in 1 0 0 0 1
B in + 1 0 1 0 0
t
Addend
f
S Sum out 1 0 0 1 0 1
a
C Carry out out 0 0 0 0 0
r
Magnitude of sum of
weighted position 10 00 01 00 01
d
position (k) 5 4 3 2 1 0
A Addend in 1 1 0
y
B Addend in + 1 1
p
S Sum out 1 0 0 1
o
Magnitude of sum of
c
t
a f
position (k) 5 4 3 2 1 0
r
C Carry in in 1 1 1 1 1 0
A in 1 1 1 1 1
d
Addend
B Addend in + 1 1 0 1
S Sum out 1 0 1 1 0 0
C Carry out out 1 1 1 1 1
Magnitude of sum of
weighted position 10 11 11 10 10

Positive and Negative Numbers in Binary: Twoʼs-Complement Form
y
Only positive numbers have been given attention thus far. Now it is time to look at a
common way to represent both positive and negative numbers in binary.
p
A negative number in binary can be written as a positive number with a minus sign in
o
front of it. When performing calculations by hand, this may be the preferred method.
c
However, to be represented and used in digital logic circuits, there is no room for a minus
sign. Recall that the only numerals or symbols we have to use are 0 and 1. These two
t
numerals can be used in a special place to represent the sign of a binary number.
f
This method in binary is called the “twoʼs-complement” representation of numbers, both
ra
positive and negative. Hereʼs how it is done:
First, it will be necessary to write positive and negative numbers in binary using some
d
fixed length, or number of numerals or bits. For the time-being, eight bits will be the
length of our number.
Second, the most significant bit will be defined as the “sign bit.” If the sign bit is a 0, the
number is interpreted to be positive. If the sign bit is a 1, the number is interpreted to be
negative.
y
Third, the remainder of the bits in the binary number represent the magnitude of the
p
number (how positive it is or how negative it is). Those bits represent positive numbers
the way weʼve seen so far. However, those bits represent negative numbers differently
o
than what weʼve seen for positive numbers.
c
Examples are shown here first with an explanation to follow.
t
The list on the next page shows a count in decimal from 5 down to -5 and the
f
corresponding twoʼs-complement representation of those numbers. Eight bits will be the
a
length of the binary numbers in this twoʼs-complement format. Note the sign bit in the
r
most-significant bit position (the left-most bit) and the way the magnitude is written in
the remaining seven bits to the right.
d
Representing Positive and Negative Numbers
y
Decimal Number Twoʼs-Complement
Form Sign Binary Form
p
5 positive 00000101
o
4 positive 00000100
c
6 positive 00000011
2 positive 00000010
t
1 positive
f
00000001
0 (treated as) positive 00000000
a
-1 negative 11111111
r
d
Some parts of procedures are similar when converting signed decimal numbers to
y
twoʼs-complement form as well as converting a twoʼs-complement number to a signed
p
decimal. Here are some names and definitions of some important methods.
c o
Method / Step Procedure
Invert Bits Change each original 0 bit to a 1 bit and also change each original 1
t
bit to a 0.
f
Oneʼs-Complement Given a pattern of bits as in a binary number representation, the
a
oneʼs complement is obtained when all bits are inverted.
r
Twoʼs-Complement Given a pattern of bits, the twoʼs-complement is obtained by first
d
inverting all bits, then add 1 to the numeric result.
Another way say describe this is to take the oneʼs-complement and
then add 1 to the numeric result.
twoʼs-complement = oneʼs-complement + 1

Procedure to Convert Signed Decimal Number to Twoʼs-Complement Binary
y
Coverting a signed decimal number to twoʼs-complement binary format is a simple
process that includes a couple extra steps if the number to be converted is negative.
p
Positive numbers in twoʼs-complement form look like the normal binary numbers seen so
o
far and the size or magnitude of the number is fairly easy to glean just from a glance at
c
the number.
t
Negative numbers in twoʼs-complement form still look like binary numbers, of course.
f
However, the leading 1 in the sign bit position and some nearby 1s that may occupy
the higher-order bits can sometime visually distort the meaning of the rest of the bits
ra
that represents the magnitude of the number. For example, while the twoʼs-complement
number 11111111111111111101 might look like a “big” number at first glance with all the
d
1s it contains, it is actually pretty close to zero and represents a value of negative three
(–3).
Step Procedure
1 Determine the number of bits, k, that will be used to represent the number. The number
y
to convert, N, must be in the range -2k ≤ N ≤ (2k-1)
p
2 If the number is negative, proceed to step 4.
o
3 Positive number: Convert this positive number to binary and insert enough leading 0s
(insert them to the left) to fill all k bit positions.
c
STOP. The positive number conversion to twoʼs-complement form is complete.
t
4 Negative number: Ignore the negative sign and convert the resulting positive number to
f
binary and insert enough leading 0s (insert them to the left) to fill all k bit positions.
a
5 From the binary number from the previous step, generate its oneʼs-complement
r
(simultaneously change all original 1s to 0s and all original 0s to 1s).
6 Add 1 to the number from the previous step.
d
STOP. The negative number conversion to twoʼs-complement form is complete.

Examples - Convert Signed Decimal Numbers in Twoʼs-Complement Form
y
Convert the decimal number +35 to an eight-bit twoʼs-complement binary number
p
The number is positive. Convert it to binary then insert enough 0s to the left side of the binary number to
fill all eight bit positions.
c o
Convert 3510
t
3510 = 1000112 00100011 convert to 8-bit binary DONE
ra f
sign bit 0=positive
d
Convert the decimal number -35 to an eight-bit twoʼs-complement binary number
The number is negative. Drop the negative sign and convert the positive result to binary then insert enough
0s to the left side of the binary number to fill all eight bit positions, then take the twoʼs-complement of that
positive number.
Convert -3510
y
3510 = 1000112 001000112 drop “–” sign and convert to 8-bit binary
p
110111002 invert all bits
o
+ 12 add 1
f t
-3510 =
c
110111012 DONE
a
sign bit 1=negative
d r
Procedure to Convert Twoʼs-Complement Binary to Signed Decimal Number
y
Coverting twoʼs-complement numbers to decimal is simple for positive nubers and
includes a couple extra steps if the number to be converted is negative.
p
Numbers with a 0 sign bit are positive and those numbers are directly converted to binary.
o
Numbers with a 1 sign bit are negative and those numbers require extra steps to
c
essentially obtain the (positive) absolute value, convert that to decimal, and than add a
t
negative sign in front of the result because we normally see negative decimal numbers
f
with a “negative sign” in front of them.
ra
Step Procedure
d
1 If the first bit of the number is 1, the number is negative so proceed to step 3.
2 Positive number: Convert the remaining bits to a decimal number.
STOP.
The twoʼs-complement positive number conversion to decimal is complete.
3 Negative number: Invert all bits (take the oneʼs complement of the number).
y
4 Add 1 to the number from the previous step.
p
5 Convert the remaining bits to a decimal number and prefix it with a negative sign.
STOP.
o
The twoʼs-complement negative number conversion to decimal is complete.
f t c
d r a
Examples - Convert Signed Decimal Numbers in Twoʼs-Complement Form
y
Convert the twoʼs-complement 10-bit binary number 00011010112 to signed decimal.
p
Convert 00011010112
c o
00011010112 : 0011010112 0 0011010112 sign bit 0 (positive number)
t
sign bit 0=positive
a f
0011010112 = 10710 convert the magnitude bits to decimal
r
therefore 00011010112 = +10710 DONE
d
Convert the twoʼs-complement 8-bit binary number 111000012 to signed decimal.
Convert 111000012
p y
111000012 : 111000012 1 11000012 sign bit 1 (negative number)
o
sign bit 1=negative
c
00111102 invert magnitude bits (oneʼs complement)
t
+ 12 add 1
f
= 00111112
a
00111112 = 3110 convert magnitude bits to decimal
d r
–3110 prefix with the negative sign
therefore 111000012 = –3110 DONE

Addition Using Twoʼs-Complement Binary Numbers
y
Step Procedure
1 Simple. Just perform the addition of the two numbers to get the result...and be sure the
p
sign bit of the result is still correct.
o
NOTE
c
Remember that both twoʼs-complement numbers must be
t
the same length. That is, each original number must be
f
represented in the same number of bits. The result is to be
ra
the same length, as well, even if it means omitting a leading
bit resulting from a final carry out of the sign bit position.
d
If the two numbers going into the operation have the same sign bit, the resulting number
should also have the same sign bit value. If the sign bit is not the same as the sign bit
common to both numbers, an “overflow” condition exists. In overflow, the number result
is too large to fit within the length of bits used by the two original numbers.
When overflow exists, the number result may still be useful if the conversions and
calculations are being done by hand. In that case, the result just happens to be an extra bit
y
longer than the original numbers going in to the calculation. However, in the more likely
p
case that the conversions and calculations are handled by an electronic digital circuit, the
number result will be fixed in length and will therefore represent an invalid result.
o
When adding two numbers of the same sign with a result of greater than the range of
c
the possible values for the designated length of the number, the resulting sign bit will be
t
opposite what is expected. That is, two positive twoʼs-complement numbers that are large
f
enough will result in a twoʼs complement sum that is negative. Likewise, two negative
twoʼs-complement numbers that are large enough will result in a twoʼs complement sum
a
that is positive. This indicates overflow. In either of these two cases, the magnitude will
r
be erroneous as well.
d
When adding a positive twoʼs-complement number to a negative twoʼs complement
number, the result will always be correct, both sign and magnitude.
Adding the negative of a number to another number is the way to achieve subtraction. To
form the negative of a twoʼs-complement number, generate the twoʼs-complement of the
twoʼs-complement number.

Examples of Twoʼs-Complement Addition
y
Add 000001002 + 000001102 equivalent to decimal adding of 4 + 6
p
In this situation, two valid, positive, twoʼs-complement numbers are being added. The length of each is
fixed at eight bits. The sign bit positive in each number. Everything fits at the start.
o
Intended Decimal Twoʼs Complement Decimal Equivalent of
c
Twoʼs Complement
410 0 0000100 2 410
t
+ 610 + 0 0000110 2 + 610
f
1010 0 0001010 2 1010 Correct
ra
Add 111001012 + 111100102 equivalent to decimal adding of -27 + (-14)
d
Similar to above: two valid, negative, eight-bit, twoʼs-complement numbers to be added.

Twoʼs Complement
-2710 1 1100101 2 -2710
+ -1410 + 1 1110010 2 + -1410
-4110 1 1 1010111 2 -4110 Correct
y
To maintain eight bits in the twoʼs-complement result, the left-most carry was omitted.
o p
Add 01002 + 01102 (both twoʼs-complement) equivalent to decimal adding of 4 + 6
c
Similar to first example except the length is reduced to four bits. Two valid, positive, twoʼs-complement
numbers are to be added. Everything fits at the start. Observe what happens in this case.
f t
Twoʼs Complement
a
410 0 100 2 410
r
+ 610 + 0 110 2 + 610
1010 ??? 1 010 2 Wrong ! ??? -610 Wrong !
d
Each addend has a positive sign bit. We expect a positive result when adding two positive numbers.
However, within the four-bit, twoʼs-complement number used here, adding +4 to +6 results in a negative
number (-6) which makes no sense. Overflow “happened.” For a digital circuit that handles this addition,
overflow would be indicated and the result would be considered unreliable. Just looking at the bits with
our eyes, it is seen that if we prefix the result with a 0 to make a longer number with a positive sign bit, the
result is a positive 10 would be meaningful. However, the cold-hearted circuit will not be so insightful.

Subtraction Using Twoʼs Complement Binary Numbers
y
Remember? Subtraction of one number, B, from another number, A, involves adding the
negative of B to A. Subtraction is done in twoʼs-complement binary arithmetic the same
p
way. Produce the twoʼs-complement of the number to be subtracted and then add it to the
o
other number.
c
Step Procedure
To calculate A - B
f t
1 Form the twoʼs-complement of B by inverting all of the bits of B and then adding one.
This result is the negative of B.
ra
2 Add the result of the previous step (the negative of B) to A to get the final answer...and
be sure the sign bit is correct.
d
Overflow can exist in subtraction as well. See the discussion on overflow in the previous
section.
Examples of Twoʼs-Complement Subtraction
p y
Use eight-bit, twoʼs complement numbers to subtract 3710 from 8210 .
o
This will be handled by adding (-3710) to 8210.
Convert (-3710) and 8210 each to the twoʼs-complement format using eight bits.
c
8210 = 0 10100102
f t
3710 = 0 01001012
-3710 = 1 10110112
r a
Twoʼs Complement
d
8210 8210 0 1010010 2 8210
– 3710 + -3710 + 1 1011011 2 + -3710
4510 4510 1 0 0101101 2 4510 Correct
therefore 00101101 2 = 4510

Use eight-bit, twoʼs complement numbers to subtract 1810 from -7610 .
This will be handled by adding (-1810) to 7610.
y
Convert (-1810) and 7610 each to the twoʼs-complement format using eight bits.
p
7610 = 0 10011002
o
-7610 = 1 01101002
c
1810 = 0 00100102
-1810 = 1 11011102
f t
Twoʼs Complement
ra
-7610 -7610 1 0110100 2 -7610
– 1810 + -1810 + 1 1101110 2 + -1810
-9410 -9410 1 1 0100010 2 -9410 Correct
d
therefore 1 0100010 2 -9410
y
Use eight-bit, twoʼs complement numbers to subtract 8310 from -10010 .
p
This will be handled by adding (-8310) to -10010.
Convert (-8310) and -10010 each to the twoʼs-complement format using eight bits.
o
10010 = 0 11001002
c
-10010 = 1 00111002
f t
8310 = 0 10100112
-8310 = 1 01011012
r a
Twoʼs Complement
d
-10010 -10010 1 0011100 2 -10010
– 8310 + -8310 + 1 0101101 2 + -8310
-18310 -18310 ??? 1 0 1001001 2 ??? +7310 Wrong !
The sign of the result is positive when it was expected to be negative. An overflow condition exists so the
result is unreliable and out of the range of what can be represented in eight-bit, twoʼs complement form.
therefore we do not have an answer

Use eight-bit, twoʼs complement numbers to subtract -1810 from -7610 .
This will be handled by adding -(-1810) to -7610. This turns out to be adding +1810 to -7610.
y
Convert (-1810) and -7610 each to the twoʼs-complement format using eight bits.
p
7610 = 0 10011002
o
-7610 = 1 01101002
c
1810 = 0 00100102
t
f
Twoʼs Complement
-7610 -7610 1 0110100 2 -7610
a
– -1810 + 1810 + 0 0010010 2 + 1810
r
-5810 -5810 1 1000110 2 -58 10 Correct
d
therefore 1 1000110 2 -5810
p y
c o
a f t
d r
Binary Multiplication
y
Multiplication of two binary numbers is similar to decimal multiplication. The examples
here will involve positive numbers in “straight” binary form (with no sign bit).
p
In handling signed numbers, convert any negative numbers to positive, do the
o
multiplication, then set the sign or convert the resulting product as follows: the sign will
c
be positive if the signs of the original numbers were the same, otherwise, the sign of
the product will be negative. If twoʼs-complement numbers were used and the result is
t
determined to be negative, convert the resulting product to become negative by obtaining
f
the resultʼs twoʼs-complement form.
ra
Examples - Binary Multiplication
carry-in value
d
Find the product of 10012 and 1112
×
equivalent to product of 9 and 7
1 0
1
0
1
1
1 ×
9
7
y
1 0 0 1
1 0 0 1
p
1 0 0 1
1 1 1 0 1 1 = 63
Find the product of 110012 and 10112
c o equivalent to product of 25 and 11
f t
1 1 0 0 1 25
× 1 0 1 1 × 11
a
carry-in value 1 1 1
r
1 1
1 1 0 0 1
1 1 0 0 1
d
0 0 0 0 0
1 1 0 0 1
1 0 1 0 1 0 0 1 1 = 275
column total 10 10 10 11 10 0 1 1
carry to next column 1 1 1 1 1

Find the product of 11112 and 11112 equivalent to product of 15 and 15
This example is given to illustrate “large” carry values that can occur when multiplying binary numbers.
y
The carry value into subsequent columns can become large, yet they eventually taper off to nothing.
p
1 1 1 1 15
o
× 1 1 1 1 × 15
carry-in value 1 10 11 11 10 1
c
1 1 1 1
1 1 1 1
t
1 1 1 1
f
1 1 1 1
a
1 1 1 0 0 0 0 1 = 225
r
column total 1 11 101 110 110 100 10 1
carry to next column
d
1 1 10 11 11 10 1
p y
c o
a f t
d r
Binary Division
y
Division of two binary numbers is similar to decimal division. The examples here will
involve positive numbers in “straight” binary form (with no sign bit).
p
In handling signed numbers, convert any negative numbers to positive, do the division,
o
then set the sign or convert the resulting product as follows: the sign will be positive if
c
the signs of the original numbers were the same, otherwise, the sign of the result will
be negative. If twoʼs-complement numbers were used and the result is determined to
t
be negative, convert the quotient result to become negative by obtaining the resultʼs
f
twoʼs-complement form.
ra
Binary division is fairly simple because each numeral to be included in the quotient is
either going to be 0 or 1.
d
Example - Binary Division
Find the quotient 11100102 divided by 1102 equivalent to 114 divided by 6
y
1 0 0 1 1 19
110 1 1 1 0 0 1 0 = 6 114
p
– 1 1 0
1 0
o
– 0
c
1 0 0
– 0
t
1 0 0 1
f
– 1 1 0
1 1 0
a
– 1 1 0
r
0
d
Hexadecimal Addition
y
Addition of two hexadecimal numbers is similar to decimal number addition. The
examples that follow will involve positive numbers.
o p
c
Addition Table for Hexadecimal Numbers
t
0 1 2 3 4 5 6 7 8 9 A B C D E F
f
0 0 1 2 3 4 5 6 7 8 9 A B C D E F
ra
1 1 2 3 4 5 6 7 8 9 A B C D E F 10
2 2 3 4 5 6 7 8 9 A B C D E F 10 11
3 3 4
d
5 6 7 8 9 A B C D E F 10 11 12
4 4 5 6 7 8 9 A B C D E F 10 11 12 13
5 5 6 7 8 9 A B C D E F 10 11 12 13 14
6 6 7 8 9 A B C D E F 10 11 12 13 14 15
7 7 8 9 A B C D E F 10 11 12 13 14 15 16
y
8 8 9 A B C D E F 10 11 12 13 14 15 16 17
9 9 A B C D E F 10 11 12 13 14 15 16 17 18
p
A A B C D E F 10 11 12 13 14 15 16 17 18 19
o
B B C D E F 10 11 12 13 14 15 16 17 18 19 1A
c
C C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B
t
D D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C
f
E E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D
a
F F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E
d r
Examples - Hexadecimal Addition
y
Find the sum of hexadecimal numbers of 2716 and 1616
p
o
carry-in value
2 7 16 39 10
c
+ 1 6 16 + 22 10
3 D 16 61 10
f t
column total 3 D
ra
d
Find the sum of hexadecimal numbers of 7FFF16 and E3B916
carry-in value 1 1 1 1
7 F F F 16 32767 10
+ E 3 B 9 16 + 58297 10
1 6 3 B 8 16 91064 10
y
column total 16 13 1B 18
p
carry to next column 1 1 1 1
c o
Find the sum of hexadecimal numbers of 40216 and 3F16
f t
carry-in value 1
4 0 2 16 1026 10
a
+ 3 F 16 + 63 10
r
4 4 1 16 1089 10
d
column total 4 4 11
carry to next column 1

Hexadecimal Subtraction
y
Subtraction of two hexadecimal numbers is similar to decimal number subtraction. The
p
The following table shows the result of subtracting one hexadecimal number (the
o
subtrahend) from another hexadecimal number (the minuend). Each box in the results
c
part of the table list the result and, if necessary, the amount to be borrowed from the next
position to the left in the original numbers.
f t
ra
Subtraction Table for Hexadecimal Numbers
d
Minuend Minuend
– Subtrahend
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 b1 0 1 2 3 4 5 6 7 8 9 A B C D E F
1 b1 F 0 1 2 3 4 5 6 7 8 9 A B C D E
2 E F 0 1 2 3 4 5 6 7 8 9 A B C D
y
b1 b1
3 b1 D b1 E b1 F 0 1 2 3 4 5 6 7 8 9 A B C
p
4 b1 C b1 D b1 E b1 F 0 1 2 3 4 5 6 7 8 9 A B
o
5 b1 B b1 C b1 D b1 E b1 F 0 1 2 3 4 5 6 7 8 9 A
c
6 A B C D E F 0 1 2 3 4 5 6 7 8 9
Subtraend
b1 b1 b1 b1 b1 b1
t
7 b1 9 b1 A b1 B b1 C b1 D b1 E b1 F 0 1 2 3 4 5 6 7 8
f
8 b1 8 b1 9 b1 A b1 B b1 C b1 D b1 E b1 F 0 1 2 3 4 5 6 7
a
9 b1 7 b1 8 b1 9 b1 A b1 B b1 C b1 D b1 E b1 F 0 1 2 3 4 5 6
r
A b1 6 b1 7 b1 8 b1 9 b1 A b1 B b1 C b1 D b1 E b1 F 0 1 2 3 4 5
d
B b1 5 b1 6 b1 7 b1 8 b1 9 b1 A b1 B b1 C b1 D b1 E b1 F 0 1 2 3 4
C b1 4 b1 5 b1 6 b1 7 b1 8 b1 9 b1 A b1 B b1 C b1 D b1 E b1 F 0 1 2 3
D b1 3 b1 4 b1 5 b1 6 b1 7 b1 8 b1 9 b1 A b1 B b1 C b1 D b1 E b1 F 0 1 2
E b1 2 b1 3 b1 4 b1 5 b1 6 b1 7 b1 8 b1 9 b1 A b1 B b1 C b1 D b1 E b1 F 0 1
F b1 1 b1 2 b1 3 b1 4 b1 5 b1 6 b1 7 b1 8 b1 9 b1 A b1 B b1 C b1 D b1 E b1 F 0

Examples - Binary Subtraction
y
Note that the “Borrow Effect” row shows the hexadecimal value of any borrowing and
that an original borrow effect may be modified and marked out due to a subsequent
p
borrow effect.
o
Subtract 3310 from 10010 after converting them to hexadecimal
c
Minuend 10010 = 6416
t
Subtrahend 3310 = 2116
f
Borrow Effect
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Minuend 6 4 16 100 10
– Subtrahend – 2 1 16 – 33 10
Result 4 3 16 67 10
d
Subtract 400016 from 82516 (both are hexadecimal)
Minuend
Subtrahend
400016
C2516
=
=
1638410
310910
p y
F F
Borrow Effect (Hex) 3 10 10 10
o
Minuend 4 0 0 0 16 16384 10
– Subtrahend – C 2 5 16 – 3109 10
c
Result 3 D D B 16 13275 10
a f t
Subtract 3310 from 6232110 after converting them to hexadecimal
r
Minuend 804910 = 1F7116
Subtrahend 396210 = F7A16
d
1E 16
Borrow Effect (Hex) 0 E 6 11
Minuend 1 F 7 1 16 8049 10
– Subtrahend – F 7 A 16 – 3962 10
Result F F 7 16 4087 10

Hexadecimal Multiplication
y
Multiplication of two hexadecimal numbers is similar to decimal multiplication. The
p
While binary, decimal, or hexadecimal multiplication can be performed on many
o
calculators, these are done the “long” way...on paper. To help in the multiplication and
c
carry resulting from two hexadecimal numbers, refer to the following hexadecimal
multiplication table.
f t
ra
Multiplication Table for Hexadecimal Numbers
× 0 1 2 3 4 5 6 7 8 9 A B C D E F
d
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 1 2 3 4 5 6 7 8 9 A B C D E F
2 0 2 4 6 8 A C E 10 12 14 16 18 1A 1C 1E
3 0 3 6 9 C F 12 15 18 1B 1E 21 24 27 2A 2D
4 0 4 8 C 10 14 18 1C 20 24 28 2C 30 34 38 3C
y
5 0 5 A F 14 19 1E 23 28 2D 32 37 3C 41 46 4B
p
6 0 6 C 12 18 1E 24 2A 30 36 3C 42 48 4E 54 5A
o
7 0 7 E 15 1C 23 2A 31 38 3F 46 4D 54 5B 62 69
c
8 0 8 10 18 20 28 30 38 40 48 50 58 60 68 70 78
9 0 9 12 1B 24 2D 36 3F 48 51 5A 63 6C 75 7E 87
f t
A 0 A 14 1E 28 32 3C 46 50 5A 64 6E 78 82 8C 96
B 0 B 16 21 2C 37 42 4D 58 63 6E 79 84 8F 9A A5
r a
C 0 C 18 24 30 3C 48 54 60 6C 78 84 90 9C A8 B4
D 0 D 1A 27 34 41 4E 5B 68 75 82 8F 9C A9 B6 C3
d
E 0 E 1C 2A 38 46 54 62 70 7E 8C 9A A8 B6 C4 D2
F 0 F 1E 2D 3C 4B 5A 69 78 87 96 A5 B4 C3 D2 E1

Examples - Binary Multiplication
y
Find the product of 1916 and 816 equivalent to product of 25 and 8
p
1 9 16 25 10
× 8 10 × 8 10
o
carry-in value
c
C 8
t
C 8 16 = 200 10
f
column total
ra
d
Find the product of 7B16 and 11D716 equivalent to product of 123 and 4567
7 B 16 123 10
× 1 1 D 7 10 × 4567 10
3 5 D
6 3 F
y
7 B
7 B
p
8 9 2 4 D 16 = 561741 10
o
column total 8 19 12 14 D
c
carry to next column 1 1 1
f t
Find the product of 7F3A16 and 3F0816 equivalent to product of 32570 and 16136
a
7 F 3 A 16 32570 10
r
× 3 F 0 8 10 × 16136 10
d
3 F 9 D 0
0 0 0 0
7 7 4 6 6
1 7 D A E
1 F 5 3 3 F D 0 16 = 525549520 10
column total 1 F 15 13 23 F D 0
carry to next column 1 1 2

Addition of Binary-Coded Decimal Numbers
y
BCD numbers are four-bit binary numbers representing decimal values zero through nine.
Adding two BCD numbers, with a carry-in value (bit), must result in an output that is a
p
BCD number zero through nine with a carry-out value (bit). The carry-in bit or carry-out
o
bit will be either 0 or 1. The following table lists all the possible results of BCD addition
with normal binary addition and what the BCD result should be, with any correction.
t c
Results of BCD Addition Using Binary Adder and Correction
f
Intermediate Binary Adder Results Necessary BCD Adder Output
ra
Decimal
When Adding (A + B + Cin) as Binary When Adding (A + B + Cin) as BCD
Cout* S3* S2* S1* S0* Cout S3 S2 S1 S0
d
0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 1 0 0 0 0 1
2 0 0 0 1 0 Results 0 0 0 1 0
3 0 0 0 1 1 OK 0 0 0 1 1
4 0 0 1 0 0 0 0 1 0 0
5 0 0 1 0 1 No 0 0 1 0 1
6 0 0 1 1 0 correction 0 0 1 1 0
0 0 1 1 1 needed 0 0 1 1 1
y
7
8 0 1 0 0 0 0 1 0 0 0
9 0 1 0 0 1 0 1 0 0 1
p
10 0 1 0 1 0 Correction 1 0 0 0 0
11 0 1 0 1 1 1 0 0 0 1
needed
o
12 0 1 1 0 0 1 0 0 1 0
13 0 1 1 0 1 here 1 0 0 1 1
c
14 0 1 1 1 0 Add 6 to 1 0 1 0 0
15 0 1 1 1 1 binary 1 0 1 0 1
t
16 1 0 0 0 0 adder 1 0 1 1 0
f
17 1 0 0 0 1 1 0 1 1 1
result and
18 1 0 0 1 0 1 1 0 0 0
set Cout=1
a
19 1 0 0 1 1 1 1 0 0 1
r
Addition of BCD numbers is tricky because it involves binary number addition and some
special rules to correct the result for proper decimal digit calculation. Adding normal
d
binary numbers results in normal binary numbers. While BCD numbers can be added as
binary numbers...as a step in the process...BCD numbers are not normal binary numbers.
Normal binary addition of two, four-bit numbers can result in a four-bit number that
is greater than nine. Binary adder output greater than nine is manifest in a result that
(a) includes the four bits being greater than nine, or (b) when the carry-out bit value is 1.

When the adder result is zero through nine and with no carry out, the BCD numeral adder
output is the same and needs no correction.
y
When the adder result for two numerals is greater than nine OR when the binary adder
p
carry-out bit is 1, correction is necessary to obtain valid BCD output. In these cases,
correction can be easily implemented by adding six (01102) to the four-bit binary adder
o
result and forcing the carry out to be 1.
c
When doing BCD addition by hand, sum and carry-out corrections are tolerable, even
t
though this can mean slightly annoying extra steps.
f
When doing BCD addition by way of a digital circuit, the sum and carry-out corrections
ra
are easily incorporated in the circuit design as extra circuit pieces included in an existing
binary full-adder circuit. The extra pieces detect the existence of a carry-out bit being set
(equal to 1) or the result of a four-bit binary number greater than nine. Both conditions
d
are easy to detect. See an example of this in the applications at the end of this text for a
circuit design modification to implement a BCD adder as a digital logic circuit.
Procedure to Perform BCD Addition of Two Numbers, A and B
y
Step Procedure
p
From right to left (least significant numeral to most significant numeral) produce each
BCD initial sum and carry out result and repeat these steps for each BCD numeral
o
position.
c
1 Add the BCD (four-bit) numerals of this position and the carry-in value (0 if this is the first
BCD numeral position) as normal, positive, binary values.
f t
2 If the resulting carry-out is 0 AND the four-bit binary sum is between zero and nine,
inclusive, the BCD numeral position result is valid, so return to step 1 for the next higher
a
BCD numeral position. Otherwise, go to step 3 for correction.
r
3 If the four-bit binary sum from step 2 was greater than nine OR the carry-out of the most
d
significant bit was 1 the result from step 2 was invalid and needs correction as follows:
a. Add six to the four-bit binary sum to get the correct BCD numeral.
b. Set the carry-out value to 1 for the next BCD numeral position.
4 Return to step 1 for the next higher BCD numeral position.

Examples - BCD Addition
y
Convert the decimal numbers 13 and 6 to BCD, add them as BCD, and convert
p
result back to decimal.
1310 = 0001 0011
o
BCD
610 = 0110 BCD
c
carry in
t
0001 0011 BCD 13 10
f
+ 0110 BCD + 6 10
Intermediate Sum 0001 1001 BCD
ra
19 10
Intermediate carry out 0 0 these carry-outs noted but not carried over
Final BCD Sum 0001 1001 BCD 19 10
d
72310 = 0111 0010 0011 BCD
y
47210 = 0100 0111 0010 BCD
p
carry in
0111 0010 0011 BCD 723 10
o
+ 0100 0111 0010 BCD + 472 10
c
Intermediate Sum 1011 1001 0101 BCD
Intermediate carry out 0 0 0 these carry-outs noted but not carried over
t
invalid
f
carry in
1011 1001 0101
a
Correction + 0110 add 6 to invalid BCD position
r
New Intermediate Sum 0001 1001 0101 and
Correction carry out 1 ensure a correction 1 carry-out
d
carry in 1
0001 1001 0101
Correction +
New Intermediate Sum 0001 0001 1001 0101 DONE
Correction carry out
Final BCD Sum 0001 0001 1001 0101 BCD 1195 10

y
p
17210 = 0001 0111 0010
o
BCD
9910 = 1001 1001 BCD
c
carry in
t
0001 0111 0010 BCD 172 10
f
+ 1001 1001 BCD + 99 10
Intermediate Sum 1011 BCD
a
Intermediate carry out 0 (this carry-out is noted but not carried over)
r
invalid
carry in
d
1011
New Intermediate Sum 0001 and (corrected BCD)
Correction carry out 1 ensure a 1 correction carry-out
carry in 1
y
0111
+ 1001 add 6 to invalid BCD position
p
New Intermediate Sum 0001 0001 0001 and
Correction carry out 1 (this carry-out is noted but not carried over)
o
invalid
carry in
c
0001
t
New Intermediate Sum 0111 (corrected BCD)
f
0001 and
Correction carry out 1 ensure a 1 correction carry-out
r a
carry in 1
0001
d
+
New Intermediate Sum 0010 0111 0001 (valid BCD)
Correction carry out 0 (this carry-out is noted but not carried over)
Final BCD Sum 0010 0111 0001 BCD 271 10

p y
c o
f t
dra
p y
c o
a f t
dr
p y
o
The ASCII Code
f t c
ra
An industry-standard, binary, 7-bit input/output (I/O) code called the American Standard
Code for Information Interchange (ASCII) exists to represent most letters and symbols
d
used in day-to-day processing in a computer. Use of seven bits allows for 128 different
character code combinations.
Although a computer usually works with groups of eight bits (eight bits = one byte),
the lower seven bits (bit 6 through bit 0) are used by ASCII codes to define a fixed, core
group of codes for the standard. The byte is often represented as two groups of four bits
y
or as two hexadecimal digits. Bits 7 through 4 make up the upper nibble (four bits = one
nibble). Bits 3 through 0 make up the lower nibble. Bit 7 is normally assumed to be 0
p
but it may not always be so. When working with the ASCII code, it is the value of bits 6
o
through 0 that are important.
c
upper lower
t
b7b6b5b4b3b2b1b0 b7b6b5b4 b3b2b1b0
f
MSB LSB MSB = Most significant bit
a
LSB = Least significant bit
d r
The following table of ASCII codes lists the binary and hexadecimal values for the codes
and it list the characters represented by each code.

y
ASCII Codes
p
upper 0000 0001 0010 0011 0100 0101 0110 0111
o
lower 0 1 2 3 4 5 6 7
c
0000 0 NUL DLE Space 0 @ P ` p
t
0001 1 SOH DC1 ! 1 A Q a q
f
0010 2 STX DC2 " 2 B R b r
r a
0011 3 ETX DC3 # 3 C S c s
d
0100 4 EOT DC4 $ 4 D T d t
0101 5 ENQ NAQ % 5 E U e u
0110 6 ACK SYN & 6 F V f v
0111 7 BEL ETB ' 7 G W g w
p y
1000 8 BS CAN ( 8 H X h x
o
1001 9 HT EM ) 9 J Y i y
c
1010 A LF SUB * : I Z j z
t
1011 B VT ESC + ; K [ k {
a f
1100 C FF FS , < L \ l |
r
1101 D CR GS - = M ] m }
d
1110 E SO RS . > N ^ n ~
1111 F SI US / ? O _ o DEL

The ASCII Code Applied - Example
y
Represent the following sentence characters using ASCII Codes:
p
Four students are in ELT-124.
c o
To help visualize this, the sentence is rewritten here with color coding to separate words and punctuation. It
becomes
t
Four students are in ELT-124.
f
The ASCII codes in hex would be:
r a
F o u r s t u d e n t s a r e i n E L T - 1 2 4 .
d
or 46 6F 75 72 20 73 74 75 64 65 6E 74 73 20 61 72 65 20 69 6E 20 45 4C 54 2D 31 32 34 2E
or 466F75722073747564656E74732061726520696E20454C542D3132342E
or 466F75722073747564656E74732061726520696E20454C542D3132342E
The ASCII codes in binary would be:
y
F o u r (space) s t
p
01000110 01101111 01110101 01110010 00100000 01110011 01110100
u d e n t s (space)
o
01110101 01100100 01100101 01101110 01110100 01110011 00100000
a r e (space) i n (space)
c
01100001 01110010 01100101 00100000 01101001 01101110 00100000
t
E L T - 1 2 4
f
01000101 01001100 01010100 00101101 00110001 00110010 00110100
.
a
00101110
r
or 01000110011011110111010101110010001000000111001101110100
d
01110101011001000110010101101110011101000111001100100000
01100001011100100110010100100000011010010110111000100000
01000101010011000101010000101101001100010011001000110100
00101110
or 010001100110111101110101011100100010000001110011011101000111010101100100
011001010110111001110100011100110010000001100001011100100110010100100000
011010010110111000100000010001010100110001010100001011010011000100110010
0011010000101110

p y
c o
f t
dra
p y
c o
a f t
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p y
o
Boolean Algebra, Operations,
c
and Logic Gates
f t
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Where 1 AND 1 is 1.
d
Digital logic is covered in the remainder of this text in terms of Boolean algebra, Boolean
operations, and logic gates. Boolean algebra expressions employ Boolean variables and
logic/Boolean operators to describe a control decision or result to be implemented based
on the input variables. Input variables and the resulting outputs have values that are of
y
two different states and these can be considered in ways that include the following pairs:
p
0 and 1, off/on, low/high, false/true, etc. The logic gates are symbols that represent logic
operations that can be implemented in electronic circuits and can be drawn as schematics
o
for those circuits. Each gate has one or more input terminals and an output terminal.
c
The ultimate result of any logic gate, operation, or Boolean algebra expression is a
t
Boolean result or a logic state. A Boolean result is NOT an arithmetic result. The ultimate
f
result will always be one state or the other: 0 or 1.
a
Boolean algebra defines digital or logic states (0 or 1) and operations (AND, OR, NOT).
r
Boolean algebra also defines properties, rules, laws, that govern the way logic states or
the variables that represent them are combined and manipulated.
d
Knowing the symbols, operations, and definitions and rules of Boolean algebra is
essential to understanding, implementing, troubleshooting digital logic circuits or
systems.

Boolean Algebra Definitions
y
Boolean Values 0 1
p
Operators + (OR) example: A + B
o
• (AND) example: A•B AB (symbol often omitted)
c
(NOT) example: A
f t
Operator Result 0+0=0 0•0=0
Definitions 0+1=1 0•1=0
a
1+0=1 1•0=0
r
1+1=1 1•1=1
d
0=1 1=0
These are the basic definitions of Boolean algebra. There are two constants, values, or
states (0 , 1).
The AND (•) and OR (+) operators are used to combine two or more values or variables.
y
A variable represents a value that can be either of the two states. Variables are not
p
intended to always to have a constant value.
o
The operator result definitions specify how the operators do their job when two Boolean
values or variables are involved for the OR operation and the AND operation, while the
c
NOT operator involves a single value or variable.
t
All other laws, rules, and properties are derived from these simple definitions.
r a f
Symbol Note: Boolean algebra operators may be represented differently in other texts as
shown in the following table.
d
Symbol Example Used Here Operation Example of Alternate Symbol
A+B OR A∨B
A•B AND A∧B
A NOT Aʹ

Boolean Algebra Laws, Rules, Properties
y
Law of Zero and One A+1=1 A•0=0
Identity A+0=A A•1=A
p
Commutative Law A+B=B+A AB = BA
o
Associative Law A + (B + C) = (A + B) + C A(BC) = (AB)C
c
Distributive Law A(B+C) = AB + AC A+BC = (A + B) (A + C)
Idempotency Law A+A=A A•A=A
f t
Law of Complements A+A=1 A•A=0
Involution A=A 0=0 1=1
a
DeMorganʼs Law A+B=A•B A•B=A+B
r
1st Law of Absorption A + AB = A A • (A + B) = A
d
2nd Law of Absorption A + AB = A + B A(A + B) = AB
These laws, rules, and properties can be proved using the basic Boolean Algebra
Definitions listed on the previous page, by using truth tables (described later), or by other
steps of using any Boolean algebra laws, rules, and properties that have been proved. Pick
y
just about any starting point and the entire list can be derived or proved.
Literal
o p
A binary variable or the complement of a binary variable. A function
with n variables has 2n distinct literals.
c
Dual The “dual” of a Boolean statement is another statement written just like
t
the original except for the simultaneous interchange of the operators
f
“•” and “+” and the values “0” and “1”.
a
Principle of Duality If two expressions can be shown to be equivalent using a series of
r
postulates, then the dual expressions can be proved to be equivalent
just by applying the series of dual postulates. Therefore, for each
Boolean property established, the dual property will also hold without
d
additional proof.

Basic Logic Gates and Operations
y
Operation Example Gate Symbol* Truth**
(Gate) Expression Description Traditional IEEE/IEC Table
o p
AND A•B Result=1 when all inputs are 1.
A B A•B
Result=0 when any input is 0.
c
AB 0 0 0
0 1 0
t
& 1 0 0
f
1 1 1
ra
OR A+B Result=1 when any input is 1.
A B A+B
d
Result=0 when all inputs are 0.
0 0 0
0 1 1
1 0 1
≥1
1 1 1
y
Buffer A Result is same as input.
A A
(often used to reproduce/boost
p
0 0
a signal in order to drive many
1 1
more gates) 1
Inverter A
c
Result is opposite of the input.
o
t
A A
f
0 1
a
1 1 0
d r
The circle or “bubble” at the output of the inverter is often used as a shortcut for
inversion at inputs and outputs of gate symbols and other device symbols.
On an input line, the circle means the input is inverted.
On an output line, the circle means the output is inverted.
* The traditional gate symbols will be used in this text.

** Truth tables are covered in detail in another chapter. See “The Truth Table”.

Other Logic Gates
y
Function Example Gate Symbol Truth
(Gate) Expression Description Traditional IEEE/IEC Table
o p
A B A•B
NAND AB Inverted AND.
0 0 1
AND gate with output inverted.
c
0 1 1
1 0 1
t
& 1 1 0
NOR A+B
r a f
Inverted OR.
OR gate with output inverted.
A B A+B
0
0
0
1
1
0
d
1 0 0
≥1 1 1 0
see
Inverter A Another way to invert is to use
an available NAND or NOR gate inverter
with all inputs tied together as a truth
y
(Implemented
single input. May be convenient table
when an inverter is needed and
p
with NAND or
NOR gates) an additional inverter chip is not
worth circuit space.
o
A B A⊕B
eXclusive A⊕B Two-input gate:
c
Result=1 when one input is 1. 0 0 0
OR
Result=0 if inputs are same. 0 1 1
t
XOR 1 0 1
f
1 1 0
r a
A B A⊕B
eXclusive A⊕B XOR gate with output inverted.
0 0 1
NOR Result is 0 when one input is 1.
d
0 1 0
Result is 1 if inputs the same.
XNOR 1 0 0
1 1 1
These other logic gates are not Boolean operations, but functions (combinations of
operations). Though XOR has its own unique gate, XOR is a function...and it is so useful
that it is basically given its own special ⊕ “operator” even though it is not an operation.

Sum-of-Products (SOP) Form
y
A Boolean Function is expressed in the Sum-of-Products for (SOP) when it is comprised
of ORed together terms of grouped ANDed variables. While it is certainly a Boolean
p
function, it has the appearance of a mathematical arrangement of multiplied terms
o
summed together and this is how it gets its name.
t c
The following examples are in Sum-of-Products form:
f
X = ABC + C + BC + BD
ra
W = AB + AC + ABC
d
Z = ABCD + BCD
H = ABC + ABC + ABC +ABC
Y = A + B + C + D (this is also a one-term POS expression)
y
Y = ABD
o p
c
The following examples are NOT in Sum-of-Products form:
t
X = A (B C + D) + B C + B D
a f
W = (A + B) (A + C) + A B C
r
Z = (A + B + C + D) (B + C + D)
d
Product-of-Sums (POS) Form
y
A Boolean Function is expressed in the Product-of-Sums for (POS) when it is comprised
of ANDed together terms of grouped ORed variables. While it is certainly a Boolean
p
function, it has the appearance of a mathematical arrangement of summed groupings of
o
variables multiplied together and this is how it gets its name.
t c
The following examples are in Product-of-Sums form:
f
X = (A + B + C) (C) (B + C) (B + D)
ra
W = (A + B) (A + C) (A + B + C)
d
Z = (A + B + C + D) (B + C + D)
H = (A + B + C) ( A + B + C) (A + B + C) (A + B + C)
Y = A + B + C + D
y
Y = ABD (this is also a one-term SOP expression)
o p
c
The following examples are NOT in Product-of-Sums form:
t
X = A (B C + D) + B C + B D
a f
W = (A + B) (A + C) + A B C
r
H = ABC + ABC + ABC +ABC
d
A off
on
Switch Circuit Equivalent of AND Gate and OR Gate

B off
y
on
o
Switch Circuit Equivalent of AND Gate
p
V+
f t
A off
on
c
B off
on
ra
Light is turned on when
d
switch A is on AND switch B is on.
Switch Circuit Equivalent of OR Gate
y
V+
p
A off
o
on
c
B off
t
on
a f
Light is turned on when
r
switch A is on OR switch B is on
(or when both are on).
dV+ A off
on
B off
on

A Look at DeMorganʼs Law
y
Using both algebraic and schematic forms, DeMorganʼs Law tell us two things:
p
Algebraic Schematic
c o
A+B = A•B =
A rhyme that might help you remember
f t
DeMorganʼs Law is:
ra
“Split the line, change the sign”
A•B = A+B =
d
By extension, it can be determined that a given input and output arrangement of an AND
gate or an OR gate can be replaced with an equivalent made by replacing the original
AND [OR] gate with an OR [AND] gate and inverting all inputs and outputs from their
original arrangement. Here are a few of the additional gate/input/output equivalents
y
resulting from DeMorganʼs Law.
p
Algebraic Schematic Algebraic Schematic
c o
A+B = A•B = A•B = A+B =
a f t
r
A•B = A+B = A+B = A•B =
d
This feature of DeMorganʼs Law is sometimes called “bubble pushing” because it appears
that any inverting symbol (the “inversion bubble”) at the inputs and outputs are being
pushed around. However, though bubbles and no-bubbles are exchanged, it also involves
gate switching.

A Look at the Principle of Duality
y
The Principle of Duality describes how one true or proved equality can be transformed
to its dual which is a different provable equality. An equality is one Boolean expression
p
shown to be equal to another Boolean expression.
Caution
c o
t
The Principle of Duality DOES NOT mean that the dual of a
f
statement or the duals of expressions are equal to the original
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from which the duals were obtained. It only means that, given a
true equality, the dual of the equality is also true in itself.
d
Other texts make impressive use of the Principle of Duality and duals of expressions in
transformations and procedures. This is beyond the scope of this text. Duality is presented
here for the “interest factor” in addition to being an important part of digital logic as it
appears in Boolean algebra laws that weʼve already seen.
y
Laws like the Commutative Law, Associative Law, Distributive Law, First and Second
Laws of Absorption, etc. each have two forms: one form tends to highlight an OR
p
operation and the other form tends to highlight an AND operation. It should be noted that
o
all forms of each of these laws can be proved using truth tables or they can be proved
using Boolean algebra definitions. What should be observed is that the two forms of each
c
of these laws are duals of each other.
t
For example, note that one form of the Second Law of Absorption states that
f
A + AB = A + B
r a
and the other form of the Second Law of Absorption is the dual form
d
A(A + B) = A B
and that each form is correct and can be proved, though the two forms are not equal.

Simplifying Expressions Using Boolean Algebra
y
Often, a Boolean expression is written in a manner that may not be simple, especially
in early chapters of a textbook on the subject. Using Boolean algebra laws, rules, and
p
properties, one can derive simpler forms of the same expression that may be easier to
o
implement in a circuit form or just for further use on paper in a given situation.
c
The purpose of simplification is to reduce the complexity of logic gates and their
interconnections, often by reducing the number of logic gates as well as the number of
t
types of logic gates.
f
The benefit of reducing gate count to reduce the number of levels of gates that signals
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must traverse to set the output state can be a valuable one. The outputs we assume to be
instantaneous actually take some tiny amount of time to appear, due to what is called
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“propagation delay” inherent to each gate in the circuit. Assume that it takes some time
Tp for a typical gate to respond to its inputs. Tp will be our measure of propagation delay.
For a circuit that has ten levels of gates, in series (inputs to one come from the outputs of
others all the way through the chain of gates) it will take 10Tp time units for the output
to become final. On the other hand, consider a circuit with the same number of gates in
just three levels, say, six gates whose outputs go to three other gates that finally feed one
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final result gate. In this case, it will take 3Tp time units for the output to become final.
p
While signal states propagate from gate to gate through a circuit to produce an output,
intermediate and final results are not stable in the tiny moments that it takes for the final
o
output to become set. Simplification can really help in terms of time and money.
c
This process of simplification involves using Boolean algebra rules that may include
t
expanding expressions or terms in ways that seem to be like “regular” algebra in their
f
appearance. Additional steps include looking for patterns or groupings of variables or
other terms that match some known Boolean algebra properties that will result in simpler
a
terms. Several iterations of this process may be necessary until the expression cannot
r
be reduced any further. At least not any further to be worth the extra effort. Another
d
technique using a K-map (covered later in this text) can also be used to simplify an
expression and it can produce the most simple expression. However, Boolean algebra is
the topic here.
Patterns to look for in an expression can exist as patterns of individual variables or
patterns of groups of variables. When a grouping of variables or terms appears in more
than one place in an expression, that grouping or pattern can be treated as a variable in

itself and it can be used as a variable in one of the Boolean algebra rules or properties...
and modified or eliminated according to those laws, rules, and properties.
y
Be aware that sometimes the order in which terms are “attacked”, that is the terms that
p
are selected first to begin the simplification, can result in more or fewer steps to achieve
a final result. Thatʼs just the way it is. In fact, this is the case with the third and longest
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simplification example that follows. In that example, the “long way” is presented.
c
Now to see simplification in action. The following examples include extensive detail
t
in order to illustrate application of rules, laws, and properties. Be aware that it is the
f
tendency of the author to list ANDed or ORed variables of a term in alphabetical order
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(using proper application of the commutative laws) to facilitate recognition of patterns.
d
y
Examples - Expression Simplification Using Boolean Algebra
p
Simplify the expression for X = (A + B)B + B + BC
o
One way:
c
X = (A + B)B + B + BC given
t
X = AB + BB + B + BC distributive law
f
X = AB + 0 + B + BC law of complements
a
X = AB + B + BC identity
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X = (A + 1)B + BC distributive law (factored out the B)
X = (A + 1)B + BC identity (anything ANDed with 1 is unchanged)
d
X = ( 1 )B + BC law of one
X = B + BC identity
X=B+C second law of absorption DONE

y
Shorter way:
p
X = [(A + B) + 1]B + BC distributive law
o
X = [ 1 ] B + BC law of one
X = B + BC identity
c
f t
ra
Shortest way:
X = B + BC first law of absorption ...(A+B) was absorbed
d
y
Simplify the expression for Z = A B + C D + A C D
p
Z=AB+CD+ACD given
Z = A B (C D) + (A + C + D) DeMorganʼs law two places
o
Z = A B (C D) + (A + C + D) involution in two places
c
Z = A B (C+D) + A + C + D DeMorganʼs law
t
Z=ABC+ABD+A+C+D distributive law
f
Z=ABC+C + A+ABD +D commutative law
Z= C + BD+A +D first law of absorption
a
second law of absorption
r
Z= C+ BD+D +A commutative law
d
Z= C+ B+D +A second law of absorption
Z= A+B+C+D commutative law to make it look nicer
(in alphabetical order, why not?)

Simplify the expression for W = (A + B + C) (A + B + C) (A + B + C)
W = (A + B + C) (A + B + C) (A + B + C) given
y
W = (AA + AB + AC + BA + BB + BC + C A + CB + CC) (A + B + C) distributive law
p
W = ( 0 + AB + AC + BA + B + BC + C A + CB + 0 ) (A + B + C) law of complements,
and idempotency
o
W = (AB + BA + B + BC + CB + AC + C A) (A + B + C) identity (ORed 0s),
c
and commutative law
W = [(A + A + 1 + C + C)B + AC + C A)] (A + B + C) distributive law
f t
W=[ ( 1 )B + AC + C A)] (A + B + C) law of one
W = [B + AC + A C] (A + B + C) identity (ANDed 1),
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and commutative law
W = (BA + ACA + A C A + BB + ACB + A C B + BC + ACC + A C C) distributive law
d
W = (AB + 0 + A C + 0 + ACB + A C B + BC + AC + 0) commutative law,
and idempotency,
and law of complements
W = (AB + A C + A B C + AC + ABC + BC) commutative law,
and identity
W = (AB + AC + AC + BC) first law of absorption (twice)
to be continued ...
p y
Okay, what follows is a leap. It turns out the author knows this expression of four two-variable terms can
be reduced to three two-variable terms. However, a way to achieve this from here is to make the expression
o
temporarily more complicated, which is not entirely intuitive. From there it will be reduced in a few more
steps. This is done here to illustrated that simplification is not solely a process of making expressions
c
smaller and smaller in every single step.
Basic intuition and pattern recognition are necessary to achieve most of the progress in simplification.
t
Sometimes, exceptional intuition (or inspirational moments) may be necessary. Further, awareness or
f
acceptance that making something simpler may require temporarily making it slightly more complicated in
creative ways in order to achieve the simpler result.
r a
W = AB( 1 ) + A C + AC + BC identity (insert an ANDed 1)
W = AB(C+C) + A C + AC + BC law of complements
d
use another form of 1 (C+C)
W = ABC + ABC + A C + AC + BC distributive law
W = ABC + BC + A C + ABC + AC commutative law
W= BC + AC + AC law of absorption (twice)
W = BC + A C + AC DONE (finally)

p y
o
Schematics To/From Logic Equations
t c
Having a Boolean logic equation that relates some output to a combination of input
f
conditions and operations may be useful in itself because it describes a system or need.
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Boolean expressions (the part of the equation that the output or result is equal to) are
useful in processing data when using spreadsheet software where a result is set to
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one value or calculation if the expression is true or another value or calculation if the
expression is false. Boolean expressions are useful in software development because
decisions are made do execute certain chunks of programming coded based on conditions
or states of other variables. Examples: Is the left mouse button down? Is it down in a
particular scroll bar? Is it down in a particular part of a particular scroll bar? Have certain
steps been executed the correct number of times to complete part of a larger process? Is
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there a condition that requires discontinuation of an ongoing, repetition of certain steps?
p
For electronics topics in education and real-world design, Boolean expressions are
used to produced circuits made from integrated circuit components, switches, relays,
o
sensors, lights, etc. Boolean expressions can be built into something real and more
c
than just a few symbols on a piece of paper. To achieve this, the Boolean expression
must be re-written in schematic form. Interconnections between input points, logic gate
t
symbols, and outputs are used to represent the equation. The schematic is equivalent to
f
the equation. The circuit built upon the schematic is equivalent to the equation and is the
a
implementation of the equation.
r
The following examples relate Boolean equations and direct equivalent schematics.
d
To draw a schematic from an equation, discern the inputs variables and their states,
route interconnections between needed logic gates based on variable/state groupings and
intermediate results, and combine them in a final logic gate to get the output.
To obtain an equation from a schematic, write down each intermediate gate output
throughout the schematic until the final output is reached. The result will be legitimate,
though it may not be the most simple form of the expression for the output.

Examples - Logic Schematics To/From Boolean Equations
y
Draw a schematic to use to build a circuit for the equation Y = A B + C D
p
[ or ... Derive an output equation from the following schematic ]
Examination of this circuit reveals four inputs and four operations. The four inputs are variables or signals
o
A, B, C, and D. There are two AND operations, one OR operation, and one INVERT operation. Variable A
c
and variable B are grouped together in one AND operation, C is grouped by itself in an INVERT operation
to obtain C. Variable D and the resulting C are grouped in one AND operation. The results of the two AND
t
operations are grouped in a final OR operation. Here is the circuit:
f
A AB
a
B
r
C Y = AB + CD
C
d
D CD
Draw a schematic to use to build a circuit for the equation W = A B + A B

y
Examination of this circuit reveals two inputs and five operations. The two inputs are variables or signals
A and B. There are two INVERT operations, two AND operations, and one OR operation. Variable A is
p
inverted. Variable B is also inverted. The resulting A and the variable B are grouped together in one AND
o
operation. The variable A and the resulting B are grouped together in one AND operation. The results of the
two AND operations are grouped in one final OR operation. Here is the circuit:
c
A
A AB
t
B
f
A
a
W = AB + AB
r
B AB
B
d
Another implementation of this circuit comes from the recognition that the expression involving variables
A and B is the “raw” way of handling an XOR operation, which can be implemented using a single gate as:
A
W=A⊕B = AB + AB
B

Draw a schematic to use to build a circuit for the equation X = A B + C D + A C D
y
Four inputs and six operations (including couple NANDs as a basic operation, though they could be done
p
as an AND gate with an INVERTER and, similarly, a NOR gate). Four inputs are variables: A, B, C, and D.
Variables A and B combined with a NAND gate. Variables C and D are ANDed. These two gate results are
o
NORed. Variable D is INVERTed, then combined with A and C in a three-input NAND gate. The NOR gate
and the three-input NAND gate results are inputs of an OR gate to produce the result. Here is the circuit:
c
A
t
AB
f
B AB + CD
C
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D CD
A X = AB + CD + ACD
d
C
ACD
D D
Draw a schematic to use to build a circuit for the equation

W = (A+B+C) (A+B+C) (A+B⊕C)
y
o p
A
A A+B+C
c
W = (A+B+C)(A+B+C)(A+B⊕C)
B
f t
C B+C A+B+C
r a
B⊕C B⊕C
d
A+B⊕C
A single eXclusive NOR (XNOR) gate could have been used instead of the two-gate combination of the
XOR followed by the INVERTER.

p y
c o
f t
dra
p y
c o
a f t
dr
p y
o
The Truth Table
f t c
The truth shall set you free.
d ra
A Boolean function can be represented algebraically using variables, operators, and
groupings. Another way of representing a Boolean function is to list the function result
and all combinations of input variables in tabular form. This tabular form is know as a
truth table.
A truth table can be used to:
y
• define a Boolean function
p
• show/prove the equivalence of two boolean expressions
o
• help derive a Boolean algebra description of the function
c
A truth table having n input variables has 2n input variable combinations
(uncomplemented and complemented states of each input variable). A truth table having
t
two input variables has four (22) input value combinations. A truth table having five input
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variables has thirty-two (25) input value combinations.
r a
A truth table is generally constructed with the input variables listed as column headings
on the left side and the output variables listed as column headings on the right side. Any
d
given row of the truth table lists a single combination of input variable states and the
associated output variable states for that combination of inputs. The standard practice of
listing the states of the input variables is to start at the top row and move down, counting
in binary. The right-most input variable is the least-significant bit of the count and the
left-most variable is the most significant bit of the count.
Below are examples of truth tables with various numbers of inputs and outputs.

Truth Table Structure
y
input output input output input output
p
A W A B C Z T3 T2 T1 T0 Alarm
o
0 1 0 0 0 0 0 0 0 0 1
c
1 0 0 0 1 1 0 0 0 1 1
0 1 0 0 0 0 1 0 1
t
0 1 1 1 0 0 1 1 1
f
1 0 0 1 0 1 0 0 1
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input output 1 0 1 1 0 1 0 1 1
A B X Y 1 1 0 0 0 1 1 0 1
d
0 0 0 1 1 1 1 1 0 1 1 1 0
0 1 1 1 1 0 0 0 1
1 0 1 0 1 0 0 1 1
1 1 0 1 1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
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1 1 0 1 0
p
1 1 1 0 0
1 1 1 1 0
o
Input variables and states listed on the left.
c
Output variable(s) and states listed on right.
t
All input state combinations listed
f
by counting in binary from 0 to 2n–1.
Interpretation
d r a
This truth table line indicates the value of the “Alarm” output is 1 when the following
input combination exists:
Alarm = 1 when
T3 = 0 , T2 = 1 , T1 = 1 , T0 = 0 (all at the same time)

Forming SOP and POS Terms From Truth Table
y
Depending on the need, input states of each line or row of a truth table can represent
either a Boolean algebra Sum-of-Products term or a Product-of-Sums term. This is an
p
important use and interpretation shown below in a four-input truth table.
o
An SOP term for a given line is formed by combining all of the inputs and, based on the
c
state of each input on that line, writing the variable as uncomplemented when the state of
that variable is 1 and writing the variable as complemented when the state of the variable
t
is 0. All of the variables are then ANDed together.
f
A POS term for a given line is formed by combining all of the inputs and, based on the
ra
state of each input on that line, writing the variable as uncomplemented when the state of
that variable is 0 and writing the variable as complemented when the state of the variable
d
is 1. All of the variables are then ORed together.
A B C D SOP term POS term
0 0 0 0 ABCD (A+B+C+D)
y
0 0 0 1 ABCD (A+B+C+D)
0 0 1 0 ABCD (A+B+C+D)
p
0 0 1 1 ABCD (A+B+C+D)
o
0 1 0 0 ABCD (A+B+C+D)
c
0 1 0 1 ABCD (A+B+C+D)
0 1 1 0 ABCD (A+B+C+D)
t
0 1 1 1 ABCD (A+B+C+D)
f
1 0 0 0 ABCD (A+B+C+D)
a
1 0 0 1 ABCD (A+B+C+D)
r
1 0 1 0 ABCD (A+B+C+D)
d
1 0 1 1 ABCD (A+B+C+D)
1 1 0 0 ABCD (A+B+C+D)
1 1 0 1 ABCD (A+B+C+D)
1 1 1 0 ABCD (A+B+C+D)
1 1 1 1 ABCD (A+B+C+D)

Making a Truth Table From a Function Written in Sum-of-Products (SOP)
Form
y
To create a truth table from a function written in Sum-of-Products (SOP) form, follow
p
these steps:
Step Procedure
c o
t
1 Generate a truth table listing the input variables and all combinations of states of those
f
variables and include a blank column for the function result (the output variable).
ra
2 Select a product term.
d
3 Put a 1 for the function result (the output variable) of a given line based on the input
variable states for that line whenever
the uncomplemented input variables appearing in the term appear in the table as 1
and
the complemented input variables appearing in the term appear as 0
y
4 Repeat step 3 for each of the other product terms in the function.
p
5 When all product terms corresponding to the 1 outputs of the function have been handled
o
as above, put a 0 all remaining or unfilled output function positions.
c
6 The truth table for the SOP function is complete.
a f t
d r
Example - Making a Truth Table From a Function Written in SOP Form
y
Create a truth table for the function X = AB + AC + BC
p
A B C X
1. Generate base truth table. 0 0 0
o
0 0 1
0 1 0
c
0 1 1
1 0 0
t
1 0 1
f
1 1 0
1 1 1
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2,3,4. Term: AB Term: AC Term: BC
Put a 1 for X when Put a 1 for X when Put a 1 for X when
d
(A=1) AND (B=1) (A=1) AND (C=1) (B=0) AND (C=1)
A B C X A B C X A B C X
0 0 0 0 0 0 0 0 0
0 0 1 0 0 1 0 0 1 1 B=0 C=1
0 1 0 0 1 0 0 1 0
0 1 1 0 1 1 0 1 1
1 0 0 1 0 0 1 0 0
y
1 0 1 1 0 1 1 A=1 C=1 1 0 1 1 B=0 C=1
1 1 0 1 A=1 B=1 1 1 0 1 1 1 0 1
p
1 1 1 1 A=1 B=1 1 1 1 1 A=1 C=1 1 1 1 1
o
A B C X
5. When all product terms of the function 0 0 0 0 zero in blank
c
have been processed as above, put a 0 0 0 1 1
in each of the remaining, unfilled output 0 1 0 0 zero in blank
t
function positions. 0 1 1 0 zero in blank
f
1 0 0 0 zero in blank
1 0 1 1
a
1 1 0 1
r
1 1 1 1
d
A B C X
6. The truth table for the SOP function is complete. 0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

Making a Truth Table From a Function Written in Product-of-Sums (POS)
Form
y
To create a truth table from a function written in Product-of-Sums (POS) form, follow
p
these steps:
Step Procedure
c o
t
1 Generate a truth table listing the input variables and all combinations of states of those
f
variables and include a blank column for the function result (the output variable).
ra
2 Select a sum term.
d
3 Put a 0 for the function result (the output variable) of a given line based on the input
variable states for that line whenever
the uncomplemented input variables appearing in the term appear in the table as 0
and
the complemented input variables appearing in the term appear as 1
y
4 Repeat step 3 for each of the other sum terms in the function.
p
5 When all sum terms corresponding to the 0 outputs of the function have been handled as
o
above, put a 1 all remaining or unfilled output function positions.
c
6 The truth table for the POS function is complete.
a f t
d r
Example - Making a Truth Table From a Function Written in POS Form
y
Create a truth table for the function X = (A+B) (A+B+C) (A+B+C)
p
A B C X
1. Generate base truth table. 0 0 0
o
0 0 1
0 1 0
c
0 1 1
1 0 0
t
1 0 1
f
1 1 0
1 1 1
ra
2,3,4. Term: (A+B) Term: (A+B+C) Term: (A+B+C)
Put a 0 for X when Put a 1 for X when Put a 1 for X when
d
(A=0) AND (B=0) (A=1) AND (B=0) AND (C=1) A=1) AND (B=1) AND (C=1)
A B C X A B C X A B C X
0 0 0 0 A=0 B=0 0 0 0 0 0 0 0 0
0 0 1 0 A=0 B=0 0 0 1 0 0 0 1 0
0 1 0 0 1 0 0 1 0
0 1 1 0 1 1 0 1 1
1 0 0 1 0 0 1 0 0
y
1 0 1 1 0 1 0 A=1 B=0 C=1 1 0 1 0
1 1 0 1 1 0 1 1 0
p
1 1 1 1 1 1 1 1 1 0 A=1 B=1 C=1
o
A B C X
5. When all sum terms of the function 0 0 0 0
c
have been processed as above, put a 1 0 0 1 0
in each of the remaining, unfilled output 0 1 0 1 one in blank
t
function positions. 0 1 1 1 one in blank
f
1 0 0 1 one in blank
1 0 1 0
a
1 1 0 1 one in blank
r
1 1 1 0
d
A B C X
6. The truth table for the POS function is complete. 0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

Making a Sum-of-Products (SOP) Form Expression From a Truth Table
y
To create a Sum-of-Products (SOP) form equation for a function from a truth table,
follow these steps:
Step Procedure
o p
c
1 Select a line from the truth table where the output/result is 1.
f t
2 Form a product term (literals ANDed together) using EACH input variable as follows:
ra
use the uncomplemented form of the variable when its truth table value in that line is 1
and
use the complemented form of the variable when its truth table value in that line is 0.
d
3 OR the product term just formed with the product terms formed so far.
4 Repeat steps 2 and 3 for each of the other lines of the truth table where the output is 1.
The raw, unsimplified SOP function is complete when all product terms corresponding to
y
5
the 1 outputs of the function have been created.
o p
f t c
d r a
Example - SOP Expression From Truth Table
y
Create a Sum-of-Products (SOP) expression for the function described by the truth table
below.
p
1 Select first line from truth table where output is 1.
o
A B C X
0 0 0 0
c
0 0 1 1
0 1 0 0 2 Form a product term based on values of input variables.
t
0 1 1 0
A=0 B=0 C=1
1 0 0 0
f
1 0 1 1
this product term is A B C
1 1 0 1
ra
1 1 1 1 3 Partial result so far is: X* = A B C
d
2 Form a product term based on values of input variables.
A=1 B=0 C=1
3 Partial result so far is: X* = A B C + A B C
y
A=1 B=1 C=0
p
o
3 Partial result so far is: X* = A B C + A B C + A B C
t c
f
A=1 B=1 C=1
r a
3 Partial result so far is: X* = A B C + A B C + A B C + A B C
d
5 The raw, unsimplified SOP function is complete now that all product terms
corresponding to the 1 outputs of the function have been created. The final
SOP representation of the output, X, is
X= ABC + ABC + ABC + ABC

Making a Product-ofSums (POS) Form Expression From a Truth Table
y
To create a Product-of-Sums (POS) form equation for a function from a truth table,
follow these steps:
Step Procedure
o p
c
1 Select a line from the truth table where the output/result is 0.
f t
2 Form a sum term (literals ORed together) using EACH input variable as follows:
ra
use the uncomplemented form of the variable when its truth table value in that line is 0.
and
use the complemented form of the variable when its truth table value in that line is 1.
d
3 AND the sum term just formed with the sum terms formed so far.
4 Repeat steps 2 and 3 for each of the other lines of the truth table where the output is 0.
The raw, unsimplified POS function is complete when all sum terms corresponding to the
y
5
0 outputs of the function have been created.
o p
f t c
d r a
Example - POS Expression From Truth Table
y
Create a Product-of-Sums (POS) expression for the function described by the truth table
below.
p
1 Select first line from truth table where output is 0.
o
A B C X
0 0 0 0
c
0 0 1 1
0 1 0 0 2 Form a sum term based on values of input variables.
t
0 1 1 0
A=0 B=0 C=0
1 0 0 0
f
1 0 1 1
this sum term is (A+B+C)
1 1 0 1
ra
1 1 1 1 3 Partial result so far is: X* = (A+B+C)
d
2 Form a sum term based on values of input variables.
A=0 B=1 C=0
3 Partial result so far is: X* = (A+B+C) • (A+B+C)
y
A=0 B=1 C=1
p
o
3 Partial result so far is: X* = (A+B+C) • (A+B+C) • (A+B+C)
t c
f
A=1 B=0 C=0
r a
3 Partial result so far is: X* = (A+B+C) • (A+B+C) • (A+B+C) • (A+B+C)
d
5 The raw, unsimplified POS function is complete now that all sum terms
corresponding to the 0 outputs of the function have been created. The final
POS representation of the output, X, is
X = (A+B+C) • (A+B+C) • (A+B+C) • (A+B+C)

p y
c o
f t
dra
p y
c o
a f t
dr
p y
o
The Karnaugh Map or K-Map
f t c
The truth [table] may set you free but the K-map will do it quicker.
d ra
Yet another way of representing a Boolean function is to list the function result in a
different table form called a Karnaugh Map, or K-map. How is the word pronounced?
Karnaugh is pronounced “KAR-no” or “kar-NO” or “KAR-naw” or “kar-NAW”.
Fortunately, is quicker, safer, and generally understood to just call it a “K-map”
(pronounced “KAY-map”).
y
A K-map can be used to:
p
• define a Boolean function
• show/prove the equivalence of two boolean expressions
o
• derive the simplest Boolean algebra descriptions of the function
c
While the first two uses of a K-map are valid, they have most likely been accomplished
t
already (and more easily) by way of a truth table. The last use, to derive the simplest
f
Boolean algebra descriptions of a function, is the most important and valuable. And it is
a
quick.
r
A K-map is drawn in the shape of rectangle. For a Boolean function having n inputs, this
d
rectangle is divided into 2n squares or cells. The edges of the overall rectangle are labeled
to indicate the state or value of a given input variable. This labelling is done in a special
way that causes the input combination represented by a cell in the K-map to differ from
an adjacent cell (one above, below, right or left...NOT diagonal) by only one literal. That
is, given the input combination of a cell, an adjacent cell differs by only one variable that
is either complemented or uncomplemented. This is an important feature of the K-map.

Each cell in a K-map has two features. A cell holds a Boolean value (1 or 0). A cell also
represents a fundamental product term (variables ANDed together) made up of all of the
y
variable states that intersect at that row and column.
p
K-maps can be drawn in different formats. Here are examples of three formats for 2-, 3-,
and 4-variable K-maps. K-maps for five or more variables are possible and they quickly
o
become large and very cumbersome.
K-Map Formats
f t c
a
A A A A A A A A
r
B P0 P2 P0 P4 C B P0 P1 P5 P4 P0 P4 P12 P8 D
d
B C
B P1 P3 P1 P5 B P2 P3 P7 P6 P1 P5 P13 P9
C D
P3 P7 C C C P3 P7 P14 P10
B C
P2 P6 C P2 P6 P15 P11 D
B B B
y
A A AB AB
0 1 0 1 00 01 11 10 00 01 11 10
B BC C CD
p
0 P0 P2 00 P0 P4 0 P0 P1 P5 P4 00 P0 P4 P12 P8
P1 P3 P1 P5 P2 P3 P7 P6 P1 P5 P13 P9
o
1 01 1 01
11 P3 P7 11 P3 P7 P14 P10
c
10 P2 P6 10 P2 P6 P15 P11
f t
A A A A AB AB AB AB AB AB AB AB
a
B P0 P2 BC P0 P4 C P0 P1 P5 P4 CD P0 P4 P12 P8
r
B P1 P3 BC P1 P5 C P2 P3 P7 P6 CD P1 P5 P13 P9
d
BC P3 P7 CD P3 P7 P14 P10
BC P2 P6 CD P2 P6 P15 P11

Each “P” represents a fundamental product term (variables ANDed together) made up
of all of the variable states that intersect at that row and column. For example, in the
y
4-variable truth table, the product term associated with cell containing P9 is A B C D .
p
In an actual K-map, there will be ones and zeros in the cells...and perhaps some “donʼt
care” values. In the case of the P9 cell, its value (1 or 0) will be the result or the function
o
or output of the circuit when the input variables have values of A=1 , B=0 , C=0 , D=1
c
all at the same time, corresponding to the product term (A B C D).
SOP Terms in a K-Map
f t
ra
A A
The state of each variable ABCD ABCD ABCD ABCD D
C
listed in the SOP term of
d
ABCD ABCD ABCD ABCD
each cell is based on the D
intersection of the variable ABCD ABCD ABCD ABCD
states for that row and C
column. ABCD ABCD ABCD ABCD D
B B B
y
AB
00 01 11 10
p
CD
00 ABCD ABCD ABCD ABCD
o
ABCD ABCD ABCD ABCD
c
01
t
f
r a
AB AB AB AB
d
CD ABCD ABCD ABCD ABCD

Making a Sum-of-Products (SOP) Form Expression from a K-Map
y
A K-map can be used to quickly derive the simplest, most reduced Sum-of-Products
(SOP) form expression for a function if a truth table can be first obtained. A simplified
p
SOP expression is obtained by the steps outlined below.
o
Crucial to the use of a K-map in deriving a SOP expression is the way to select groups of
c
adjacent cells that all contain a value of 1 (or a “donʼt care”). In a K-map of n variables,
adjacent cells can be selected in groups of 2i , where 0 ≤ i ≤ n. That is, they are selected
t
in groups of 1, 2, 4, 8, 16, etc. Adjacent cells are cells that appear in specific forms of a
f
rectangle or line as shown in examples on the next page.
ra
Step Procedure for SOP
d
1 Draw a K-map for the number of variables in the expression or truth table.
2 Load the K-map cells with 1 and 0 result values in the appropriate cells that correspond
to the input variable state combinations of the truth table.
3 Circle the largest groupings of 2i adjacent cells that contain values of 1. Be sure to
observe the DOs, DONʼTs, and SUGGESTIONS listed on the next pages covering
y
grouping rules.
p
4 Repeat step 3 until each cell containing a 1 is in one group or another. No 1s can be left
o
ungrouped, even if the group size contains just one cell.
c
5 Create and record the SOP term based on each circled group. The SOP term is obtained
by noting which variables/states (literals) are entirely common throughout the given
t
grouping and ANDing ONLY THOSE COMMON LITERALS.
f
6 Once all groupings have been utilized to create SOP terms, these terms are all ORed
a
together to make the final, simplified SOP expression for the function defined by the
r
K-map (or truth table the K-map is based on).
d
The final SOP expression can be the most simplified form possible for the expression.
This makes using the K-map very helpful in obtaining simplified Boolean expressions.

Making a Product-of-Sums (POS) Form Expression from a K-Map
y
A K-map can also be used to quickly derive the simplest, most reduced Product-of-Sums
(POS) form expression for a function if a truth table can be first obtained. A simplified
p
POS expression is obtained by the steps outlined below.
o
Crucial to the use of a K-map for deriving a POS expression is the way to select groups
c
of adjacent cells that all contain a value of 0 (or a “donʼt care”). In a K-map of n
variables, adjacent cells can be selected in groups of 2i, where 0 ≤ i ≤ n. That is, they are
t
selected in groups of 1, 2, 4, 8, 16, etc. Adjacent cells are cells that appear in specific
f
forms of a rectangle or line as shown in examples on the next page.
ra
Step Procedure for POS
d
1 Draw a K-map for the number of variables in the expression or truth table.
2 Load the K-map cells with 1 and 0 result values in the appropriate cells that correspond
to the input variable state combinations of the truth table.
3 Circle the largest groupings of 2i adjacent cells that contain values of 0. Be sure to
observe the DOs, DONʼTs, and SUGGESTIONS listed on the next pages covering
y
grouping rules.
p
4 Repeat step 3 until each cell containing a 0 is in one group or another. No 0s can be left
o
ungrouped, even if the group size contains just one cell.
c
5 Create and record the POS term based on each circled group. The POS term is obtained
by noting which variables/states (literals) are entirely common throughout the given
t
grouping and ORing THE COMPLEMENTS OF ONLY THOSE COMMON LITERALS.
f
6 Once all groupings have been utilized to create POS terms, these terms are all ANDed
a
together to make the final, simplified POS expression for the function defined by the
r
K-map (or truth table the K-map is based on).
d
The final POS expression can be the most simplified form possible for the expression.
This makes using the K-map very helpful in obtaining simplified Boolean expressions.

K-Map Cell Grouping Methods for Sum-Of-Product (SOP) Terms
y
K-map cells containing values of 1 can be grouped to produce Sum-Of-Product (SOP)
terms to define the Boolean function that results in that K-map or truth table from
p
which the K-map was made. Cells are grouped in rectangular, square, or linear patterns.
o
The number of cells in each group is a power of two (1, 2, 4, 8, 16, etc.) and all are
“adjacent.” Adjacent cells are cells that are next to each other left or right or above or
c
below. NO DIAGONAL groupings are allowed.
t
Valid grouping opportunities often occur by way of wrapping around from one side of
f
the K-map to another, as if the K-map were rolled into a tube so one edge lines up with
ra
the opposite edge, top-to-bottom, or left-to-right. Even all four corners can be a single
group. Each example shows a circled grouping. The variables and states (complemented
or uncomplemented), known as the literals, common everywhere in the circled grouping
d
are listed for reference. The common literals are found by determining which literals are
consistent in a row or column throughout the grouping. Each grouping defines a SOP
term. Each K-map grouping example below also lists the SOP term of that grouping, with
the intersecting literal rows and columns highlighted. For simplicity, a 4-variable K-map
is used.
y
K-map Cell Grouping DOs
p
• Select adjacent cells only in groups sized as a power of two (1, 2, 4, 8, 16 cells, etc.).
o
• Select adjacent cells in square/rectangular shapes.
c
K-map Cell Grouping DONʼTs
t
• NEVER select cells in groups of 3, 5, 6, 7, or anything other than a power of two.
f
• NEVER select cells along a diagonal.
a
• NEVER select cells in a non-linear or non-rectangular shape.
r
K-map Cell Grouping SUGGESTIONS
d
• Select the largest groupings possible, even if one group overlaps another.
• Avoid overlapped groupings where all cells are already included in other groupings.
Overlapping redundancy is acceptable and is normally beneficial. In fact, the larger
the size of the groupings, even with overlaps, the simpler the final expression that

K-Map Cell Grouping Patterns
y
A A A A A A A A
1 0 0 0 D 1 0 0 0 D 1 0 0 0 D 1 0 0 0 D
p
C C C C
0 1 0 0 D
0 0 0 1 D
0 1 1 1 D
0 0 0 1 D
1 0 0 1 1 1 1 1 1 0 0 1 0 1 1 1
o
C C C C
1 0 0 0 D 1 0 0 0 D 1 0 0 0 D 1 0 0 0 D
c
B B B B B B B B B B B B
2-cell vertical
t
1-cell group 2-cell vertical 2-cell horizontal wrap-around
f
ABCD ABD BCD ABD
r a
A A A A A A A A
C
0 0 1 1 D
C
1 0 0 0 D
C
1 0 0 0 D
C
0 0 1 0 D
d
1 0 0 0 D
0 0 0 1 D
1 0 0 1 D
1 0 0 1 D
C
1 0 0 1 C
1 1 1 1 C
1 1 1 1 C
1 1 0 1
0 1 1 0 D 1 0 0 0 D 1 0 0 0 D 1 0 0 0 D
2-cell horizontal 4-cell square

wrap-around 4-cell horizontal 4-cell vertical horizontal wrap-around
BCD CD AB BD
y
A A A A A A A A
p
C
0 0 1 1 D
C
1 0 0 1 D
C
1 1 0 1 D
C
1 1 1 0 D
1 0 0 0 0 1 0 0 1 1 1 0 0 1 1 1
o
D D D D
C
1 0 0 1 C
1 1 0 1 C
0 1 0 1 C
0 1 1 1
c
0 1 1 1 D 1 0 0 1 D 1 0 0 0 D 1 1 1 0 D
t
4-cell square
f
vertical wrap-around 4-cell corners 4-cell square 8-cell vertical
AD BD AC B
r a
A A A A A A A A
d
C
1 1 1 1 D
C
1 1 1 1 D
C
1 0 1 1 D
C
1 1 1 1 D
1 1 1 1 D
1 0 0 0 D
1 0 1 1 D
1 1 1 1 D
C
1 0 0 0 C
0 1 0 1 C
1 1 0 1 C
1 1 1 1
0 1 0 1 D 1 1 1 1 D 1 0 0 1 D 1 1 1 1 D
8-cell horizontal 8-cell vertical

8-cell horizontal wrap-around wrap-around all cells
C D B 1

Example - Using K-map to Obtain Simplified SOP Expression
y
Use a K-map to obtain a simplified SOP expression for a function based on the truth
p
table shown at right.
A B C X
o
0 0 0 0
0 0 1 1
c
0 1 0 0
t
0 1 1 0
f
1 0 0 0
1 0 1 1
1. Draw a K-map for the number of variables
ra
A A 1 1 0 1
in the expression or truth table.
0 0 C 1 1 1 1
B
1 1
d
2. Load the K-map cells C
0 1
with 1 and 0 result values in the B
appropriate cells that correspond
0 1 C
to the input variable state combinations
of the truth table.
A A
y
0 0 C
B
p
3. Circle the largest groupings
1 1
of 2k adjacent cells that contain values of 1. C
o
0 1
B
0 1 C
c
4. Repeat step 3 until [all cells with 1s are used up].
5.
a f t
Create and record the SOP term based on each group. The SOP Terms are: AB BC
6.
d r
Once all groupings have been utilized to create SOP terms, these terms are all ORed together to
make the final, simplified SOP expression for the function defined by the K-map (or truth table the
K-map is based on).
Therefore, the simplest SOP equation for X is: X=BC+AB

y
table shown below.
p
A B C D W
o
0 0 0 0 1
0 0 0 1 1
c
0 0 1 0 0
0 0 1 1 1
t
0 1 0 0 1
f
0 1 0 1 1
a
0 1 1 0 0
0 1 1 1 0 A A
r
1 0 0 0 1 1 0 0 1 D
d
1 0 0 1 1 B
1 0 1 0 0 1 1 1 1
D
1 0 1 1 1 1 0 0 1
1 1 0 0 1 B
1 1 0 1 1 1 0 1 1 D
1 1 1 0 1 C C C
1 1 1 1 0
p y
Note the second row of 1s in the K-map and that the
entire row of four cells is circled to produce a SOP term
o
of BD. Given the large single grouping of the left and
right edge of the K-map (eight cells, four on the left edge A A
c
and four on the right), one might choose to just circle 1 0 0 1 D
t
the two middle cells in that second row, thinking overlap B
1 1 1 1
f
redundancy is not helpful. However, circling just the two
middle cells of the second row would produce an SOP D
1 0 0 1
a
term of BCD. Choosing to circle the entire row of four, B
r
with the overlap, produces a simpler SOP term of BD 1 0 1 1 D
which contains one less literal than if just two cells in the C C C
d
middle had been circled.
The SOP Terms are: BD C ABD
Therefore, the simplest SOP equation for W is: W= C + BD + ABD

Example - Using K-map to Obtain Simplified POS Expression
y
p
table shown at right.
o
A B C D R
0 0 0 0 1
c
0 0 0 1 1
0 0 1 0 0
t
0 0 1 1 0
f
0 1 0 0 0
ra
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
d
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
A A 1 1 1 0 0
y
1 0 0 1 D 1 1 1 1 0
B
1 0 0 0
p
D
1 0 0 0 A A
o
B
0 0 0 1 D 1 0 0 1 D
B
c
C C C 1 0 0 0
D
t
1 0 0 0
B
f
0 0 0 1 D
a
C C C
d r
The common rows and columns
for the circled groups are: ABD C AD
Therefore, the POS terms for the circled groups are: A+B+D C A+D
Therefore, the simplest POS equation for X is: R = (A+B+D) • C • (A+D)

p y
o
Digital Logic Design Applications
f t c
This chapter presents a few digital logic circuit applications. The needs or expected
ra
outputs are described and related to input conditions. Logic equations are derived and
schematics are drawn. In some cases, a resulting circuit building block is “packaged” to
d
become its own device with a block diagram symbol and further used in the example to
create a larger device or component.
p y
c o
a f t
d r
Design Example - Enable Circuits
y
An “enable” circuit is a part of a digital logic circuit that allows (“enables”) a digital signal to be passed
through to subsequent circuitry. Functions or features are enabled or disabled. This can be done by use of
p
an AND gate or even an OR gate.
o
The enable control is used to (1) allow the incoming signal to pass through when enabled or (2) force the
output to be at a fixed state when disabled. An enable feature is like a valve. The valve can either be closed
c
(system disabled) or open (enabled).
f t
AND Gate Enable
d ra
Logic Gates
Processing
Circuit
“Result”
Output = 0 always when disabled.
y
Enable Control
1 = enable Output = “Result” when enabled
0 = disable
OR Gate Enable
o p
f t c
a
Logic Gates
r
Processing “Result”
d
Circuit
Enable Control Output = 1 always when disabled.

1 = disable Output = “Result” when enabled
0 = enable

Design Example - Bank Alarm Application of AND Gate Enable
y
Picture a situation at a bank where a sensor is connected to a vault door and two motion sensors are
positioned in the bank lobby. The door sensor and the motion sensors normally have a low(0) output when
p
the door is closed and when there is no motion, respectively. When the vault door is open, the door sensor
output state switches to high(1). When a motion sensor detects activity within its field of view, its output
o
state switches to high(1). Lights need to be illuminated when the vault door is open or when motion is
detected in the lobby. After banking hours, no one should be in the bank. If the sensors detect that there is
c
motion or that the vault door open, an appropriate alarm needs to be sent to a security monitoring service or
t
to the police department. During business hours, open vault door and lobby motion are normal and should
f
be noted. However, during business hours, no alarms need to be sounded.
ra
The following circuit activates lights on a security monitoring panel when there is motion in the lobby or
when the vault door is open any time, day or night. This circuit also activates special alarms or calls police
when these conditions occur after banking hours, as enabled by the “Arm Security System” switch.
d
Light_Motion_1
Motion_1
Sensor
Light_Motion_2
y
Intruder Alarm
Notify Security
p
Motion_2
Sensor
o
Light_VaultDoor
c
VaultDoor Vault Open!
t
Sensor
Notify Security
f
and POLICE
(1) Activate Unoccupied Security
“Arm Security System”
d
Switch
r a (0) Normal Hours Monitoring
One consideration or implementation might be to have sensors that have a high(1) output in the normal or
safe or non-alarm state and low(0) output in the active or alarm state. This way, if there is a power failure
or disconnection at the sensor end, and the monitoring system still has power, then the failure or disconnect
would show up as an alarm condition to get someoneʼs attention, too. The circuit would need to be changed
to handle “low” inputs as the alarm conditions to still accomplish the same security purpose.

Design Example - XOR as Controlled Inverter / Complement Circuit
y
Use an XOR gate with one input as a control to determine whether the output with be the same as the other
input or the complement of the other input. Here are the circuit and the truth table:
o
Controlled Inverter/Complement Circuit
p
c
Input
t
Output
f
Control
d r
Control
0
0
1
1
0
1
0
1
a
Input Output
0
1
1
0
Note
Control = 0 , Output = Input
Gate acts as Buffer
Control = 1 , Output = Input
Gate acts as Inverter
p y
o
Design Example - XNORs Used as Bit Pattern Comparator
c
A comparator can be designed to compare one pattern (an ordered grouping) of binary values with another
t
same-length pattern of binary values. Both patterns are tested/compared and a resulting binary value is the
f
indication of whether the patterns are the same.
a
This can be done with XNOR gates or XOR and INVERTER gates. The output of the XNOR gate is true
r
when both inputs are the same. This can be done using one XNOR gate per input bit position (one bit value
d
from a given position of one bit pattern and the bit value from the same position of the other bit pattern)
and an AND gate to combine all results.
Here is a comparator circuit schematic that check two patterns, A and B, of eight bits each. The XNOR
outputs are each the result of a bit-pair comparison. All XNOR outputs are combined using an AND gate.
A high(1) output means the bit patterns, A and B, are the same and a low(0) output means the patterns are
different.

A = A7A6A5A4A3A2A1A0 B = B7B6B5B4B3B2B1B0
y
A7 A6 A5 A4 A3 A2 A1 A0
p
B7 B6 B5 B4 B3 B2 B1 B0
c o
f t
d ra Comparator Output
= 1 only if
bit pattern A
is the same as
bit pattern B
y
Comparator Output is 1 only when (A7=B7) AND (A6=B6) AND (A5=B5) AND (A4=B4) AND (A3=B3) AND
p
(A2=B2) AND (A1=B1) AND (A0=B0). That is, Comparator Output is 1 only when bit pattern A is the same
as bit pattern B.
c o
The state of the comparator result could be chosen and designed to be 0 if that would work better for the
circuit at hand. In this case, the logic was kept positive or true or high. To achieve a low/0 output if the bit
t
patterns were the same, a NAND gate would be used, or an INVERTER could be attached to the output of
f
the AND gate in the circuit shown.
a
Interesting
r
An alternative to this circuit is one that uses XOR gates all feeding a NOR gate. This is due to an
d
application of DeMorganʼs Law. Note that the circuit above is essentially XOR gates with all inputs to the
AND gate inverted. This is the case if the inverted output “bubbles” of the XNOR gates were moved to
the inputs of the AND gate. From DeMorganʼs Law, an equivalent to an AND gate with all inputs inverted
and a non-inverted output is an OR gate with non-inverted inputs and with its output inverted. Therefore,
an equivalent comparator can be made by replacing the XNOR gates and the AND gate, respectively, with
XOR gates and a NOR gate.

Design Example - Full Adder Circuits
y
Refer to the discussion on Adding Numbers in the Arithmetic and Negative Numbers chapter. The
following design is based on adding binary numbers. When adding two one-bit binary values with a
p
carry-in value included, there are eight combinations of the input values. For the actual addition, there are
just four combinations of actual numbers being added:
o
0+0+0 = 00 Carry out = 0 Sum bit = 0
c
0+0+1 = 01 Carry out = 0 Sum bit = 1
t
0+1+1 = 10 Carry out = 1 Sum bit = 0
f
1+1+1 = 11 Carry out = 1 Sum bit = 1
r a
Cin A B Cout S Cin Cin Cin Cin
0 0 0 0 0
d
0 0 B 0 1 B
0 0 1 0 1 A A
0 1 0 0 1 0 1 1 0
0 1 1 1 0 B B
1 0 0 0 1 1 1 0 1
A A
1 0 1 1 0 0 1 B 1 0 B
1 1 0 1 0
1 1 1 1 1
y
K-map for Cout K-map for S
Truth Table for Carry Out and Sum Results
p
of Full Adder Circuits
c o
Boolean equation for Cout using K-map: Boolean equation for S using K-map:
t
Cout = A B + A Cin + B Cin S = A B Cin + A B Cin + A B Cin + A B Cin
f
Schematic for Cout : S = A ( B Cin + B Cin ) + A ( B Cin + B Cin )
r a
A S = A ⊕ ( B ⊕ Cin )
d
S= (A⊕B)⊕C
B
Cout Schematic for S :
A
Cin
B
S
Cin

The carry-out (Cout) and sum (S) circuits just obtained can be combined to form a simple building-block
component called a “full adder.” (Note: If the carry-in input were not included it would be given the lowly
y
name of “half adder.”)
p
Full Adder Schematic Packaged as Full Adder
Building Block
c o
A
t
B A B
Cout
f
Full Adder
Cin
Cout Cin
ra
A
B
Cout
Cin
d
S
Combine Full Adders to Make a Four-Bit Full Adder
A B A B A B A B
y
Full Full Full Full
p
Cout Adder Cin Cout Adder Cin Cout Adder Cin Cout Adder Cin
o
S S S S
t c
Re-Packaged as a Four-Bit Full Adder Building Block
f
a
A3 A2 A1 A0 B3 B2 B1 B0
r
4-Bit Full Adder
d
Cout Cin
S3 S2 S1 S0

Design Example - Half Adder Circuit
y
Similar to a full adder is the half adder. The only difference is that the half adder does not include a carry-in
bit. Circuit development is more brief here since detail was given in the full adder circuit example. When
p
adding two one-bit binary values, there are four combinations of the input values and three combinations of
actual numbers being added:
c o
A B Cout S
0 0 0 0
t
0+0=00 Carry out = 0 Sum bit = 0 0 1 0 1
f
1 0 0 1
0+1=01 Carry out = 0 Sum bit = 1
1 1 1 0
ra
1+1=10 Carry out = 1 Sum bit = 0
Truth Table for Carry Out and Sum Results
of Half Adder Circuits
d
A glance at the truth table will show easily recognizable patterns of an AND operation to produce Cout and
the XOR function to produce S.
Cout = A B S= A⊕B
Half Adder Schematic
p y
Packaged as Half Adder
o
Building Block
f t
Cout
c A
Half Adder
B
a
Cout A
r
Cout
S
B
d
B S

y
Combine Three Full Adders and One Half Adder
to Make a Four-Bit Full Adder
o p
c
A B A B A B A B
t
Full Full Full Half
f
Cout Adder Cin Cout Adder Cin Cout Adder Cin Cout
Adder
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S S S S
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Re-Packaged as a Four-Bit Full Adder Building Block
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A3 A2 A1 A0 B3 B2 B1 B0
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Cout 4-Bit Half Adder
f t
S3 S2 S1 S0
d r a
Design Example - Twoʼs-Complement Adder/Subtracter Circuit
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A circuit can be built to perform twoʼs-complement arithmetic for either addition or subtraction and is
based on a full adder. The operation to be performed (addition or subtraction) is controlled by a digital
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input. In this case the control is in the form of a switch. This is another two-state situation: not just off/on or
0/1, but addition/subtraction.
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The addition of twoʼs-complement numbers, A and B, is simple addition of the binary numbers with the
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result having the same number of bits as there were in the two addends. No change is made to either A or
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B. Therefore, to use an full adder as a device to add B to A, only two things need to be added together: the
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original of the number A, the original of the number B.
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Subtraction of a twoʼs-complement number (B) from another twoʼs-complement number (A) involves
adding the twoʼs-complement of B to A. The negative of B is created and added to A. To form the
twoʼs-complement of a number, we take the oneʼs-complement of the number and add one to it. Therefore,
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when using a full adder as the device to subtract B from , three things need to be added together: the
original of the number A, the oneʼs-complement of the number B, and an extra one.
For circuit or design simplicity, it would be helpful to keep the number of “things” needed for the addition
and the subtraction equal. The last two paragraphs show that addition needs two inputs and subtraction
needs three inputs. A slight change to the addition can cause addition to need three inputs as well. A third
input can be a zero. Adding zero to a sum does not change the sum. It helps because it is a third “thing” for
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the addition, making implementation of both operations similar. Here is a summary of what is needed now:
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Using Full Adder to Handle Both Addition and Subtraction
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Addition Operation Inputs Subtraction Operation Inputs
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1. Original number A 1. Original number A
2. Original number B 2. Twoʼs-complement of number B
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3. zero 3. one
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Hereʼs the idea of the circuit:
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1 Leave number A alone. It is input “as-is” to the full adder.
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2 For addition, input the number B “as-is” to the full adder.
For subtraction, input the oneʼs-complement of the number B to the full adder (but we need the
twoʼs-complement, meaning we still need to add one...donʼt worry, that is taken care of next)
3 For addition, add zero by forcing the carry-in input to be 0.

For subtraction, add one by forcing the carry-in input to be 1.
(Okay, This is where the extra “one” comes from for the twoʼs-complement. Sweeeeet!)

Use a control input to choose addition or subtraction as follows: control is 0 for addition and control is 1 for
subtraction. This will generate the needed 0 or 1 for those operations as the carry-in input of the full adder.
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Use that same addition/subtraction control input to control whether the number B is used “as-is” for
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addition or inverted to obtain the oneʼs-complement for subtraction. This will require something that can
be controlled to be either a buffer (pass-through) when the control input is 0 or an inverter when the control
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input is 1. This can be done very nicely with an XOR gate as a controlled inverter which is covered earlier
in this chapter.
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When one input to the XOR gate is a 0, the output will be the same as the other input. When one input to
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the XOR gate is a 1, the output will be the complement of the other input. This is what we want.
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“Buffer” or “Pass-through” mode “Inverter” mode
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B B
Output = B Output = B
Control = 0 Control = 1
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Four-Bit Twoʼs Complement Adder/Subtracter Circuit
Designed Around a Full Adder
A3 A2 A1 A0 B3 B2 B1 B0
o p
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1 (Subtraction)
f t
0 (Addition)
a
Operation
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Selector Switch
d
A3 A2 A1 A0 B3 B2 B1 B0
Cout 4-Bit Full Adder Cin
S3 S2 S1 S0

Design Example - Multiplexer
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A circuit that can be used to select a particular input out of several to be the single output is called a
“multiplexer.” A multiplexer is sometimes referred to as a “mux.” Typically, a multiplexer has one output,
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N selection inputs, and 2N data input bits to choose from.
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Multiplexers are referred in ways like “one-of-four” multiplexer to indicate that one output is selected
from the four inputs...using two other bits to control which input is selected. Similarly, there are “one-of-
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eight” or “one of sixteen” multiplexers having input bits of increasing powers of two and correspondingly
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increasing numbers of selection control inputs.
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Which data input bit is selected is determined by a binary number pattern input to part of the multiplexer
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circuit. The output state will be the same as the input bit corresponding to that number. That is, if a binary
number corresponding to “3” is the selector input, then the output state will be the same as input bit #3, if
“5” is the selection control value, then the output state will be the same as input bit #5, and so on.
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This selection can be accomplished using AND gates, each with multiple enable inputs. The enabling inputs
are different for each AND gate and correspond to each number in the range allowed by the selector input
control bits.
The following circuit is an implementation of a one-of-eight multiplexer. Eight data input bits can be
selected with three selection lines. Each data input bit is connected to different four-input (also known as
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quad-input) AND gates. The other three inputs of each AND gate are connected to an enabling combination
of the selection lines in a way that each binary number in the range of zero through seven will cause a
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specific AND gate to be enabled. This will allow the selected data bit to pass through to the multiplexer
output through an OR gate fed by all of the AND gate outputs. Only one AND gate is enabled and the
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remainder are disabled to force their outputs to be 0. The one enabled AND gate will have its input data bit,
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a 0 or 1, appear at the multiplexer output as the same 0 or 1.
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To help understand the way this circuit works, the selection control enabling lines have been highlighted
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in a way to help visualize the binary count enabling planned for each AND gate. The complemented
and uncomplemented Select_2, Select_1, and Select_0 selection control inputs are drawn such that the
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inverted form of a given selection control appears as a thin line and the non-inverted form appears as a
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thick line (interpreted as thick=1 and thin=0 if we consider them a binary number). This helps visualize
the binary count that will enable a given AND gate. For example, the AND gate that controls data input
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bit D3 is selected or enabled with the inverted (thin) Select_2 value, the non-inverted (thick) Select_1, and
non-inverted (thick) Select_0 values. This will happen when Select_2, Select_1, and Select_0 lines are 0, 1,
1, respectively (310=0112).

p y
o
Select_2
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Select_1
f t
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Select_0
D7 D6 D5 D4 D3 D2 D1 D0
d
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c o
Output
f t
Implementation of a One-of-Eight Multiplexer
d r a
Design Example - BCD Adder Circuit
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Review BCD addition in the chapter on Addition and Negative Numbers. BCD addition is implemented
using two, four-bit full adders, OR gates and an AND gate as shown within the dotted rectangle below. And
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the BCD numerals as binary to produce an intermediate sum. If the carry out is 0 and the intermediate sum
is between zero and nine, the intermediate sum is valid and needs no correction. If the carry out is 1 OR if
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the four-bit intermediate sum is greater than nine, correction is needed for the invalid intermediate sum.
c
To correct or not correct is handled with the AND gate and the two OR gates. The need to correct is
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determined by looking at the first adderʼs carry-out bit is 1 OR if the intermediate sum is greater than
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nine. Greater than nine is detected by
A3 A2 A1 A0 B3 B2 B1 B0
testing sum bits S3, S2, and S1 . An BCD BCD
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intermediate result greater than numeral numeral
nine will known whenever S3=1
AND (S2=1 OR S1=1). The
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A A A A B B B B
greater than nine test is ORed
3 2 1 0 3 2 1 0
intermediate
with the carry-out bit test. If carry-out bit 4-Bit Full Adder
C out C in Cin
either case exists, the result
of the correction check is 1. A S S S S
result of 0 only happens if no test if > 9 3 2 1 0
correction is needed. S3
intermediate
sum
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The correction check result is S2
used in a couple ways:
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(a) as the carry-out bit and S1
(b) to produce parts of the
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correction check result
appropriate correction number to 0 = valid
1 = invalid
c
add to the intermediate sum.
correction number
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A correction number of ( 00002 or 01102 )
f
zero (00002) is added if
no correction is needed. Cout
a
A correction number of BCD correction
carry-out adder
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0 0
six (01102) is added if bit A A A A 3 2 B B B B
1 0 3 2 1 0
correction is needed. The
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correction check result is C 4-Bit Full Adder
out C
0 in
used to set the bits A2 and

A1 in the correction number S S S S 3 2 1 0
in the correction adder. Bits BCD Full Adder

A3 and A1 of that adder are
forced always to 0. final BCD
S3 S2 S1 S0 sum result

p y
c o
f t
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a f t
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f t
dra
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c o
a f t
dr
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Glossary
f t c
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addend One of the numbers to be added to at least one other number (another addend)
to produce an arithmetic sum.
adjacent cell A cell within a Karnaugh map (K-map) that borders a given cell either above
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or below or to the left or to the right of the given cell. NEVER DIAGONAL.
ASCII Acronym for “American Standard Code for Information Interchange.”
An industry-standard, binary, 7-bit input/output (I/O) code called the American
Standard Code for Information Interchange (ASCII) exists to represent most
letters and symbols used in day-to-day processing in a computer. Use of seven
bits allows for 128 different character code combinations.
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BCD Acronym for “binary-coded decimal” (see “binary coded decimal”).
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binary Relating to the base-2 number system. There are two numeric symbols: 0 1
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and these symbols can also be considered as two opposite logic states. Each
numeral position of a binary number is weighted to a different power of two
c
(..., 24, 23, 22, 21, 20, 2-1, 2-2, ...).
t
binary coded The four-bit binary representation of decimal numbers zero through nine.
f
decimal
a
bit A single binary numeral or a single variable, circuit input, or circuit output.
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Boole, George George Boole (1815-1864), honored as the “father” of symbolic logic and
binary/state algebra leading to digital logic. This symbolic logic and algebra
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system is called “Boolean algebra.”
Boolean algebra A mathematical system (not an arithmetic system) based on binary values or
states and variables grouped and combined by operations (AND, OR, NOT)
and following a few simple and specific rules. The value of any Boolean
algebra term or expression is either of the digital logic or binary states (0 or 1).

Boolean equation A logic statement whereby one Boolean expression is said to be equal to
another Boolean expression. Often, one of the Boolean expressions is a single
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variable representing a result (output) that is said to be equal to a longer
Boolean expression involving one or more other variables (inputs).
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Boolean expression A logic expression combining Boolean variables and values by way of
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groupings of operations between the each of the variables and values.
c
bubble The “inversion bubble.” The small circle that may be drawn at a gate or device
input or output to indicate an inverting operation
f t
byte A series of eight bits.
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carry in From basic arithmetic addition, the value carried in to a column of numerals
being added and this carry in comes from the previous (lower weight) column
position.
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carry out From basic arithmetic addition, the value carried out of a column of numerals
being added and this carry out will be added to the next (higher weight)
column position.
cell A box or position within a Karnaugh map (K-map).
combinational logic A logic circuit or equation involving more two or more logic gates.
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complement The inverse of a binary value or variable. The complement of A is A. The
complement of 0 is 1 (0=1) and the complement of 1 is 0 (1=0).
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decimal Relating to the base-10 number system. There are ten numeric symbols: 0 1
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2 3 4 5 6 7 8 9. Each numeral position of a decimal number is weighted to
a different power of ten (..., 104, 103, 102, 101, 100, 10-1, 10-2, ...).
c
digital A system that deals with two discrete and unique values or states. These states
t
can be considered false/true or 0/1 or low/high or off/on, etc.
f
donʼt care A variable state that will have no effect on the final output. At the discretion of
a
the designer, logic equations or circuits being developed can treat a donʼt care
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as either a 0 or a 1, depending on how the designer may choose to simplify the
equation or circuit. Perhaps a few 1s used as “donʼt-care” values (or in places
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where an input combination is not expected or important) may greatly simplify
a circuit implementation or Boolean equation of the truth table.

demultiplexer A data distributor. A digital circuit or device that accepts a single input bit and
directs the state of that input bit to one of the selected output data lines. The
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selection is made by a binary number being input at a “select output” set of
pins. This selection identifies the number/position of the desired output line
p
that is to be set to the state of the single input.
o
disable To deactivate a function or circuit. To force a function or circuit result to be
one fixed state.
c
enable To activate or allow a function or circuit result to be passed to subsequent
t
circuitry. To allow a function or circuit result to be freely propagated to
f
subsequent circuitry, regardless of the function or circuit result state.
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full adder A circuit that adds inputs that include two addend values and a carry-in value
to produce outputs that are a sum value and a carry-out value.
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gate The actual electronic hardware implementation of a Boolean logic operation
that has one or more inputs and, typically, a single output. A gate may be one
of several gates manufactured onto an integrated circuit device.
half adder A circuit that adds two input values to produce outputs that are a sum value
and a carry-out value.
hex Abbreviated name for “hexadecimal” and relating to base-16 number system.
y
Also, “hex” can refer to “six” of something, as in a “hex inverter” is an
integrated circuit containing six inverters.
p
hexadecimal Relating to the base-16 number system. There are sixteen hexadecimal
o
numeric symbols: 0 1 2 3 4 5 6 7 8 9 A B C D E F. Each numeral
position of a hexadecimal number is weighted to a different power of sixteen
c
(..., 164, 163, 162, 161, 160, 16-1, 16-2, ...).
t
inversion bubble The small circle that may be drawn at a gate or device input or output to
f
indicate an inverting operation
a
Karnaugh Map A tabular of output variable states arranged in a rectangle of cells. The overall
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(K-map) rectangle is divided and labeled with input variable states. Each variableʼs
state possibilities (0 or 1, complemented or uncomplemented) completely in
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half the cells of the K-map rectangle. Each cell in a K-map is associated with a
Boolean “product” term formed by combining the variable state labels of each
row and column that intersect at that particular cell. The method of dividing
and labeling is covered in the chapter on Karnaugh maps and a cell can have
more than one variable associated with any given row or column.
least significant bit The bit position with the least weight in a binary number. When written or
printed, this is typically the right-most bit.

literal A binary variable or the complement of a binary variable. A function with
n variables has 2n distinct literals.
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LSB Acronym for “least significant bit.” The bit position with the least weight in a
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binary number. When written or printed, this is typically the right-most bit.
minuend The number in a subtraction operation from which another number (the
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subtrahend) is to be subtracted to produce their arithmetic difference relative
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to the minuend. In the expression (5–2), 5 is the minuend.
most significant bit The bit position with the greatest weight in a binary number. When written or
t
printed, this is typically the left-most bit.
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MSB Acronym for “most significant bit.” The bit position with the greatest weight
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in a binary number. When written or printed, this is typically the left-most bit.
multiplexer A data selector. Sometimes called a “mux.” A digital circuit device that is
d
used to select any one input from its multiple data inputs to be routed to the
single output of the device. Multiplexers have data inputs in quantities that are
powers of two. A multiplexer with 2n data input bits has n data selection input
lines. The selection is made by a binary number being input at a “select input”
set of pins. This selection identifies the number/position of the desired input
bit to be sent to the output.
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mux A nickname for “multiplexer.”
octal
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Relating to the base-8 number system.There are eight octal numeric symbols:
0 1 2 3 4 5 6 7. Each numeral position of an octal number is weighted to a
o
different power of eight (..., 84, 83, 82, 81, 80, 8-1, 8-2, ...).
c
oneʼs-complement The complement of a pattern of binary bits. From the original pattern of bits, 1
and 0 values are interchanged.
t
overflow A condition in basic addition of two fixed-length binary numbers where
f
the result includes a carry out of the most significant bit position (the result
a
doesnʼt “fit” in the same length). A condition in twoʼs-complement addition of
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two numbers of the same sign where the sign of the result is not the same as
the sign of both addends (two positives must result in a positive sum and two
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negatives must result in a negative sum). Overflow cannot result when adding
a negative number to a positive number.
POS Acronym for “Product-of-Sums”
product The arithmetic result of the multiplication of numbers.
Product-of-Sums One or more Boolean “sum terms” (ORed variable groups) ANDed together.

product term One or more Boolean variables or literals all ANDed together. An example of
a product term is (A B C).
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radix The number used as the basis of a numeration scale.
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schematic A representation of a circuit that uses symbols for logic gates and lines
o
showing interconnections between gates and their inputs and outputs.
sign bit The left-most bit (the MSB) of a twoʼs-complement number used to represent
c
the sign of a number where 0=positive and 1=negative.
t
SOP Acronym for “Sum-of-Products”
f
subtrahend The number in a subtraction operation which is subtracted from another
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number (the minuend) to produce their arithmetic difference relative to the
minuend. In the expression (5–2), 2 is the subtrahend.
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sum The arithmetic result of the addition of numbers.
Sum-of-Products One or more Boolean “product terms” (ANDed variable groups) ORed
together.
sum term One or more Boolean variables or literals all ORed together. An example of a
sum term is (A+B+D).
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truth table A tabular listing of input variables and outputs. Each variable and output
appears as a column heading. Each row or line of the table lists a unique input
p
variable state combination and corresponding states of the outputs. A truth
table having n input variables has 2n combinations of input variable states.
o
twoʼs-complement A fixed-length binary number format where the most significant bit (MSB)
c
is 0 for positive numbers and 1 for negative numbers. The magnitude of the
number is defined by the remaining bits as follows: positive numbers are
t
represented normally as a binary number and negative number magnitudes are
f
represented by first converting the absolute value of the number to binary then
a
take the oneʼs-complement of that and finally add one to the result.
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The twoʼs-complement of a number (positive or negative) is the negative
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of that original twoʼs-complement number. This obtained by taking the
oneʼs-complement of the original number and then adding one to the result.
This will result in a positive number if the original was negative and a
negative number if the original was positive.

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Digital Logic Basics B

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Digital Logic Basics

Rapid Reference and Refresher

Rapid Reference and Refresher

Published by MoonDocs LLC

Anderson, Indiana USA

Arithmetic and Negative Numbers . . . . . . . . . . . . . . . . . . . . . . . . 15

ii Digital Logic Basics: Rapid Reference and Refresher

Refresher, Reference, and Introduction All in One

Digital Logic Basics: Rapid Reference and Refresher 1

Digital Logic Basics: Rapid Reference and Refresher 3

A positive, ﬁxed-point number in a base-R number system is written as

Digital Logic Basics: Rapid Reference and Refresher 5

Convert Base-10 Integer to Base-R Integer

6 Digital Logic Basics: Rapid Reference and Refresher

Digital Logic Basics: Rapid Reference and Refresher 7

8 Digital Logic Basics: Rapid Reference and Refresher

Convert the decimal number 742 to octal (base 8)

Digital Logic Basics: Rapid Reference and Refresher 9

The corresponding decimal number is

10 Digital Logic Basics: Rapid Reference and Refresher

Digital Logic Basics: Rapid Reference and Refresher 11

Decimal Number Written as BCD

12 Digital Logic Basics: Rapid Reference and Refresher

16 Digital Logic Basics: Rapid Reference and Refresher

C Carry in in CN-1 CN-2 … C2 C1 C0 0

Digital Logic Basics: Rapid Reference and Refresher 17

18 Digital Logic Basics: Rapid Reference and Refresher

Digital Logic Basics: Rapid Reference and Refresher 19

Digital Logic Basics: Rapid Reference and Refresher 21

22 Digital Logic Basics: Rapid Reference and Refresher

therefore 111000012 = –3110 DONE

Digital Logic Basics: Rapid Reference and Refresher 25

26 Digital Logic Basics: Rapid Reference and Refresher

Intended Decimal Twoʼs Complement Decimal Equivalent of

Digital Logic Basics: Rapid Reference and Refresher 27

Examples of Twoʼs-Complement Subtraction

therefore 00101101 2 = 4510

28 Digital Logic Basics: Rapid Reference and Refresher

therefore we do not have an answer

Digital Logic Basics: Rapid Reference and Refresher 29

Find the product of 110012 and 10112

c o equivalent to product of 25 and 11

carry to next column 1 1 1 1 1

Digital Logic Basics: Rapid Reference and Refresher 31

carry to next column

Find the quotient 11100102 divided by 1102 equivalent to 114 divided by 6

Digital Logic Basics: Rapid Reference and Refresher 35

36 Digital Logic Basics: Rapid Reference and Refresher

Digital Logic Basics: Rapid Reference and Refresher 37

38 Digital Logic Basics: Rapid Reference and Refresher

Digital Logic Basics: Rapid Reference and Refresher 39

When Adding (A + B + Cin) as Binary When Adding (A + B + Cin) as BCD

Cout* S3* S2* S1* S0* Cout S3 S2 S1 S0

40 Digital Logic Basics: Rapid Reference and Refresher

Procedure to Perform BCD Addition of Two Numbers, A and B

Digital Logic Basics: Rapid Reference and Refresher 41

Final BCD Sum 0001 1001 BCD 19 10

Final BCD Sum 0001 0001 1001 0101 BCD 1195 10

42 Digital Logic Basics: Rapid Reference and Refresher

Final BCD Sum 0010 0111 0001 BCD 271 10

Digital Logic Basics: Rapid Reference and Refresher 43

Digital Logic Basics: Rapid Reference and Refresher 45

46 Digital Logic Basics: Rapid Reference and Refresher

The ASCII codes in binary would be: