Result

Experiment 1

VHDL code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity no11 is
port ( clr :in std_logic;
clk : in std_logic;
q: out std_logic_vector(2 downto 0));
end no11;

architecture Behavioral of no11 is

signal tmp : std_logic_vector (2 downto 0);
begin
process (clk, clr)
begin
if (clr = '1') then
tmp <= "000";
elsif (clk' event and clk = '1') then
tmp <= tmp + 1;
end if;
end process;
q <= tmp;
end Behavioral;
RTL schematic

Technology schematic
Behavioral Simulation output

Between 120ns - 400ns

CLR is logic ‘1’, thus the output are always LOW. For the output above, CLR was set to HIGH for
seven clocks

Between 400ns - 560ns

CLR is logic ‘0’, thus it will count up and repeat after all the ouput are ‘1’, but for this
experiment, it will only count up to logic ‘100’ because of the CLR state will reset the output to all LOW

These progresses will end at 560ns and repeat again thereafter.

Experiment 2(a)

VHDL code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MOD10 is
PORT(CLR:IN STD_LOGIC;
CLK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
end MOD10;

architecture Behavioral of MOD10 is

SIGNAL TMP: STD_LOGIC_VECTOR (3 DOWNTO 0);
Begin
PROCESS(CLK,CLR)
BEGIN
IF (CLR='1')THEN
TMP<="0000";
ELSIF(CLK'EVENT AND CLK ='1')THEN

IF (TMP = 9) THEN
TMP <= "0000";

ELSE
TMP<=TMP + 1;
END IF;
END IF;
END PROCESS;
Q<=TMP;

end Behavioral;
.
RTL schematic
Technology schematic
Behavioral Simulation output

Between 60ns - 80ns

A must to initiate the logic circuit, CLR is set to HIGH
Between 120ns - 480ns
The counter will count from 0 up to 9 or '1001' and restart again to '0000' because CLR is LOW
and also because this is a MOD10 counter

These progresses will end at 600ns and repeat again thereafter.

Experiment 2(b)

VHDL code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity NO2B is
port(CLK,RST,UD,EN : in std_logic;
Q : out std_logic_vector(2 downto 0));
end NO2B;

architecture Behavioral of NO2B is

SIGNAL tmp:std_logic_vector (2 downto 0);
begin
process (CLK,RST)
begin
if (RST='1') then
tmp <= "000";

elsif (CLK'event and CLK='1' and EN = '1') then

if (UD ='0') then

tmp <= tmp + 1;

else
tmp <= tmp - 1;
end if;
end if;
end process;
Q <= tmp;

end Behavioral;
RTL schematic
Technology schematic
Behavioral Simulation output

At 60ns
A must to initiate the logic circuit, RST is set to HIGH will result of all outputs to reset

Between 60ns - 360ns

Logic of EN is set to HIGH, this will enable the circuit to count

Between 120ns - 270ns

Logic of UD is HIGH will result in the circuit to count down

Between 270ns - 320ns

RST is HIGH, this will result in all of the output to LOW

Between 320ns - 360ns (one clock cycle)

It will start to count down from '000' to '111'

Between 360ns - 440ns

The count will stop because EN is logic LOW, thus it stays at logic '111'

Between 440ns - 590ns

Logic of UD is LOW, and EN is HIGH again will result in the circuit to count up

These progress will end at 590ns and repeat again thereafter.