Scoreboarding or SVA?

I see a difference between "scoreboarding + checking" and assertions. I see scoreboarding for
special cases, like the results of signal processing, or something very complex. In my paper SVA
in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-
a-UVM-Class-based-Environment
I make the following CONCLUSIONS AND RECOMMENDATIONS
Verification consists of several methodologies that work well, particularly when combined in
symphony. UVM is a class-based methodology that tends to stress the use of scoreboarding to
compare expected results against actual observations. Though the scoreboarding approach solves
many verification tasks, SVA provides another complementary approach that works with UVM
to speed up the model building process, to support the class-based environment, and to quickly
localize errors at the cycle level.
Bottom line, I am not enamored by scoreboards, particularly if they are copies of the RTL.

SVA provides complementary advantages for UVM. This includes the simpler definition of
temporal design properties for verification and coverage; the support of covergroup sampling
control based on sequence of events; the localized detection of errors and effective debug via on-
demand waveform/transaction recording; the control of system level tasks based on sequence of
events; and the reporting of errors back to the UVM environment for flow control.

For bus protocol types of verification properties (signal level verification), we recommend SVA
at the interfaces instead of using scoreboarding with compare as a verification technique. If a tool
supports SystemVerilog checkers (1800-2009 and 2012), use checkers bound to interfaces.
Assertion results can be written into the interface variables or class static variables for control
and access by the UVM environment. For coverage of temporal properties, use assertions in SV
interfaces. For covergroups that require the completion of temporal sequences as the sampling
trigger, use SVA sequences that can transfer the sampling triggers to class variables. Use UVM
severity levels in all SVA action blocks instead of the SystemVerilog native severity levels. Use
SVA immediate assertions to flag unsuccessful randomization and terminate the simulation run.

Consider this example: http://SystemVerilog.us/vf/counter_rtlOK.sv

This is a very weird kind of counter, complex to stress the values and capabilities of assertions:
// requirements:
// Loadable counter, reset to 0 if reset_n==0,
// Min count -2, Max count ==5
// This is an activity counter, thus count must change at least
// every 8 cycles
In the model (link above) I used assertions to model the requirements and to veify the RTL.
SVA models can be bound to the RTL in the testbench. SV interfaces are other places to put
assertions.
Other papers of interest are shown below.
1) SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
2) https://verificationacademy.com/forums/systemverilog/sva-package-dynamic-and-range-
delays-and-repeats
Question: How about if there is a requirement where we need to verify the whole
RTL using scoreboard with checkers implemented, then there is no option right?
Adding assertions for whole of the RTL will make look code bigger. What is your
take on it.

What is a scoreboard with checkers other than a set of assertions (in the English sense, not SVA
sense) to attest that the design is correct?
The implementation of that verification mechanism can be done in a variety of ways.

1. Visual analysis of the waveforms -- Outdated now, but valid way back then/
2. Hardware emulation or breadboard of the design
3. verification code -- scoreboard with checkers, SVA, SVA emulation (see 1) SVA Alternative
for Complex Assertions in my signature)

Items like interface protocols are best tested with SVA, an assertion language defines the
properties of the design and thru simulation or formal verification checks that the design meets
the requirements.
Computational items can also use SVA, even something like a CPU with complex instructions
like ADD, Multiply, divide, read, write, and combination of.
I see the use of a scoreboard for complex things like signal processing that performs complex
operations on an image (FFT, other filters).
The danger of using a scoreboard is that it tends to mimic the design, hopefully at a higher level
if that is possible. It does not address the requirements directly. One could even cheat and copy
the RTL, which defeats the purpose. SVA, on the other hand, addresses the requirements and not
the implementation, and that brings out a better understanding of the requirements, along with its
weaknesses for lack of definitions. Different aspects of the requirements are also addressed with
SVA (see my funky counter above).
By the way, even the scoreboard has to meet the requirements, but the angle of approach is the
implementation, though at a higher level if possible. SVA targets the requirements directly.
That's my take.

Ben Cohen

http://www.systemverilog.us/ ben@systemverilog.us

For training, consulting, services: contact http://cvcblr.com/home

* [url=http://goo.gl/JOfuEB]SVA Handbook 4th Edition, 2016 ISBN 978-1518681448[/url]

* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5

* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-
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* [url=https://goo.gl/d10QHh]Real Chip Design and Verification Using Verilog and VHDL,

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* Component Design by Example ", 2001 ISBN 0-9705394-0-1

* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1

* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

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1) SVA Alternative for Complex Assertions

https://verificationacademy.com/news/verification-horizons-march-2018-issue

2) https://verificationacademy.com/forums/systemverilog/sva-package-dynamic-and-range-
delays-and-repeats

3) SVA in a UVM Class-based Environment

https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-
in-a-UVM-Class-based-Environment