library IEEE;

use IEEE.std_logic_1164.all;
entity CONTADOR is
generic(J0,K0,J1,K1,J2,K2:std_logic := '1');
port( Q0:out std_logic;
Q1:out std_logic;
Q2:out std_logic;
clk: in std_logic);
end CONTADOR;

architecture main of CONTADOR is

--divisor de frecuencia
signal NK: std_logic;
signal count :integer range 0 to 99999999:=0;
signal pulso: std_logic:='0';
--Fin divisor de frecuencia

signal Q0int:std_logic:='0';
signal Q1int:std_logic:='0';
signal Q2int:std_logic:='0';
--
begin
tff:process(clk,NK)
begin
--divisor de frecuencia
if(rising_edge(clk)) then
if (count=25000000) then
pulso<=not(pulso);
count<=0;
else
count<=count+1;
end if;
end if;
NK<=pulso;
--Fin divisor de frecuencia

if(falling_edge(NK)) then
Q0int<=not(Q0int);
end if;
if(falling_edge(Q0int)) then
Q1int<=not(Q1int);
end if;
if(falling_edge(Q1int)) then
Q2int<=not(Q2int);
end if;

Q0<=Q0int;
Q1<=Q1int;
Q2<=Q2int;
end process tff;

end main;