Professional Documents
Culture Documents
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
CMOS Technology:
• Low power, high speed Flash technology
• Wide operating voltage range (2.5V to 5.5V)
• Industrial and Extended temperature ranges
• Low power consumption
UART
SPITM
I2CTM
CAN
SRAM EEPROM Timer Input A/D 10-bit Quad
Device Pins Mem. Bytes/ Comp/Std Control
Bytes Bytes 16-bit Cap 500 Ksps Enc
Instructions PWM PWM
28-Pin QFN
EMUC3/AN1/VREF- /CN3/RB1
EMUD3/AN0/VREF+/CN2/RB0
PWM1H/RE1
PWM1L/RE0
MCLR
AVDD
AVSS
22
28
27
26
25
24
23
AN2/SS1/CN4/RB2 1 21 PWM2L/RE2
AN3/INDX/CN5 RB3 2 20 PWM2H/RE3
AN4/QEA/IC7/CN6/RB4 3 19 PWM3L/RE4
AN5/QEB/IC8/CN7/RB5 4 dsPIC30F2010 18 PWM3H/RE5
VSS 5 17 VDD
OSC1/CLKIN 6 16 VSS
OSC2/CLKO/RC15 7 15 PGC/EMUC/U1RX/SDI1/SDA/RF2
10
12
13
14
11
8
9
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
VDD
EMUD2/OC1/IC1/INT1/RD0
EMUC2/OC0/IC1/INT0/RD0
PGD/EMUD/U1TX/SDO1/SCL/RF3
FLTA/INT0/SCK1/OCFA/RE8
Note: Pinout subject to change. See specific device data sheet for the most current design information.
MCLR 1 28 AVDD
EMUD3/AN0/VREF+/CN2/RB0 2 27 AVSS
EMUC3/AN1/VREF-/CN3/RB1 3 26 PWM1L/RE0
AN2/SS1/CN4/RB2 4 25 PWM1H/RE1
dsPIC30F3010
dsPIC30F2010
AN3/INDX/CN5/RB3 5 24 PWM2L/RE2
AN4/QEA/IC7/CN6/RB4 6 23 PWM2H/RE3
AN5/QEB/IC8/CN7/RB5 7 22 PWM3L/RE4
VSS 8 21 PWM3H/RE5
OSC1/CLKI 9 20 VDD
OSC2/CLKO/RC15 10 19 VSS
EMUD1/SOSCI/T2CK/U1ATX/CN1//RC13 11 18 PGC/EMUC/U1RX/SDI1/SDA/RF2
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 12 17 PGD/EMUD/U1TX/SDO1/SCL/RF3
VDD 13 16 FLTA/INT0/SCK1/OCFA/RE8
EMUD2/OC2/IC2/INT2/RD1 14 15 EMUC2/OC1/IC1/INT1/RD0
Note: Pinout subject to change. See specific device data sheet for the most current design information.
MCLR 1 28 AVDD
EMUD3/AN0/VREF+/CN2/RB0 2 27 AVSS
EMUC3/AN1/VREF-/CN3/RB1 3 26 PWM1L/RE0
AN2/SS1/CN4/RB2 4 25 PWM1H/RE1
dsPIC30F4012
AN3/INDX/CN5/RB3 5 24 PWM2L/RE2
AN4/QEA/IC7/CN6/RB4 6 23 PWM2H/RE3
AN5/QEB/IC8/CN7/RB5 7 22 PWM3L/RE4
VSS 8 21 PWM3H/RE5
OSC1/CLKI 9 20 VDD
OSC2/CLKO/RC15 10 19 VSS
EMUD1/SOSCI/T2CK/U1ATX/CN1//RC13 11 18 PGC/EMUC/U1RX/SDI1/SDA/C1RX/RF2
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 12 17 PGD/EMUD/U1TX/SDO1/SCL/C1TX/RF3
VDD 13 16 FLTA/INT0/SCK1/OCFA/RE8
EMUD2/OC2/IC2/INT2/RD1 14 15 EMUC2/OC1/IC1/INT1/RD0
Note: Pinout subject to change. See specific device data sheet for the most current design information.
40-Pin PDIP
MCLR 1 40 AVDD
EMUD3/AN0/VREF+/CN2/RB0 2 39 AVSS
EMUC3/AN1/VREF-/CN3/RB1 3 38 PWM1L/RE0
AN2/SS1/LVDIN/CN4/RB2 4 37 PWM1H/RE1
AN3/INDX/CN5/RB3 5 36 PWM2L/RE2
AN4/QEA/IC7/CN6/RB4 6 35 PWM2H/RE3
AN5/QEB/IC8/CN7/RB5 7 34 PWM3L/RE4
dsPIC30F3011
AN6/OCFA/RB6 8 33 PWM3H/RE5
AN7/RB7 9 32 VDD
AN8/RB8 10 31 VSS
VDD 11 30 RF0
VSS 12 29 RF1
OSC1/CLKI 13 28 U2RX/RF4
OSC2/CLKO/RC15 14 27 U2TX/RF5
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 15 26 PGC/EMUC/U1RX/SDI1/SDA/RF2
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 16 25 PGD/EMUD/U1TX/SDO1/SCK/RF3
FLTA/INT0/RE8 17 24 SCK1/RF6
EMUD2/OC2/IC2/INT2/RD1 18 23 EMUC2/OC1/IC1/INT1/RD0
OC4/RD3 19 22 OC3/RD2
VSS 20 21 VDD
Note: Pinout subject to change. See specific device data sheet for the most current design information.
40-Pin PDIP
MCLR 1 40 AVDD
EMUD3/AN0/VREF+/CN2/RB0 2 39 AVSS
EMUC3/AN1/VREF-/CN3/RB1 3 38 PWM1L/RE0
AN2/SS1/LVDIN/CN4/RB2 4 37 PWM1H/RE1
AN3/INDX/CN5/RB3 5 36 PWM2L/RE2
AN4/QEA/IC7/CN6/RB4 6 35 PWM2H/RE3
AN5/QEB/IC8/CN7/RB5 7 34 PWM3L/RE4
dsPIC30F4011
AN6/OCFA/RB6 8 33 PWM3H/RE5
AN7/RB7 9 32 VDD
AN8/RB8 10 31 VSS
VDD 11 30 C1RX/RF0
VSS 12 29 C1TX/RF1
OSC1/CLKI 13 28 U2RX/RF4
OSC2/CLKO/RC15 14 27 U2TX/RF5
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 15 26 PGC/EMUC/U1RX/SDI1/SDA/RF2
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 16 25 PGD/EMUD/U1TX/SDO1/SCK/RF3
FLTA/INT0/RE8 17 24 SCK1/RF6
EMUD2/OC2/IC2/INT2/RD1 18 23 EMUC2/OC1/IC1/INT1/RD0
OC4/RD3 19 22 OC3/RD2
VSS 20 21 VDD
Note: Pinout subject to change. See specific device data sheet for the most current design information.
44-Pin TQFP
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
PGD/EMUD/U1TX/SDO1/SCL/RF3
EMUD/OC2/IC2/INT2/RD1
FLTA/INT0/RE8
IC1/INT1/RD8
SCK1/RF6
OC4/RD3
OC3/RD2
VDD
VSS
NC
44
43
42
41
40
39
38
37
36
35
34
PGC/EMUC/U1RX/SDI1/SDA/RF2 1 33 NC
U2TX/CN18/RF5 2 32 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
U2RX/CN17/RF4 3 31 OSC2/CLKO/RC15
RF1 4 30 OSC1/CLKI
RF0 5 29 VSS
VSS 6 dsPIC30F3011 28 VDD
VDD 7 27 AN8/RB8
PWM3H/RE5 8 26 AN7/RB7
PWM3L/RE4 9 25 AN6/OCFA/RB6
PWM2H/RE3 10 24 AN5/QEB/IC8/CN7/RB5
PWM2L/RE2 11 23 AN4/QEA/IC7/CN6/RB4
12
13
14
15
16
17
18
19
20
21
22
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
NC
NC
MCLR
PWM1H/RE1
PWM1L/RE0
AVSS
AVDD
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
Note: Pinout subject to change. See specific device data sheet for the most current design information.
44-Pin QFN
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
PGD/EMUD/U1TX/SDO1/SCL/RF3
EMUD2/OC2/IC2/INT2/RD1
EMUC2/OC1/IC1/INT1/RD0
FLTA/INT0/RE8
SCK1/RF6
OC4/RD3
OC3/RD2
VDD
VSS
44
43
42
41
40
39
38
37
36
35
34
PGC/EMUC/U1RX/SDI1/SDA/RF2 1 33 OSC2/CLKO/RC15
U2TX/CN18/RF5 2 32 OSC1/CLKI
U2RX/CN17/RF4 3 31 VSS
RF1 4 30 VSS
RF0 5 29 VDD
VSS 6 dsPIC30F3011 28 VDD
VDD 7 27 AN8/RB8
VDD 8 26 AN7/RB7
PWM3H/RE5 9 25 AN6/OCFA/RB6
PWM3L/RE4 10 24 AN5/QEB/IC8/CN7/RB5
PWM2H/RE3 11 23 AN4/QEA/IC7/CN6/RB4
12
13
14
15
16
17
18
19
20
21
22
PWM2L/RE2
MCLR
NC
PWM1L/RE0
AVSS
AVDD
PWM1H/RE1
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
Note: Pinout subject to change. See specific device data sheet for the most current design information.
44-Pin TQFP
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
PGD/EMUD/U1TX/SDO1/SCL/RF3
EMUC2/OC1/IC1/INT1/RD0
EMUD2/OC2/IC2/INT2/RD1
FLTA/INT0/RE8
SCK1/RF6
OC3/RD2
OC4/RD3
VDD
VSS
NC
44
43
42
41
40
39
38
37
36
35
34
PGC/EMUC/U1RX/SDI1/SDA/RF2 1 33 NC
U2TX/CN18/RF5 2 32 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
U2RX/CN17/RF4 3 31 OSC2/CLKO/RC15
CTX1/RF1 4 30 OSC1/CLKIN
CRX1/RF0 5 29 VSS
VSS 6 28 VDD
dsPIC30F4011 AN8/RB8
VDD 7 27
PWM3H/RE5 8 26 AN7/RB7
PWM3L/RE4 9 25 AN6/OCFA/RB6
PWM2H/RE3 10 24 AN5/QEB/IC8/CN7/RB5
PWM2L/RE2 11 23 AN4/QEA/IC7/CN6/RB4
12
13
14
15
16
17
18
19
20
21
22
NC
NC
PWM1L/RE0
MCLR
AN2/SS1/CN4/RB2
PWM1H/RE1
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN3/INDX/CN5/RB3
AVSS
AVDD
Note: Pinout subject to change. See specific device data sheet for the most current design information.
44-Pin QFN
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
PGD/EMUD/U1TX/SDO1/SCL/RF3
EMUD2/OC2/IC2/INT2/RD1
EMUC2/OC1/IC1/INT1/RD0
FLTA/INT0/RE8
SCK1/RF6
OC4/RD3
OC3/RD2
VDD
VSS
44
43
42
41
40
39
38
37
36
35
34
PGC/EMUC/U1RX/SDI1/SDA/RF2 1 33 OSC2/CLKO/RC15
U2TX/CN18/RF5 2 32 OSC1/CLKIN
U2RX/CN17/RF4 3 31 VSS
CTX1/RF1 4 30 VSS
CRX1/RF0 5 29 VDD
VSS 6 dsPIC30F4011 28 VDD
VDD 7 27 AN8/RB8
VDD 8 26 AN7/RB7
PWM3H/RE5 9 25 AN6/OCFA/RB6
PWM3L/RE4 10 24 AN5/QEB/IC8/CN7/RB5
PWM2H/RE3 11 23 AN4/QEA/IC7/CN6/RB4
12
13
14
15
16
17
18
19
20
21
22
EMUC3/AN1/VREF-/CN3/RB1
NC
MCLR
EMUD3/AN0/VREF+/CN2/RB0
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
PWM2L/RE2
PWM1H/RE1
PWM1L/RE0
AVSS
AVDD
Note: Pinout subject to change. See specific device data sheet for the most current design information.
64-Pin TQFP
EMUD2/OC2/RD1
CN16/UPDN/RD7
PWM2H/RE3
PWM1H/RE1
PWM3L/RE4
PWM2L/RE2
PWM1L/RE0
CRX1/RF0
CN15/RD6
CN14/RD5
CN13/RD4
CTX1/RF1
OC4/RD3
OC3/RD2
VDD
VSS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PWM3H/RE5 1 48 EMUC1/SOSCO/T1CK/CN0/RC14
PWM4L/RE6 2 47 EMUD1/SOSCI/T4CK/CN1/RC13
PWM4H/RE7 3 46 EMUC2/OC1/RD0
SCK2/CN8/RG6 4 45 INT4/RD11
SDI2/CN9/RG7 5 44 INT3/RD10
SDO2/CN10/RG8 6 43 IC2/FLTB/INT2/RD9
MCLR 7 42 IC1/FLTA/INT1/RD8
SS2/CN11/RG9 8 dsPIC30F5015 41 VSS
VSS 9 40 OSC2/CLKO/RC15
VDD 10 39 OSC1/CLKIN
AN5/QEB/IC8/CN7/RB5 11 38 VDD
AN4/QEA/IC7/CN6/RB4 12 37 SCL/RG2
AN3/INDX/CN5/RB3 13 36 SDA/RG3
AN2/SS1/LVDIN/CN4/RB2 14 35 EMUC3/SCK1/INT0/RF6
AN1/VREF-/CN3/RB1 15 34 U1RX/SDI1/RF2
AN0/VREF+/CN2/RB0 16 33 EMUD3/U1TX/SDO1/RF3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AN10/RB10
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
PGD/EMUD/AN7/RB7
AVDD
AVSS
AN8/RB8
AN9/RB9
AN11/RB11
VSS
VDD
CN17/RF4
CN18/RF5
PGC/EMUC/AN6/OCFA/RB6
Note: Pinout subject to change. See specific device data sheet for the most current design information.
80-Pin TQFP
OC8/CN16/UPDN/RD7
EMUD2/OC2/RD1
OC6/CN14/RD5
OC7/CN15/RD6
IC6/CN19/RD13
OC5/CN13/RD4
PWM2H/RE3
PWM1H/RE1
PWM2L/RE2
PWM1L/RE0
PWM3L/RE4
C2RX/RG0
C2TX/RG1
C1RX/RF0
C1TX/RF1
IC5/RD12
OC4/RD3
OC3/RD2
VDD
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PWM3H/RE5 1 60 EMUC1/SOSCO/T1CK/CN0/RC14
PWM4L/RE6 2 59 EMUD1/SOSCI/CN1/RC13
PWM4H/RE7 3 58 EMUC2/OC1/RD0
T2CK/RC1 4 57 IC4/RD11
T4CK/RC3 5 56 IC3/RD10
SCK2/CN8/RG6 6 55 IC2/RD9
SDI2/CN9/RG7 7 54 IC1/RD8
SDO2/CN10/RG8 8 53 INT4/RA15
MCLR 9 52 INT3/RA14
SS2/CN11/RG9 10 51 VSS
dsPIC30F6010
VSS 11 50 OSC2/CLKO/RC15
VDD 12 49 OSC1/CLKI
FLTA/INT1/RE8 13 48 VDD
FLTB/INT2/RE9 14 47 SCL/RG2
AN5/QEB/CN7/RB5 15 46 SDA/RG3
AN4/QEA/CN6/RB4 16 45 EMUC3/SCK1/INT0/RF6
AN3/INDX/CN5/RB3 17 44 SDI1/RF7
AN2/SS1/LVDIN/CN4/RB2 18 43 EMUD3/SDO1/RF8
PGC/EMUC/AN1/CN3/RB1 19 42 U1RX/RF2
PGD/EMUD/AN0/CN2/RB0 20 41 U1TX/RF3
21
22
34
35
36
37
38
39
40
23
24
25
26
27
28
29
30
31
32
33
IC7/CN20/RD14
AN6/OCFA/RB6
AN7/RB7
VREF-/RA9
VREF+/RA10
AVDD
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VDD
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
IC8/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
AVSS
VSS
Note: Pinout subject to change. See specific device data sheet for the most current design information.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include
literature number) you are using.
Y Data Bus
X Data Bus
16 16 16 16 VREF-/RA9
16
VREF+/RA10
Interrupt Data Latch Data Latch
PSV & Table INT3/RA14
Controller Y Data X Data
Data Access 8 16 INT4/RA15
24 Control Block RAM RAM
(4 Kbytes) (4 Kbytes)
PORTA
Address Address
24 Latch Latch PGD/EMUD/AN0/CN2/RB0
16 16 16 PGC/EMUC/AN1/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
24 X RAGU
Y AGU AN3/INDX/CN5/RB3
PCU PCH PCL X WAGU
AN4/QEA/CN6/RB4
Program Counter
AN5/QEB/CN7/RB5
Address Latch Stack Loop
Control Control AN6/OCFA/RB6
Program Memory Logic Logic AN7/RB7
(144 Kbytes) AN8/RB8
AN9/RB9
Data EEPROM
AN10/RB10
(4 Kbytes) Effective Address AN11/RB11
Data Latch 16 AN12/RB12
AN13/RB13
AN14/RB14
ROM Latch 16 AN15/OCFB/CN12/RB15
24 PORTB
IR T2CK/RC1
T4CK/RC3
16 16 EMUD1/SOSCI/CN1/RC13
EMUC1/SOSCO/T1CK/CN0/RC14
16 x 16
OSC2/CLKO/RC15
W Reg Array
Decode
PORTC
Instruction
Decode & 16 16
Control EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
Control Signals DSP
to Various Blocks Divide OC4/RD3
Power-up Engine Unit OC5/CN13/RD4
Timer OC6/CN14/RD5
Timing Oscillator OC7/CN15/RD6
OSC1/CLKI OC8/CN16/UPDN/RD7
Generation Start-up Timer
IC1/RD8
POR/BOR ALU<16> IC2/RD9
Reset IC3/RD10
Watchdog 16 16 IC4/RD11
MCLR IC5/RD12
Timer
IC6/CN19/RD13
Low Voltage IC7/CN20/RD14
VDD, VSS Detect IC8/CN21/RD15
AVDD, AVSS PORTD
PWM1L/RE0
CAN1, Input Output PWM1H/RE1
2
CAN2 10-bit ADC Capture Compare I C PWM2L/RE2
Module Module
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SPI1, Motor Control UART1, FLTA/INT1/RE8
Timers QEI
SPI2 PWM UART2 FLTB/INT2/RE9
PORTE
C1RX/RF0
C2RX/RG0
C1TX/RF1
C2TX/RG1
U1RX/RF2
SCL/RG2
U1TX/RF3
SDA/RG3
SCK2/CN8/RG6 U2RX/CN17/RF4
SDI2/CN9/RG7 U2TX/CN18/RF5
SDO2/CN10/RG8 EMUC3/SCK1/INT0/RF6
SDI1/RF7
SS2/CN11/RG9
EMUD3/SDO1/RF8
PORTG PORTF
D15 D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3 Legend
W4
DSP Operand W5
Registers
W6
W7
Working Registers
W8
W9
DSP Address
Registers W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
PC22 PC0
0 Program Counter
7 0
TABPAG
TBLPAG Data Table Page Address
7 0
PSVPAG Program Space Visibility Page Address
15 0
RCOUNT REPEAT Loop Counter
15 0
DCOUNT DO Loop Counter
22 0
DOSTART DO Loop Start Address
22
DOEND DO Loop End Address
15 0
CORCON Core Configuration Register
SRH SRL
FIGURE 2-8: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE WITH INSTRUCTION STALL
S
a
40 40-bit Accumulator A 40 Round t 16
40-bit Accumulator B u
Logic r
a
Carry/Borrow Out t
Saturate e
Carry/Borrow In Adder
Negate
40
40 40
Barrel
16
Shifter
X Data Bus
40
Sign-Extend
Y Data Bus
32 16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
16 16
To/From W Array
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1
2 0
2 14
2 13
2 12 11
2 .... 20
0x4001 = 214 + 20 = 16385
1.15 Fractional:
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1
In the special case when both input operands are 1.15 a DSP multiply in Fractional mode also includes a left
fractions and equal to 0x8000 (-110), the result of the shift by one bit to keep the radix point properly
multiplication is corrected to 0x7FFFFFFF (as the clos- aligned. This feature reduces the resolution of the
est approximation to +1) by hardware, before it is used. DSP multiplier to 2-30, but has no other effect on the
It should be noted that with the exception of DSP mul- computation.
tiplies, the dsPIC30F ALU operates identically on inte- The same multiplier is used to support the MCU multi-
ger and fractional data. Namely, an addition of two ply instructions, which include integer 16-bit signed,
integers will yield the same result (binary number) as unsigned and mixed sign multiplies. Additional data
the addition of two fractional numbers. The only differ- paths are provided to allow these instructions to write
ence is how the result is interpreted by the user. How- the result back into the W array and X data bus (via the
ever, multiplies performed by DSP operations are W array). These paths are placed prior to the data
different. In these instructions, data format selection is scaler. The IF bit in the CORCON register, therefore,
made with the IF bit (CORCON<0>) and US bits only affects the result of the MAC class of DSP instruc-
(CORCON<12>), and it must be set accordingly (‘0’ tions. All other multiply operations are assumed to be
for Fractional mode, ‘1’ for Integer mode in the case integer operations. If the user executes a MAC instruc-
of the IF bit, and ‘0’ for signed mode, ‘1’ for unsigned tion on fractional data without clearing the IF bit, the
mode in the case of the US bit). This is required result must be explicitly shifted left by the user program
because of the implied radix point used by dsPIC30F after multiplication in order to obtain the correct result.
fractions. In Integer mode, multiplying two 16-bit inte-
gers produces a 32-bit integer result. However, multi-
plying two 1.15 values generates a 2.30 result. Since
the dsPIC30F uses 1.31 format for the accumulators,
2.5.2 DATA ACCUMULATORS AND The OA and OB bits are modified each time data
passes through the adder/Subtractor. When set, they
ADDER/SUBTRACTOR
indicate that the most recent operation has overflowed
The data accumulator consists of a 40-bit adder/ into the accumulator guard bits (bits 32 through 39).
subtractor with automatic sign extension logic. It can The OA and OB bits can also optionally generate an
select one of two accumulators (A or B) as its pre- arithmetic warning trap when set and the correspond-
accumulation source and post-accumulation destina- ing overflow trap flag enable bit (OVATEN, OVBTEN) in
tion. For the ADD and LAC instructions, the data to be the INTCON1 register (refer to Section 5.0) is set. This
accumulated or loaded can be optionally scaled via the allows the user to take immediate action, for example,
barrel shifter, prior to accumulation. to correct system gain.
2.5.2.1 Adder/Subtractor, Overflow and The SA and SB bits are modified each time data passes
through the adder/subtractor, but can only be cleared by
Saturation
the user. When set, they indicate that the accumulator
The adder/subtractor is a 40-bit adder with an optional has overflowed its maximum range (bit 31 for 32-bit sat-
zero input into one side and either true or complement uration, or bit 39 for 40-bit saturation) and will be satu-
data into the other input. In the case of addition, the rated (if saturation is enabled). When saturation is not
carry/borrow input is active high and the other input is enabled, SA and SB default to bit 39 overflow and thus
true data (not complemented), whereas in the case of indicate that a catastrophic overflow has occurred. If the
subtraction, the carry/borrow input is active low and the COVTE bit in the INTCON1 register is set, SA and SB
other input is complemented. The adder/subtractor bits will generate an arithmetic warning trap when satu-
generates overflow status bits SA/SB and OA/OB, ration is disabled.
which are latched and reflected in the status register.
The overflow and saturation status bits can optionally
• Overflow from bit 39: this is a catastrophic be viewed in the Status Register (SR) as the logical OR
overflow in which the sign of the accumulator is of OA and OB (in bit OAB) and the logical OR of SA and
destroyed. SB (in bit SAB). This allows programmers to check one
• Overflow into guard bits 32 through 39: this is a bit in the Status Register to determine if either accumu-
recoverable overflow. This bit is set whenever all lator has overflowed, or one bit to determine if either
the guard bits are not identical to each other. accumulator has saturated. This would be useful for
The adder has an additional saturation block which complex number arithmetic which typically uses both
controls accumulator data saturation, if selected. It the accumulators.
uses the result of the adder, the overflow status bits The device supports three Saturation and Overflow
described above, and the SATA/B (CORCON<7:6>) modes.
and ACCSAT (CORCON<4>) mode control bits to 1. Bit 39 Overflow and Saturation:
determine when and to what value to saturate. When bit 39 overflow and saturation occurs, the
Six status register bits have been provided to support saturation logic loads the maximally positive 9.31
saturation and overflow; they are: (0x7FFFFFFFFF) or maximally negative 9.31
1. OA: value (0x8000000000) into the target accumula-
AccA overflowed into guard bits tor. The SA or SB bit is set and remains set until
cleared by the user. This is referred to as ‘super
2. OB:
saturation’ and provides protection against erro-
AccB overflowed into guard bits
neous data or unexpected algorithm problems
3. SA: (e.g., gain calculations).
AccA saturated (bit 31 overflow and saturation)
2. Bit 31 Overflow and Saturation:
or
When bit 31 overflow and saturation occurs, the
AccA overflowed into guard bits and saturated
saturation logic then loads the maximally positive
(bit 39 overflow and saturation)
1.31 value (0x007FFFFFFF) or maximally nega-
4. SB: tive 1.31 value (0x0080000000) into the target
AccB saturated (bit 31 overflow and saturation) accumulator. The SA or SB bit is set and remains
or set until cleared by the user. When this Saturation
AccB overflowed into guard bits and saturated mode is in effect, the guard bits are not used (so
(bit 39 overflow and saturation) the OA, OB or OAB bits are never set).
23 bits
Using
Program 0 Program Counter 0
Counter
Select
1 EA
Using
Program 0 PSVPAG Reg
Space
Visibility 8 bits 15 bits
EA
User/ Byte
Configuration 24-bit EA
Space Select
Select
Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory.
PC Address 23 16 8 0
0x000000 00000000
0x000002 00000000
0x000004 00000000
0x000006 00000000
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
Program Memory
‘Phantom’ Byte
TBLRDL.B (Wn<0> = 1)
(Read as ‘0’).
TBLRDH.W
PC Address 23 16 8 0
0x000000 00000000
0x000002 00000000
0x000004 00000000
0x000006 00000000
TBLRDH.B (Wn<0> = 0)
Program Memory
‘Phantom’ Byte
(Read as ‘0’) TBLRDH.B (Wn<0> = 1)
3.1.2 PROGRAM SPACE VISIBILITY Note that by incrementing the PC by 2 for each pro-
FROM DATA SPACE gram memory word, the LS 15 bits of data space
addresses directly map to the LS 15 bits in the corre-
The upper 32 Kbytes of data space may optionally be
sponding program space addresses. The remaining
mapped into any 16K word program space page. This
bits are provided by the Program Space Visibility Page
provides transparent access of stored constant data
register, PSVPAG<7:0>, as shown in Figure 3-4.
from X data space, without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/H instructions). Note: PSV access is temporarily disabled during
Program space access through the data space occurs Table Reads/Writes.
if the MS bit of the data space EA is set and program For instructions that use PSV which are executed
space visibility is enabled, by setting the PSV bit in the outside a REPEAT loop:
Core Control register (CORCON). The functions of
• The following instructions will require one instruc-
CORCON are discussed in Section 2.5, DSP Engine.
tion cycle in addition to the specified execution
Data accesses to this area add an additional cycle to time:
the instruction being executed, since two program - MAC class of instructions with data operand
memory fetches are required. pre-fetch
Note that the upper half of addressable data space is - MOV instructions
always part of the X data space. Therefore, when a - MOV.D instructions
DSP operation uses program space mapping to access
• All other instructions will require two instruction
this memory region, Y data space should typically con-
cycles in addition to the specified execution time
tain state (variable) data for DSP operations, whereas
of the instruction.
X data space should typically contain coefficient
(constant) data. For instructions that use PSV which are executed
inside a REPEAT loop:
Although each data space address, 0x8000 and
higher, maps directly into a corresponding program • The following instances will require two instruction
memory address (see Figure 3-4), only the lower cycles in addition to the specified execution time
16-bits of the 24-bit program word are used to contain of the instruction:
the data. The upper 8 bits should be programmed to - Execution in the first iteration
force an illegal instruction to maintain machine robust- - Execution in the last iteration
ness. Refer to the Programmer’s Reference Manual - Execution prior to exiting the loop due to an
(DS70030) for details on instruction encoding. interrupt
- Execution upon re-entering the loop after an
interrupt is serviced
• Any other iteration of the REPEAT loop will allow
the instruction, accessing data using PSV, to
execute in a single cycle.
Data Space
0x0000
15 PSVPAG(1)
EA<15> = 0 0x21
8
Data 16
Space 0x8000 0x108000
EA 15 23 15 0
Address
EA<15> = 1 0x108200
15 Concatenation 23
Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address
(i.e., it defines the page in program space to which the upper half of data space is being mapped).
0000FE
User Flash 000100 instructions (MAC class). The X write data bus is the
Program Memory only write path to data space for all instructions.
(48K instructions)
017FFE The X data space also supports Modulo Addressing for
018000 all instructions, subject to Addressing mode restric-
Reserved
(Read 0’s) tions. Bit-Reversed Addressing is only supported for
7FEFFE writes to X data space.
7FF000
Data EEPROM
(4 Kbytes)
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
7FFFFE
800000
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to pro-
vide two concurrent data read paths. No writes occur
across the Y bus. This class of instructions dedicates
two W register pointers, W10 and W11, to always
address Y data space, independent of X data space,
whereas W8 and W9 always address X data space.
Note that during accumulator write back, the data
Reserved address space is considered a combination of X and Y
data spaces, so the write occurs across the X bus.
Consequently, the write can be to any address in the
entire data space.
The Y data space can only be used for the data pre-
Configuration Memory
8005C0
automated circular buffers. Of course, all other instruc-
UNITID (32 instr.) tions can access the Y data address space through the
8005FE
800600 X data path, as part of the composite linear space.
Reserved The boundary between the X and Y data spaces is
F7FFFE
Device Configuration F80000 defined as shown in Figure 3-8 and is not user pro-
Registers F8000E grammable. Should an EA point to data outside its own
F80010 assigned address space, or to a location outside phys-
ical memory, an all-zero word/byte will be returned. For
example, although Y address space is visible by all
non-MAC instructions using any Addressing mode, an
attempt by a MAC instruction to fetch data from that
Reserved space, using W8 or W9 (X space pointers), will return
0x0000.
FEFFFE
DEVID (2) FF0000
FFFFFE
POP: [--W15]
PUSH: [W15++]
MS Byte LS Byte
Address 16 bits Address
MSB LSB
0x0001 0x0000
2 Kbyte SFR Space
SFR Space 0x07FE
0x07FF
0x0801 0x0800
8 Kbyte
X Data RAM (X) Near
Data
Space
8 Kbyte 0x17FF 0x17FE
SRAM Space 0x1801 0x1800
0x1FFF 0x1FFE
Y Data RAM (Y)
0x27FF 0x27FE
0x2801 0x2800
0x8001 0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF 0xFFFE
Note: The address map shown is conceptual, and may vary across individual devices depending on
available memory.
X SPACE
UNUSED
X SPACE
X SPACE
UNUSED
Indirect EA from any W Indirect EA from W8, W9 Indirect EA from W10, W11
DS70082G-page 40
W3 0006 W3 0000 0000 0000 0000
W4 0008 W4 0000 0000 0000 0000
W5 000A W5 0000 0000 0000 0000
dsPIC30F
Preliminary
ACCBL 0028 ACCBL 0000 0000 0000 0000
ACCBH 002A ACCBH 0000 0000 0000 0000
ACCBU 002C Sign-Extension (ACCB<39>) ACCBU 0000 0000 0000 0000
PCL 002E PCL 0000 0000 0000 0000
PCH 0030 — — — — — — — — — PCH 0000 0000 0000 0000
TBLPAG 0032 — — — — — — — — TBLPAG 0000 0000 0000 0000
PSVPAG 0034 — — — — — — — — PSVPAG 0000 0000 0000 0000
RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu
DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu
DOSTARTL 003A DOSTARTL 0 uuuu uuuu uuuu uuu0
DOSTARTH 003C — — — — — — — — — DOSTARTH 0000 0000 0uuu uuuu
DOENDL 003E DOENDL 0 uuuu uuuu uuuu uuu0
DOENDH 0040 — — — — — — — — — DOENDH 0000 0000 0uuu uuuu
SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0000 0000 0000
CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000
Legend: u = uninitialized bit
Preliminary
DS70082G-page 41
dsPIC30F
dsPIC30F
NOTES:
In addition, the X WAGU can support: In the Split Data Space mode, some W register address
pointers are dedicated to X RAGU, and others to Y
• Bit-Reversed Addressing AGU. The EAs of each operand must, therefore, be
Linear and Modulo Data Addressing modes can be restricted within different address spaces. If they are
applied to data space or program space. Bit-Reversed not, one of the EAs will be outside the address space
addressing is only applicable to data space addresses. of the corresponding data space (and will fetch the bus
default value, 0x0000).
4.1 Data Space Organization
4.2 Instruction Addressing Modes
Although the data space memory is organized as 16-bit
words, all effective addresses (EAs) are byte The Addressing modes in Table 4-1 form the basis of
addresses. Instructions can thus access individual the Addressing modes optimized to support the specific
bytes, as well as properly aligned words. Word features of individual instructions. The Addressing
addresses must be aligned at even boundaries. Mis- modes provided in the MAC class of instructions are
aligned word accesses are not supported, and if somewhat different from those in the other instruction
attempted, will initiate an address error trap. types.
Some Addressing mode combinations may lead to a
one-cycle stall during instruction execution, or are not
allowed, as discussed in Section 4.3.
File Register Direct The address of the file register is specified explicitly.
Register Direct The contents of a register are accessed directly.
Register Indirect The contents of Wn forms the EA.
Register Indirect Post-modified The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-modified Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.
4.2.2 MCU INSTRUCTIONS Note: Not all instructions support all the
Addressing modes given above. Individual
The three-operand MCU instructions are of the form: instructions may support different subsets
Operand 3 = Operand 1 <function> Operand 2 of these Addressing modes.
where Operand 1 is always a working register (i.e., the
4.2.4 MAC INSTRUCTIONS
Addressing mode can only be register direct), which is
referred to as Wb. Operand 2 can be W register, The dual source operand DSP instructions (CLR, ED,
fetched from data memory, or 5-bit literal. In two- EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also
operand instructions, the result location is the same as referred to as MAC instructions, utilize a simplified set of
that of one of the operands. Certain MCU instructions Addressing modes to allow the user to effectively
are one-operand operations. The following Addressing manipulate the data pointers through register indirect
modes are supported by MCU instructions: tables.
• Register Direct The two source operand pre-fetch registers must be a
• Register Indirect member of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 will always be directed to the X
• Register Indirect Post-modified
RAGU and W10 and W11 will always be directed to the
• Register Indirect Pre-modified Y AGU. The effective addresses generated (before and
• 5-bit or 10-bit Literal after modification) must, therefore, be valid addresses
Note: Not all instructions support all the within X data space for W8 and W9 and Y data space
Addressing modes given above. Individual for W10 and W11.
instructions may support different subsets Note: Register Indirect with Register Offset
of these Addressing modes. Addressing is only available for W9 (in X
space) and W11 (in Y space).
4.2.3 MOVE AND ACCUMULATOR
INSTRUCTIONS In summary, the following Addressing modes are
supported by the MAC class of instructions:
Move instructions and the DSP Accumulator class of
instructions provide a greater degree of addressing • Register Indirect
flexibility than other instructions. In addition to the • Register Indirect Post-modified by 2
Addressing modes supported by most MCU instruc- • Register Indirect Post-modified by 4
tions, Move and Accumulator instructions also support • Register Indirect Post-modified by 6
Register Indirect with Register Offset Addressing
• Register Indirect with Register Offset (Indexed)
mode, also referred to as Register Indexed mode.
Note: For the MOV instructions, the Addressing 4.2.5 OTHER INSTRUCTIONS
mode specified in the instruction can differ Besides the various Addressing modes outlined above,
for the source and destination EA. How- some instructions use literal constants of various sizes.
ever, the 4-bit Wb (Register Offset) field is For example, BRA (branch) instructions use 16-bit
shared between both source and signed literals to specify the branch destination directly,
destination (but typically only used by whereas the DISI instruction uses a 14-bit unsigned
one). literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
An example of a RAW dependency is a write operation When it observes a match between the destination and
(in the current instruction) that modifies W5, followed source registers, a set of rules are applied to decide
by a read operation (in the next instruction) that uses whether or not to stall the instruction by one cycle.
W5 as a source address pointer. W5 will not be valid for Table 4-2 lists out the various RAW conditions which
the read operation until the earlier write completes. cause an instruction execution stall.
This problem is resolved by stalling the instruction exe-
cution for one instruction cycle, thereby allowing the
write to complete before the next read is started.
Byte
Address MOV #0x1100,W0
MOV W0, XMODSRT ;set modulo start address
MOV #0x1163,W0
MOV W0,MODEND ;set modulo end address
0x1100 MOV #0x8001,W0
MOV W0,MODCON ;enable W1, X AGU for modulo
MOV #0x0000,W0 ;W0 holds buffer fill value
MOV #0x1110,W1 ;point W1 to buffer
DO AGAIN,#0x31 ;fill the 50 buffer locations
MOV W0, [W1++] ;fill the next location
AGAIN: INC W0,W0 ;increment the fill value
0x1163
Byte
Address MOV #0x11D0,W0
MOV #0, XMODSRT ;set modulo start address
MOV 0x11FF,W0
MOV W0,XMODEND ;set modulo end address
MOV #0x8001,W0
MOV W0,MODCON ;enable W1, X AGU for modulo
MOV #0x000F,W0 ;W0 holds buffer fill value
MOV #0x11E0,W1 ;point W1 to buffer
0x11D0 DO AGAIN,#0x17 ;fill the 24 buffer locations
MOV W0, [W1--] ;fill the next location
AGAIN: DEC W0,W0 ;decrement the fill value
0x11FF
Pivot Point
XB = 0x0008 for a 16-word Bit-Reversed Buffer
Math Error Trap Vector tions. Users must save the key registers in software
Priority
DS70082G-page 56
IFS1 0086 IC6IF IC5IF IC4IF IC3IF C1IF SPI2IF U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF IC8IF IC7IF INT1IF 0000 0000 0000 0000
IFS2 0088 — — — FLTBIF FLTAIF LVDIF — QEIIF PWMIF C2IF INT4IF INT3IF OC8IF OC7IF OC6IF OC5IF 0000 0000 0000 0000
IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000
dsPIC30F
IEC1 008E IC6IE IC5IE IC4IE IC3IE C1IE SPI2IE U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE IC8IE IC7IE INT1IE 0000 0000 0000 0000
IEC2 0090 — — — FLTBIE FLTAIE LVDIE — QEIIE PWMIE C2IE INT4IE INT3IE OC8IE OC7IE OC6IE OC5IE 0000 0000 0000 0000
IPC0 0094 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100
IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100
IPC2 0098 — ADIP<2:0> — U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100
IPC3 009A — CNIP<2:0> — MI2CIP<2:0> — SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100
IPC4 009C — OC3IP<2:0> — IC8IP<2:0> — IC7IP<2:0> — INT1IP<2:0> 0100 0100 0100 0100
IPC5 009E — INT2IP<2:0> — T5IP<2:0> — T4IP<2:0> — OC4IP<2:0> 0100 0100 0100 0100
IPC6 00A0 — C1IP<2:0> — SPI2IP<2:0> — U2TXIP<2:0> — U2RXIP<2:0> 0100 0100 0100 0100
IPC7 00A2 — IC6IP<2:0> — IC5IP<2:0> — IC4IP<2:0> — IC3IP<2:0> 0100 0100 0100 0100
IPC8 00A4 — OC8IP<2:0> — OC7IP<2:0> — OC6IP<2:0> — OC5IP<2:0> 0100 0100 0100 0100
IPC9 00A6 — PWMIP<2:0> — C2IP<2:0> — INT41IP<2:0> — INT3IP<2:0> 0100 0100 0100 0100
IPC10 00A8 — FLTAIP<2:0> — LVDIP<2:0> — — — — — QEIIP<2:0> 0100 0100 0000 0100
IPC11 00AA — — — — — — — — — — — — — FLTBIP<2:0> 0000 0000 0000 0100
Preliminary
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
NVMADR Reg EA
Using
NVMADR 1/0 NVMADRU Reg
Addressing
8 bits 16 bits
Working Reg EA
Byte
User/Configuration Select
Space Select 24-bit EA
Note: In Example 6-2, the contents of the upper byte of W3 has no effect.
DS70082G-page 62
Legend: u = uninitialized bit
dsPIC30F
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Preliminary
2004 Microchip Technology Inc.
dsPIC30F
7.0 DATA EEPROM MEMORY Control bit WR initiates write operations, similar to pro-
gram Flash writes. This bit cannot be cleared, only set,
Note: This data sheet summarizes features of this group in software. This bit is cleared in hardware at the com-
of dsPIC30F devices and is not intended to be a complete pletion of the write operation. The inability to clear the
reference source. For more information on the CPU,
peripherals, register descriptions and general device
WR bit in software prevents the accidental or
functionality, refer to the dsPIC30F Family Reference premature termination of a write operation.
Manual (DS70046). For more information on the device The WREN bit, when set, will allow a write operation.
instruction set and programming, refer to the dsPIC30F
Programmer’s Reference Manual (DS70030). On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
The Data EEPROM Memory is readable and writable Reset, or a WDT Time-out Reset, during normal oper-
during normal operation over the entire VDD range. The ation. In these situations, following Reset, the user can
data EEPROM memory is directly mapped in the check the WRERR bit and rewrite the location. The
program memory address space. address register NVMADR remains unchanged.
The four SFRs used to read and write the program Note: Interrupt flag bit NVMIF in the IFS0 regis-
Flash memory are used to access data EEPROM ter is set when write is complete. It must be
memory, as well. As described in Section 4.0, these cleared in software.
registers are:
• NVMCON 7.1 Reading the Data EEPROM
• NVMADR
A TBLRD instruction reads a word at the current pro-
• NVMADRU
gram word address. This example uses W0 as a
• NVMKEY pointer to data EEPROM. The result is placed in
The EEPROM data memory allows read and write of register W4, as shown in Example 7-1.
single words and 16-word blocks. When interfacing to
data memory, NVMADR, in conjunction with the EXAMPLE 7-1: DATA EEPROM READ
NVMADRU register, is used to address the EEPROM MOV #LOW_ADDR_WORD,W0 ; Init Pointer
location being accessed. TBLRDL and TBLWTL instruc- MOV #HIGH_ADDR_WORD,W1
tions are used to read and write data EEPROM. The MOV W1,TBLPAG
dsPIC30F devices have up to 8 Kbytes (4K words) of TBLRDL [ W0 ], W4 ; read data EEPROM
data EEPROM, with an address range from 0x7FF000
to 0x7FFFFE.
A word write operation should be preceded by an erase
of the corresponding memory location(s). The write
typically requires 2 ms to complete, but the write time
will vary with voltage and temperature.
A program or erase operation on the data EEPROM
does not stop the instruction flow. The user is respon-
sible for waiting for the appropriate duration of time
before initiating another data EEPROM write/erase
operation. Attempting to read the data EEPROM while
a programming or erase operation is in progress results
in unspecified data.
8.1 Parallel I/O (PIO) Ports When a pin is shared with another peripheral or func-
tion that is defined as an input only, it is nevertheless
When a peripheral is enabled and the peripheral is regarded as a dedicated port because there is no
actively driving an associated pin, the use of the pin as other competing source of outputs. An example is the
a general purpose output pin is disabled. The I/O pin INT4 pin.
may be read, but the output driver for the parallel port The format of the registers for PORTA are shown in
bit will be disabled. If a peripheral is enabled, but the Table 8-1.
peripheral is not actively driving a pin, that pin may be
driven by a port. The TRISA (Data Direction Control) register controls
the direction of the RA<7:0> pins, as well as the INTx
pins and the VREF pins. The LATA register supplies
data to the outputs, and is readable/writable. Reading
the PORTA register yields the state of the input pins,
while writing the PORTA register modifies the contents
of the LATA register.
Read TRIS
I/O Cell
TRIS Latch
Data Bus D Q
WR TRIS CK
Data Latch
D Q I/O Pad
WR LAT +
CK
WR Port
Read LAT
Read Port
PIO Module 1
Output Data
0
Read TRIS
I/O Pad
Data Bus D Q
WR TRIS CK
TRIS Latch
D Q
WR LAT +
WR Port CK
Data Latch
Read LAT
Input Data
Read Port
Preliminary
TABLE 8-4: PORTD REGISTER MAP
SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name
TRISD 02D2 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111
PORTD 02D4 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0000 0000 0000 0000
LATD 02D6 LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 0000 0000 0000 0000
Legend: u = uninitialized bit
DS70082G-page 69
dsPIC30F
TABLE 8-6: PORTF REGISTER MAP
SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name
TRISF 02EE — — — — — — — TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 0000 0001 1111 1111
PORTF 02E0 — — — — — — — RF8 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 0000 0000 0000 0000
LATF 02E2 — — — — — — — LATF8 LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 0000 0000 0000 0000
DS70082G-page 70
Legend: u = uninitialized bit
dsPIC30F
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Preliminary
2004 Microchip Technology Inc.
dsPIC30F
8.3 Input Change Notification Module
The Input Change Notification module provides the
dsPIC30F devices the ability to generate interrupt
requests to the processor in response to a change-of-
state on selected input pins. This module is capable of
detecting input change-of-states even in Sleep mode,
when the clocks are disabled. There are up to 22 exter-
nal signals (CN0 through CN21) that may be selected
(enabled) for generating an interrupt request on a
change-of-state.
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
PR1
Equal
Comparator x 16 TSYNC
1 Sync
(3)
TMR1
Reset
0
0
T1IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
SOSCO/ TON 2
1X
T1CK
SOSCI
TCY 00
Enabling LPOSCEN (OSCCON<1>) will disable the Enabling an interrupt is accomplished via the respec-
normal Timer and Counter modes and enable a timer tive timer interrupt enable bit, T1IE. The Timer interrupt
carry-out wake-up event. enable bit is located in the IEC0 control register in the
Interrupt Controller.
When the CPU enters Sleep mode, the RTC will con-
tinue to operate, provided the 32 kHz external crystal
oscillator is active and the control bits have not been
changed. The TSIDL bit should be cleared to ‘0’ in
order for RTC to continue operation in Idle mode.
DS70082G-page 76
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
dsPIC30F
Preliminary
2004 Microchip Technology Inc.
dsPIC30F
10.0 TIMER2/3 MODULE 16-bit Mode: In the 16-bit mode, Timer2 and Timer3
can be configured as two independent 16-bit timers.
Note: This data sheet summarizes features of this group Each timer can be set up in either 16-bit Timer mode or
of dsPIC30F devices and is not intended to be a complete 16-bit Synchronous Counter mode. See Section 9.0,
reference source. For more information on the CPU,
peripherals, register descriptions and general device
Timer1 Module, for details on these two operating
functionality, refer to the dsPIC30F Family Reference modes.
Manual (DS70046). The only functional difference between Timer2 and
This section describes the 32-bit General Purpose Timer3 is that Timer2 provides synchronization of the
(GP) Timer module (Timer2/3) and associated opera- clock prescaler output. This is useful for high frequency
tional modes. Figure 10-1 depicts the simplified block external clock inputs.
diagram of the 32-bit Timer2/3 module. Figure 10-2 32-bit Timer Mode: In the 32-bit Timer mode, the timer
and Figure 10-3 show Timer2/3 configured as two increments on every instruction cycle up to a match
independent 16-bit timers; Timer2 and Timer3, value, preloaded into the combined 32-bit period regis-
respectively. ter PR3/PR2, then resets to 0 and continues to count.
The Timer2/3 module is a 32-bit timer, which can be For synchronous 32-bit reads of the Timer2/Timer3
configured as two 16-bit timers, with selectable operat- pair, reading the LS word (TMR2 register) will cause
ing modes. These timers are utilized by other the MS word to be read and latched into a 16-bit
peripheral modules such as: holding register, termed TMR3HLD.
• Input Capture For synchronous 32-bit writes, the holding register
• Output Compare/Simple PWM (TMR3HLD) must first be written to. When followed by
The following sections provide a detailed description, a write to the TMR2 register, the contents of TMR3HLD
including setup and control registers, along with asso- will be transferred and latched into the MSB of the
ciated block diagrams for the operational modes of the 32-bit timer (TMR3).
timers. 32-bit Synchronous Counter Mode: In the 32-bit
The 32-bit timer has the following modes: Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal,
• Two independent 16-bit timers (Timer2 and which is synchronized with the internal phase clocks.
Timer3) with all 16-bit operating modes (except The timer counts up to a match value preloaded in the
Asynchronous Counter mode) combined 32-bit period register PR3/PR2, then resets
• Single 32-bit Timer operation to ‘0’ and continues.
• Single 32-bit Synchronous Counter When the timer is configured for the Synchronous
Further, the following operational characteristics are Counter mode of operation and the CPU goes into the
supported: Idle mode, the timer will stop incrementing, unless the
TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer
• ADC Event Trigger
module logic will resume the incrementing sequence
• Timer Gate Operation upon termination of the CPU Idle mode.
• Selectable Prescaler Settings
Note: In some devices, one or more of the TxCK
• Timer Operation during Idle and Sleep modes
pins may be absent. For these timers
• Interrupt on a 32-bit Period Register Match without the external clock input pin, the
These operating modes are determined by setting the following modes should not be used:
appropriate bit(s) in the 16-bit T2CON and T3CON 1. TCS = 1 (16-bit counter)
SFRs. 2. TCS = 0, TGATE = 1 (gated time
For 32-bit timer/counter operation, Timer2 is the LS accumulation.
Word and Timer3 is the MS Word of the 32-bit timer.
Note: For 32-bit timer operation, T3CON control
bits are ignored. Only T2CON control bits
are used for setup and control. Timer 2
clock and gate inputs are utilized for the
32-bit timer module, but an interrupt is
generated with the Timer3 interrupt flag
(T3IF) and the interrupt is enabled with the
Timer3 interrupt enable bit (T3IE).
TMR3HLD
16
16
Write TMR2
Read TMR2
16
Reset
TMR3 TMR2 Sync
MSB LSB
ADC Event Trigger
Comparator x 32
Equal
PR3 PR2
0
T3IF
Event Flag 1 Q D TGATE(T2CON<6>)
Q CK
TGATE
(T2CON<6>)
TGATE
TCS
TCKPS<1:0>
TON 2
T2CK 1X
Prescaler
Gate 1, 8, 64, 256
Sync 01
TCY
00
Note: Timer configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation. All control
bits are respective to the T2CON register.
PR2
Equal
Comparator x 16
TMR2 Sync
Reset
0
T2IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
TON 2
T2CK 1X
Gate Prescaler
Sync 01 1, 8, 64, 256
TCY 00
PR3
TMR3
Reset
0
T3IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
TON 2
T3CK Sync 1X
Prescaler
01 1, 8, 64, 256
TCY 00
Preliminary
DS70082G-page 81
dsPIC30F
dsPIC30F
NOTES:
TMR5HLD
16
16
Write TMR4
Read TMR4
16
Reset
TMR5 TMR4 Sync
MSB LSB
Comparator x 32
Equal
PR5 PR4
0
T5IF
Event Flag
1 Q D TGATE(T4CON<6>)
Q CK
TGATE
(T4CON<6>)
TGATE
TCS
TCKPS<1:0>
TON 2
T4CK 1X
Prescaler
Gate 1, 8, 64, 256
Sync 01
TCY 00
Note: Timer configuration bit T32, T4CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control
bits are respective to the T4CON register.
PR4
Equal
Comparator x 16
TMR4 Sync
Reset
0
T4IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
TON 2
T4CK 1X
Gate Prescaler
Sync 01 1, 8, 64, 256
TCY 00
PR5
TMR5
Reset
0
T5IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
TON 2
T5CK Sync 1X
Prescaler
01 1, 8, 64, 256
TCY 00
Preliminary
DS70082G-page 85
dsPIC30F
dsPIC30F
NOTES:
16 16
ICx ICTMR
Pin 1 0
Edge FIFO
Prescaler Clock Detection R/W
1, 4, 16 Synchronizer Logic Logic
3 ICM<2:0> ICxBUF
Mode Select
ICBNE, ICOV
ICI<1:0>
Interrupt
ICxCON Logic
Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input
capture channels 1 through N.
IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
DS70082G-page 90
IC2CON 0146 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>
IC3BUF 0148 Input 3 Capture Register uuuu uuuu uuuu uuuu
IC3CON 014A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
dsPIC30F
IC4CON 014E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC5CON 0152 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC6CON 0156 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC7CON 015A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC8CON 015E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Preliminary
2004 Microchip Technology Inc.
dsPIC30F
13.0 OUTPUT COMPARE MODULE The key operational features of the Output Compare
module include:
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
• Timer2 and Timer3 Selection mode
reference source. For more information on the CPU, • Simple Output Compare Match mode
peripherals, register descriptions and general device • Dual Output Compare Match mode
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046). • Simple PWM mode
• Output Compare during Sleep and Idle modes
This section describes the Output Compare module
and associated operational modes. The features pro- • Interrupt on Output Compare/PWM Event
vided by this module are useful in applications requiring These operating modes are determined by setting the
operational modes such as: appropriate bits in the 16-bit OCxCON SFR (where x =
• Generation of Variable Width Output Pulses 1,2,3,...,N). The dsPIC devices contain up to 8
compare channels, (i.e., the maximum value of N is 8).
• Power Factor Correction
OCxRS and OCxR in the figure represent the Dual
Figure 13-1 depicts a block diagram of the Output
Compare registers. In the dual compare mode, the
Compare module.
OCxR register is used for the first compare and OCxRS
is used for the second compare.
OCxRS
3 Output Enable
OCM<2:0>
Comparator Mode Select OCFA
(for x = 1, 2, 3 or 4)
OCTSEL
0 1 0 1 or OCFB
(for x = 5, 6, 7 or 8)
Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels 1 through N.
13.3 Dual Output Compare Match Mode The user must perform the following steps in order to
configure the output compare module for PWM
When control bits OCM<2:0> (OCxCON<2:0>) = 100 operation:
or 101, the selected output compare channel is config-
1. Set the PWM period by writing to the appropriate
ured for one of two Dual Output Compare modes,
period register.
which are:
2. Set the PWM duty cycle by writing to the OCxRS
• Single Output Pulse mode register.
• Continuous Output Pulse mode 3. Configure the output compare module for PWM
operation.
13.3.1 SINGLE PULSE MODE
4. Set the TMRx prescale value and enable the
For the user to configure the module for the generation Timer, TON (TxCON<15>) = 1.
of a single output pulse, the following steps are
required (assuming timer is off): 13.4.1 INPUT PIN FAULT PROTECTION
• Determine instruction cycle time TCY. FOR PWM
• Calculate desired pulse width value based on TCY. When control bits OCM<2:0> (OCxCON<2:0>) = 111,
• Calculate time to start pulse from timer start value the selected output compare channel is again config-
of 0x0000. ured for the PWM mode of operation, with the addi-
• Write pulse width start and stop times into OCxR tional feature of input fault protection. While in this
and OCxRS compare registers (x denotes mode, if a logic 0 is detected on the OCFA/B pin, the
channel 1, 2, ...,N). respective PWM output pin is placed in the high imped-
ance input state. The OCFLT bit (OCxCON<4>) indi-
• Set timer period register to value equal to, or
cates whether a FAULT condition has occurred. This
greater than, value in OCxRS compare register.
state will be maintained until both of the following
• Set OCM<2:0> = 100. events have occurred:
• Enable timer, TON (TxCON<15>) = 1.
• The external FAULT condition has been removed.
To initiate another single pulse, issue another write to • The PWM mode has been re-enabled by writing
set OCM<2:0> = 100. to the appropriate control bits.
Duty Cycle
DS70082G-page 94
OC2R 0188 Output Compare 2 Main Register 0000 0000 0000 0000
OC2CON 018A — — OCSIDL — — — — — — — — OCFLT OCTSE OCM<2:0> 0000 0000 0000 0000
dsPIC30F
OC3RS 018C Output Compare 3 Secondary Register 0000 0000 0000 0000
OC3R 018E Output Compare 3 Main Register 0000 0000 0000 0000
OC3CON 0190 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC4RS 0192 Output Compare 4 Secondary Register 0000 0000 0000 0000
OC4R 0194 Output Compare 4 Main Register 0000 0000 0000 0000
OC4CON 0196 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC5RS 0198 Output Compare 5 Secondary Register 0000 0000 0000 0000
OC5R 019A Output Compare 5 Main Register 0000 0000 0000 0000
OC5CON 019C — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC6RS 019E Output Compare 6 Secondary Register 0000 0000 0000 0000
OC6R 01A0 Output Compare 6 Main Register 0000 0000 0000 0000
OC6CON 01A2 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC7RS 01A4 Output Compare 7 Secondary Register 0000 0000 0000 0000
OC7R 01A6 Output Compare 7 Main Register 0000 0000 0000 0000
Preliminary
OC7CON 01A8 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC8RS 01AA Output Compare 8 Secondary Register 0000 0000 0000 0000
OC8R 01AC Output Compare 8 Main Register 0000 0000 0000 0000
OC8CON 01AE — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
TQCKPS<1:0>
Sleep Input TQCS
2
TCY
0
Synchronize
Prescaler
Det 1 1, 8, 64, 256
1
QEIM<2:0>
0
QEIIF
D Q Event
TQGATE
CK Q Flag
Programmable
QEB
Digital Filter
Programmable
INDX
Digital Filter
PCDOUT
UPDN
Up/Down
1
Note: The control bits in the DFLTCON register may vary depending on the device that is selected. See the dsPIC30F Family Reference Manual (DS70046) and the
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Preliminary
DS70082G-page 99
dsPIC30F
dsPIC30F
NOTES:
PWMCON1
PWM Enable and Mode SFRs
PWMCON2
DTCON2
FLTBCON
PWM Manual
OVDCON
Control SFR
PWM Generator #4
PDC4 Buffer
16-bit Data Bus
PDC4
PWM Generator
#1 Channel 1 Dead-Time PWM1H
Generator and
PTPER Buffer Override Logic PWM1L
PTCON FLTA
FLTB
SEVTCMP PTDIR
Note: Details of PWM Generator #1, #2, and #3 not shown for clarity.
PWMCON1
PWM Enable and Mode SFRs
PWMCON2
PWM Manual
OVDCON
Control SFR
PWM Generator #3
PDC3 Buffer
16-bit Data Bus
PDC3
Comparator
PWM Generator
Channel 1 Dead-Time PWM1H
#1 Generator and
PTPER Override Logic PWM1L
FLTA
PTPER Buffer
PTCON
SEVTCMP PTDIR
Note: If the period register is set to 0x0000, the 15.1.3 CONTINUOUS UP/DOWN
timer will stop counting, and the interrupt COUNTING MODES
and the special event trigger will not be
generated, even if the special event value In the Continuous Up/Down Counting modes, the PWM
is also 0x0000. The module will not time base counts upwards until the value in the PTPER
update the period register, if it is already at register is matched. The timer will begin counting
0x0000; therefore, the user must disable downwards on the following input clock edge. The
the module in order to update the period PTDIR bit in the PTCON SFR is read only and indicates
register. the counting direction The PTDIR bit is set when the
timer counts downwards.
The PWM time base can be configured for four different
modes of operation: In the Up/Down Counting mode (PTMOD<1:0> = 10),
an interrupt event is generated each time the value of
• Free Running mode the PTMR register becomes zero and the PWM time
• Single Shot mode base begins to count upwards. The postscaler selec-
• Continuous Up/Down Count mode tion bits may be used in this mode of the timer to reduce
• Continuous Up/Down Count mode with interrupts the frequency of the interrupt events.
for double updates
15.1.4 DOUBLE UPDATE MODE
These four modes are selected by the PTMOD<1:0>
bits in the PTCON SFR. The Up/Down Counting modes In the Double Update mode (PTMOD<1:0> = 11), an
support center aligned PWM generation. The Single interrupt event is generated each time the PTMR regis-
Shot mode allows the PWM module to support pulse ter is equal to zero, as well as each time a period match
control of certain Electronically Commutative Motors occurs. The postscaler selection bits have no effect in
(ECMs). this mode of the timer.
The interrupt signals generated by the PWM time base The Double Update mode provides two additional func-
depend on the mode selection bits (PTMOD<1:0>) and tions to the user. First, the control loop bandwidth is
the postscaler bits (PTOPS<3:0>) in the PTCON SFR. doubled because the PWM duty cycles can be
updated, twice per period. Second, asymmetrical cen-
15.1.1 FREE RUNNING MODE ter-aligned PWM waveforms can be generated, which
are useful for minimizing output waveform distortion in
In the Free Running mode, the PWM time base counts certain motor control applications.
upwards until the value in the Time Base Period regis-
ter (PTPER) is matched. The PTMR register is reset on Note: Programming a value of 0x0001 in the
period register could generate a continu-
ous interrupt pulse, and hence, must be
avoided.
TCY • (PTPER + 1)
TPWM =
(PTMR Prescale Value) 15.4 Center Aligned PWM
Center aligned PWM signals are produced by the mod-
Note: PWM period will be twice the value provided ule when the PWM time base is configured in an Up/
by this equation when using center aligned modes. Down Counting mode (see Figure 15-4).
The PWM compare output is driven to the active state
If the PWM time base is configured for one of the Up/ when the value of the duty cycle register matches the
Down Count modes, the PWM period will be twice the value of PTMR and the PWM time base is counting
value provided by Equation 15-1. downwards (PTDIR = 1). The PWM compare output is
driven to the inactive state when the PWM time base is
counting upwards (PTDIR = 0) and the value in the
PTMR register matches the duty cycle value.
PWMxH
PWMxL
15.8 Independent PWM Output In the Independent mode, each duty cycle generator is
connected to both of the PWM I/O pins in an output
An independent PWM Output mode is required for driv- pair. By using the associated duty cycle register and
ing certain types of loads. A particular PWM output pair the appropriate bits in the OVDCON register, the user
is in the Independent Output mode when the corre- may select the following signal output options for each
sponding PMOD bit in the PWMCON1 register is set. PWM I/O pin operating in the Independent mode:
No dead-time control is implemented between adjacent
PWM I/O pins when the module is operating in the • I/O pin outputs PWM signal
Independent mode and both I/O pins are allowed to be • I/O pin inactive
active simultaneously. • I/O pin active
15.13 PWM Update Lockout 15.15 PWM Operation During CPU Sleep
For a complex PWM application, the user may need to Mode
write up to four duty cycle registers and the time base
The FAULT A and FAULT B input pins have the ability
period register, PTPER, at a given time. In some appli-
to wake the CPU from Sleep mode. The PWM module
cations, it is important that all buffer registers be written
generates an interrupt if either of the FAULT pins is
before the new duty cycle and period values are loaded
driven low while in Sleep.
for use by the module.
The PWM update lockout feature is enabled by setting 15.16 PWM Operation During CPU Idle
the UDIS control bit in the PWMCON2 SFR. The UDIS
bit affects all duty cycle buffer registers and the PWM
Mode
time base period buffer, PTPER. No duty cycle The PTCON SFR contains a PTSIDL control bit. This
changes or period value changes will have effect while bit determines if the PWM module will continue to
UDIS = 1. operate or stop when the device enters Idle mode. If
PTSIDL = 0, the module will continue to operate. If
PTSIDL = 1, the module will stop operation as long as
the CPU remains in Idle mode.
DS70082G-page 110
PWMCON1 01C8 — — — — PTMOD4 PTMOD3 PTMOD2 PTMOD1 PEN4H PEN3H PEN2H PEN1H PEN4L PEN3L PEN2L PEN1L 0000 0000 1111 1111
PWMCON2 01CA — — — — SEVOPS<3:0> — — — — — — OSYNC UDIS 0000 0000 0000 0000
dsPIC30F
DTCON1 01CC DTBPS<1:0> Dead-Time B Value DTAPS<1:0> Dead-Time A Value 0000 0000 0000 0000
DTCON2 01CE — — — — — — — — DTS4A DTS4I DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I 0000 0000 0000 0000
FLTACON 01D0 FAOV4H FAOV4L FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM — — — FAEN4 FAEN3 FAEN2 FAEN1 0000 0000 0000 0000
FLTBCON 01D2 FBOV4H FBOV4L FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L FLTBM — — — FBEN4 FBEN3 FBEN2 FBEN1 0000 0000 0000 0000
OVDCON 01D4 POVD4H POVD4L POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L POUT4H POUT4L POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L 1111 1111 0000 0000
PDC1 01D6 PWM Duty Cycle #1 Register 0000 0000 0000 0000
PDC2 01D8 PWM Duty Cycle #2 Register 0000 0000 0000 0000
PDC3 01DA PWM Duty Cycle #3 Register 0000 0000 0000 0000
PDC4 01DC PWM Duty Cycle #4 Register 0000 0000 0000 0000
Legend: u = uninitialized bit
Preliminary
PTMR 01C2 PTDIR PWM Timer Count Value
PTPER 01C4 — PWM Time Base Period Register 0000 0000 0000 0000
SEVTCMP 01C6 SEVTDIR PWM Special Event Compare Register 0000 0000 0000 0000
PWMCON1 01C8 — — — — — PTMOD3 PTMOD2 PTMOD1 — PEN3H PEN2H PEN1H — PEN3L PEN2L PEN1L 0000 0000 0111 0111
PWMCON2 01CA — — — — SEVOPS<3:0> — — — — — — OSYNC UDIS 0000 0000 0000 0000
DTCON1 01CC — — — — — — — — DTAPS<1:0> Dead-Time A Value 0000 0000 0000 0000
FLTACON 01D0 — — FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM — — — — FAEN3 FAEN2 FAEN1 0000 0000 0000 0000
OVDCON 01D4 — — POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L — — POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L 0011 1111 0000 0000
PDC1 01D6 PWM Duty Cycle #1 Register 0000 0000 0000 0000
PDC2 01D8 PWM Duty Cycle #2 Register 0000 0000 0000 0000
PDC3 01DA PWM Duty Cycle #3 Register 0000 0000 0000 0000
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
SPIxBUF SPIxBUF
Receive Transmit
SPIxSR
SDIx bit0
SDOx Shift
clock
SS & FSYNC Clock Edge
Control Select
SSx Control
Secondary Primary
Prescaler Prescaler FCY
1,2,4,6,8 1, 4, 16, 64
SCKx
Note: x = 1 or 2.
SDOx SDIy
Note: x = 1 or 2, y = 1 or 2.
DS70082G-page 114
dsPIC30F
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Preliminary
2004 Microchip Technology Inc.
dsPIC30F
17.0 I2C MODULE 17.1 Operating Function Description
Note: This data sheet summarizes features of this group The hardware fully implements all the master and slave
of dsPIC30F devices and is not intended to be a complete functions of the I2C Standard and Fast mode specifica-
reference source. For more information on the CPU, tions, as well as 7 and 10-bit addressing.
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference Thus, the I2C module can operate either as a slave or
Manual (DS70046). a master on an I2C bus.
The Inter-Integrated Circuit (I2C) module provides
17.1.1 VARIOUS I2C MODES
complete hardware support for both Slave and Multi-
Master modes of the I2C serial communication The following types of I2C operation are supported:
standard, with a 16-bit interface. • I2C Slave operation with 7-bit address
This module offers the following key features: • I2C Slave operation with 10-bit address
• I2C interface supporting both Master and Slave • I2C Master operation with 7 or 10-bit address
operation. See the I2C programmer’s model in Figure 17-1.
• I2C Slave mode supports 7 and 10-bit address.
• I2C Master mode supports 7 and 10-bit address. 17.1.2 PIN CONFIGURATION IN I2C MODE
• I2C port allows bi-directional transfers between I2C has a 2-pin interface; pin SCL is clock and pin SDA
master and slaves. is data.
• Serial clock synchronization for I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
• I2C supports Multi-Master operation; detects bus
collision and will arbitrate accordingly.
I2CRCV (8 bits)
bit 7 bit 0
I2CTRN (8 bits)
bit 7 bit 0
I2CBRG (9 bits)
bit 8 bit 0
I2CCON (16-bits)
bit 15 bit 0
I2CSTAT (16-bits)
bit 15 bit 0
I2CADD (10-bits)
bit 9 bit 0
17.1.3 I2C REGISTERS The I2CADD register holds the slave address. A status
bit, ADD10, indicates 10-bit Address mode. The
I2CCON and I2CSTAT are control and status registers,
I2CBRG acts as the baud rate generator reload value.
respectively. The I2CCON register is readable and writ-
able. The lower 6 bits of I2CSTAT are read only. The In receive operations, I2CRSR and I2CRCV to-
remaining bits of the I2CSTAT are read/write. gether form a double buffered receiver. When
I2CRSR receives a complete byte, it is transferred to
I2CRSR is the shift register used for shifting data,
I2CRCV and an interrupt pulse is generated. During
whereas I2CRCV is the buffer register to which data
transmission, the I2CTRN is not double buffered.
bytes are written, or from which data bytes are read.
I2CRCV is the receive buffer, as shown in Figure 16-1. Note: Following a Restart condition in 10-bit
I2CTRN is the transmit register to which bytes are writ- mode, the user only needs to match the
ten during a transmit operation, as shown in Figure 16-2. first 7-bit address.
Internal
Data Bus
I2CRCV
Read
Shift
SCL Clock
I2CRSR
LSB
SDA Addr_Match
Match Detect
Write
I2CADD
Read
Start and
Stop bit Detect
Write
I2CSTAT
Start, Restart,
Stop bit Generate
Read
Control Logic
Collision
Detect
Write
I2CCON
Acknowledge
Read
Generation
Clock
Stretching Write
I2CTRN
Shift LSB Read
Clock
Reload
Control Write
Preliminary
DS70082G-page 121
dsPIC30F
dsPIC30F
NOTES:
Write Write
– Control TSR
– Control Buffer
– Generate Flags
– Generate Interrupt
Load TSR
UxTXIF
UTXBRK
Data
Transmit Shift Register (UxTSR)
‘0’ (Start)
UxTX
‘1’ (Stop)
Control
Signals
Note: x = 1 or 2.
UxMODE UxSTA
LPBACK 8-9
From UxTX
1 Load RSR
to Buffer Control
FERR
PERR
Receive Shift Register Signals
UxRX
0 (UxRSR)
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Preliminary
DS70082G-page 129
dsPIC30F
dsPIC30F
NOTES:
Acceptance Mask
BUFFERS RXM1
Acceptance Filter
RXF2
MESSAGE
MESSAGE
MTXBUFF
MTXBUFF
MTXBUFF
MSGREQ
MSGREQ
MSGREQ
TXLARB
TXLARB
TXLARB
c RXF0 RXF4 p
TXERR
TXERR
TXERR
TXABT
TXABT
TXABT
e t
Acceptance Filter Acceptance Filter
p
RXF1 RXF5
t
R R
X Identifier M Identifier X
Message B A B
Queue 0 B 1
Control
Transmit Byte Sequencer Data Field Data Field
Receive RERRCNT
Error
Counter
PROTOCOL TERRCNT
Protocol
Finite
CRC Generator CRC Check
State
Machine
Bit
Transmit
Timing Bit Timing
Logic
Logic Generator
CiTX(1) CiRX(1)
Input Signal
Sample Point
TQ
19.6.6 SYNCHRONIZATION
19.6.3 PROPAGATION SEGMENT
To compensate for phase shifts between the oscillator
This part of the bit time is used to compensate physical frequencies of the different bus stations, each CAN
delay times within the network. These delay times con- controller must be able to synchronize to the relevant
sist of the signal propagation time on the bus line and signal edge of the incoming signal. When an edge in
the internal delay time of the nodes. The Propagation the transmitted data is detected, the logic will compare
Segment can be programmed from 1 TQ to 8 TQ by the location of the edge to the expected time (Synchro-
setting the PRSEG<2:0> bits (CiCFG2<2:0>). nous Segment). The circuit will then adjust the values
of Phase1 Seg and Phase2 Seg. There are 2
19.6.4 PHASE SEGMENTS mechanisms used to synchronize.
The phase segments are used to optimally locate the
sampling of the received bit within the transmitted bit 19.6.6.1 Hard Synchronization
time. The sampling point is between Phase1 Seg and Hard Synchronization is only done whenever there is a
Phase2 Seg. These segments are lengthened or short- 'recessive' to 'dominant' edge during Bus Idle, indicat-
ened by re-synchronization. The end of the Phase1 ing the start of a message. After hard synchronization,
Seg determines the sampling point within a bit period. the bit time counters are restarted with the Synchro-
The segment is programmable from 1 TQ to 8 TQ. nous Segment. Hard synchronization forces the edge
Phase2 Seg provides delay to the next transmitted data which has caused the hard synchronization to lie within
transition. The segment is programmable from 1 TQ to the synchronization segment of the restarted bit time. If
8 TQ, or it may be defined to be equal to the greater of a hard synchronization is done, there will not be a
Phase1 Seg or the Information Processing Time re-synchronization within that bit time.
(2 TQ). The Phase1 Seg is initialized by setting bits
SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is ini- 19.6.6.2 Re-synchronization
tialized by setting SEG2PH<2:0> (CiCFG2<10:8>).
As a result of re-synchronization, Phase1 Seg may be
The following requirement must be fulfilled while setting lengthened or Phase2 Seg may be shortened. The
the lengths of the Phase Segments: amount of lengthening or shortening of the phase
• Propagation Segment + Phase1 Seg > = Phase2 buffer segment has an upper bound known as the Syn-
Seg chronization Jump Width, and is specified by the
SJW<1:0> bits (CiCFG1<7:6>). The value of the syn-
chronization jump width will be added to Phase1 Seg or
subtracted from Phase2 Seg. The re-synchronization
jump width is programmable between 1 TQ and 4 TQ.
The following requirement must be fulfilled while setting
the SJW<1:0> bits:
• Phase2 Seg > Synchronization Jump Width
DS70082G-page 138
C1RXF1EIDH 030A — — — — Receive Acceptance Filter 1 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXF1EIDL 030C Receive Acceptance Filter 1 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
dsPIC30F
C1RXF2SID 0310 — — — Receive Acceptance Filter 2 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF2EIDH 0312 — — — — Receive Acceptance Filter 2 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXF2EIDL 0314 Receive Acceptance Filter 2 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXF3SID 0318 — — — Receive Acceptance Filter 3 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF3EIDH 031A — — — — Receive Acceptance Filter 3 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXF3EIDL 031C Receive Acceptance Filter 3 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXF4SID 0320 — — — Receive Acceptance Filter 4 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF4EIDH 0322 — — — — Receive Acceptance Filter 4 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXF4EIDL 0324 Receive Acceptance Filter 4 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXF5SID 0328 — — — Receive Acceptance Filter 5 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF5EIDH 032A — — — — Receive Acceptance Filter 5 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXF5EIDL 032C Receive Acceptance Filter 5 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXM0SID 0330 — — — Receive Acceptance Mask 0 Standard Identifier <10:0> — MIDE 000u uuuu uuuu uu0u
C1RXM0EIDH 0332 — — — — Receive Acceptance Mask 0 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
Preliminary
C1RXM0EIDL 0334 Receive Acceptance Mask 0 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXM1SID 0338 — — — Receive Acceptance Mask 1 Standard Identifier <10:0> — MIDE 000u uuuu uuuu uu0u
C1RXM1EIDH 033A — — — — Receive Acceptance Mask 1 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXM1EIDL 033C Receive Acceptance Mask 1 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1TX2SID 0340 Transmit Buffer 2 Standard Identifier <10:6> — — — Transmit Buffer 2 Standard Identifier <5:0> SRR TXIDE uuuu u000 uuuu uuuu
C1TX2EID 0342 Transmit Buffer 2 Extended Identifier <17:14> — — — — Transmit Buffer 2 Extended Identifier <13:6> uuuu 0000 uuuu uuuu
C1TX2DLC 0344 Transmit Buffer 2 Extended Identifier <5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000
C1TX2B1 0346 Transmit Buffer 2 Byte 1 Transmit Buffer 2 Byte 0 uuuu uuuu uuuu uuuu
C1TX2B2 0348 Transmit Buffer 2 Byte 3 Transmit Buffer 2 Byte 2 uuuu uuuu uuuu uuuu
C1TX2B3 034A Transmit Buffer 2 Byte 5 Transmit Buffer 2 Byte 4 uuuu uuuu uuuu uuuu
C1TX2B4 034C Transmit Buffer 2 Byte 7 Transmit Buffer 2 Byte 6 uuuu uuuu uuuu uuuu
C1TX2CON 034E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000
C1TX1SID 0350 Transmit Buffer 1 Standard Identifier <10:6> — — — Transmit Buffer 1 Standard Identifier <5:0> SRR TXIDE uuuu u000 uuuu uuuu
C1TX1EID 0352 Transmit Buffer 1 Extended Identifier <17:14> — — — — Transmit Buffer 1 Extended Identifier <13:6> uuuu 0000 uuuu uuuu
C1TX1DLC 0354 Transmit Buffer 1 Extended Identifier <5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000
C1TX1B1 0356 Transmit Buffer 1 Byte 1 Transmit Buffer 1 Byte 0 uuuu uuuu uuuu uuuu
Legend: u = uninitialized bit
Preliminary
C1RX0EID 0382 — — — — Receive Buffer 0 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RX0DLC 0384 Receive Buffer 0 Extended Identifier <5:0> RXRTR RXRB1 — — — RXRB0 DLC<3:0> uuuu uuuu 000u uuuu
C1RX0B1 0386 Receive Buffer 0 Byte 1 Receive Buffer 0 Byte 0 uuuu uuuu uuuu uuuu
C1RX0B2 0388 Receive Buffer 0 Byte 3 Receive Buffer 0 Byte 2 uuuu uuuu uuuu uuuu
C1RX0B3 038A Receive Buffer 0 Byte 5 Receive Buffer 0 Byte 4 uuuu uuuu uuuu uuuu
C1RX0B4 038C Receive Buffer 0 Byte 7 Receive Buffer 0 Byte 6 uuuu uuuu uuuu uuuu
C1RX0CON 038E — — — — — — — — RXFUL — — — RXRTRRO DBEN JTOFF FILHIT0 0000 0000 0000 0000
C1CTRL 0390 CANCAP — CSIDLE ABAT CANCKS REQOP<2:0> OPMODE<2:0> — ICODE<2:0> — 0000 0100 1000 0000
C1CFG1 0392 — — — — — — — — SJW<1:0> BRP<5:0> 0000 0000 0000 0000
C1CFG2 0394 — WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0u00 0uuu uuuu uuuu
C1INTF 0396 RX0OVR RX1OVR TXBO TXEP RXEP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF 0000 0000 0000 0000
C1INTE 0398 — — — — — — — — IVRIE WAKIE ERRIE TX2IE TX1IE TX0IE RX1E RX0IE 0000 0000 0000 0000
C1EC 039A Transmit Error Count Register Receive Error Count Register 0000 0000 0000 0000
Legend: u = uninitialized bit
DS70082G-page 139
dsPIC30F
TABLE 19-2: CAN2 REGISTER MAP
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
C2RXF0SID 03C0 — — — Receive Acceptance Filter 0 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u
C2RXF0EIDH 03C2 — — — — Receive Acceptance Filter 0 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C2RXF0EIDL 03C4 Receive Acceptance Filter 0 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C2RXF1SID 03C8 — — — Receive Acceptance Filter 1 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u
DS70082G-page 140
C2RXF1EIDH 03CA — — — — Receive Acceptance Filter 1 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C2RXF1EIDL 03CC Receive Acceptance Filter 1 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
dsPIC30F
C2RXF2SID 03D0 — — — Receive Acceptance Filter 2 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u
C2RXF2EIDH 03D2 — — — — Receive Acceptance Filter 2 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C2RXF2EIDL 03D4 Receive Acceptance Filter 2 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C2RXF3SID 03D8 — — — Receive Acceptance Filter 3 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u
C2RXF3EIDH 03DA — — — — Receive Acceptance Filter 3 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C2RXF3EIDL 03DC Receive Acceptance Filter 3 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C2RXF4SID 03E0 — — — Receive Acceptance Filter 4 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u
C2RXF4EIDH 03E2 — — — — Receive Acceptance Filter 4 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C2RXF4EIDL 03E4 Receive Acceptance Filter 4 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C2RXF5SID 03E8 — — — Receive Acceptance Filter 5 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u
C2RXF5EIDH 03EA — — — — Receive Acceptance Filter 5 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C2RXF5EIDL 03EC Receive Acceptance Filter 5 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C2RXM0SID 03F0 — — — Receive Acceptance Mask 0 Standard Identifier <10:0> — MIDE 000u uuuu uuuu uu0u
C2RXM0EIDH 03F2 — — — — Receive Acceptance Mask 0 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
Preliminary
C2RXM0EIDL 03F4 Receive Acceptance Mask 0 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C2RXM1SID 03F8 — — — Receive Acceptance Mask 1 Standard Identifier <10:0> — MIDE 000u uuuu uuuu uu0u
C2RXM1EIDH 03FA — — — — Receive Acceptance Mask 1 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C2RXM1EIDL 03FC Receive Acceptance Mask 1 Extended Identifier <5:0> — — — — — — — — — — uuuu uu00 0000 0000
C2TX2SID 0400 Transmit Buffer 2 Standard Identifier <10:6> — — — Transmit Buffer 2 Standard Identifier <5:0> SRR TXIDE uuuu u000 uuuu uuuu
C2TX2EID 0402 Transmit Buffer 2 Extended Identifier <17:14> — — — — Transmit Buffer 2 Extended Identifier <13:6> uuuu 0000 uuuu uuuu
C2TX2DLC 0404 Transmit Buffer 2 Extended Identifier <5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000
C2TX2B1 0406 Transmit Buffer 2 Byte 1 Transmit Buffer 2 Byte 0 uuuu uuuu uuuu uuuu
C2TX2B2 0408 Transmit Buffer 2 Byte 3 Transmit Buffer 2 Byte 2 uuuu uuuu uuuu uuuu
C2TX2B3 040A Transmit Buffer 2 Byte 5 Transmit Buffer 2 Byte 4 uuuu uuuu uuuu uuuu
C2TX2B4 040C Transmit Buffer 2 Byte 7 Transmit Buffer 2 Byte 6 uuuu uuuu uuuu uuuu
C2TX2CON 040E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000
C2TX1SID 0410 Transmit Buffer 1 Standard Identifier <10:6> — — — Transmit Buffer 1 Standard Identifier <5:0> SRR TXIDE uuuu u000 uuuu uuuu
C2TX1EID 0412 Transmit Buffer 1 Extended Identifier <17:14> — — — — Transmit Buffer 1 Extended Identifier <13:6> uuuu 0000 uuuu uuuu
C2TX1DLC 0414 Transmit Buffer 1 Extended Identifier <5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000
C2TX1B1 0416 Transmit Buffer 1 Byte 1 Transmit Buffer 1 Byte 0 uuuu uuuu uuuu uuuu
C2TX1B2 0418 Transmit Buffer 1 Byte 3 Transmit Buffer 1 Byte 2 uuuu uuuu uuuu uuuu
Preliminary
C2RX0DLC 0444 Receive Buffer 0 Extended Identifier <5:0> RXRTR RXRB1 — — — RXRB0 DLC<3:0> uuuu uuuu 000u uuuu
C2RX0B1 0446 Receive Buffer 0 Byte 1 Receive Buffer 0 Byte 0 uuuu uuuu uuuu uuuu
C2RX0B2 0448 Receive Buffer 0 Byte 3 Receive Buffer 0 Byte 2 uuuu uuuu uuuu uuuu
C2RX0B3 044A Receive Buffer 0 Byte 5 Receive Buffer 0 Byte 4 uuuu uuuu uuuu uuuu
C2RX0B4 044C Receive Buffer 0 Byte 7 Receive Buffer 0 Byte 6 uuuu uuuu uuuu uuuu
C2RX0CON 044E — — — — — — — — RXFUL — — — RXRTRRO DBEN JTOFF FILHIT0 0000 0000 0000 0000
C2CTRL 0450 CANCAP — CSIDLE ABAT CANCKS REQOP<2:0> OPMODE<2:0> — ICODE<2:0> — 0000 0100 1000 0000
C2CFG1 0452 — — — — — — — — SJW<1:0> BRP<5:0> 0000 0000 0000 0000
C2CFG2 0454 WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0u00 0uuu uuuu uuuu
C2INTF 0456 RX0OVR RX1OVR TXBO TXEP RXEP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF 0000 0000 0000 0000
C2INTE 0458 — — — — — — — — IVRIE WAKIE ERRIE TX2IE TX1IE TX0IE RX1E RX0IE 0000 0000 0000 0000
C2EC 045A Transmit Error Count Register Receive Error Count Register 0000 0000 0000 0000
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
DS70082G-page 141
dsPIC30F
dsPIC30F
NOTES:
AVDD AVSS
VREF+
VREF-
AN0 AN0
AN3 +
S/H CH1 ADC
AN6 -
AN9
Format
Data
AN7 -
AN10 16-word, 10-bit
Dual Port
Buffer
Bus Interface
AN2 AN2
AN5 +
S/H CH3
AN8 - CH1,CH2,
AN11 CH3,CH0 Sample/Sequence
sample Control
AN0
AN1 input
AN2 switches Input Mux
AN3 AN3 Control
AN4 AN4
AN5 AN5
AN6 AN6
AN7 AN7
AN8 AN8
AN9 AN9
AN10 AN10
AN11 AN11
AN12 AN12
AN13 AN13
AN14 AN14
AN15 AN15 +
S/H CH0
AN1 -
Note: Input multiplexer circuit will vary depending on the device selected.
RAM Contents: d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Read to Bus:
Signed Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0
Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0
Signed Integer d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Integer 0 0 0 0 0 0 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Preliminary
ADPCFG 02A8 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
ADCSSL 02AA CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 0000 0000 0000
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
DS70082G-page 149
dsPIC30F
dsPIC30F
NOTES:
Wake-up Request
FPLL
OSC1
Primary PLL
Oscillator x4, x8, x16 PLL
OSC2
Lock COSC<1:0>
Primary Osc
NOSC<1:0>
Primary
Oscillator OSWEN
Stability Detector
Oscillator
POR Done Start-up
Timer Clock
Programmable
Switching
Secondary Osc Clock Divider System
and Control
Clock
Block
SOSCO
32 kHz LP Secondary 2
Oscillator
Oscillator
SOSCI Stability Detector
POST<1:0>
Internal Fast RC
Oscillator (FRC)
CF
Fail-Safe Clock
FCKSM<1:0> Monitor (FSCM)
2 Oscillator Trap
To Timer1
.
Note: Paths indicated by dotted lines are not available on all devices. Please refer to the specific device data
sheet for details.
Enabling the LP oscillator is controlled with two The dsPIC30F operates from the FRC oscillator when-
elements: ever the current oscillator selection control bits in the
OSCCON register (OSCCON<13:12>) are set to ‘01’.
1. The current oscillator group bits COSC<1:0>.
The four bit field specified by TUN<3:0> (OSCON
2. The LPOSCEN bit (OSCON register).
<15:14> and OSCON<11:10>) allows the user to tune
The LP oscillator is ON (even during Sleep mode) if the internal fast RC oscillator (nominal 8.0 MHz). The
LPOSCEN = 1. The LP oscillator is the device clock if: user can tune the FRC oscillator within a range of
• COSC<1:0> = 00 (LP selected as main oscillator) +10.5% (840 kHz) and -12% (960 kHz) in steps of
and 1.50% around the factory-calibrated setting, see
Table 21-3.
• LPOSCEN = 1
If OSCCON<13:12> are set to ‘11’ and FPR<3:0> are
Keeping the LP oscillator ON at all times allows for a
set to ‘0001’, ‘1010’ or ‘0011’, then a PLL multiplier of 4,
fast switch to the 32 kHz system clock for lower power
8 or 16 (respectively) is applied.
operation. Returning to the faster main oscillator will
still require a start-up time Note: When a 16x PLL is used, the FRC
frequency must not be tuned to a
frequency greater than 7.5 MHz.
RESET
Instruction
Digital
Glitch Filter
MCLR
Sleep or Idle
WDT
Module
Illegal Opcode/
Uninitialized W Register
21.3.1 POR: POWER-ON RESET The POR circuit inserts a small delay, TPOR, which is
nominally 10 µs and ensures that the device bias cir-
A power-on event will generate an internal POR pulse
cuits are stable. Furthermore, a user selected power-
when a VDD rise is detected. The Reset pulse will occur
up time-out (TPWRT) is applied. The TPWRT parameter
at the POR circuit threshold voltage (VPOR), which is
is based on device configuration bits and can be 0 ms
nominally 1.85V. The device supply voltage character-
(no delay), 4 ms, 16 ms or 64 ms. The total delay is at
istics must meet specified starting voltage and rise rate
device power-up TPOR + TPWRT. When these delays
requirements. The POR pulse will reset a POR timer
have expired, SYSRST will be negated on the next
and place the device in the Reset state. The POR also
leading edge of the Q1 clock, and the PC will jump to
selects the device clock source identified by the oscil-
the Reset vector.
lator configuration fuses.
The timing for the SYSRST signal is shown in
Figure 21-3 through Figure 21-5.
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
FIGURE 21-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
FIGURE 21-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
21.3.1.2 Operating without FSCM and PWRT FIGURE 21-6: EXTERNAL POWER-ON
If the FSCM is disabled and the Power-up Timer RESET CIRCUIT (FOR
(PWRT) is also disabled, then the device will exit rap- SLOW VDD POWER-UP)
idly from Reset on power-up. If the clock source is VDD
FRC, LPRC, EXTRC or EC, it will be active
immediately. D R
If the FSCM is disabled and the system clock has not R1
MCLR
started, the device will be in a frozen state at the Reset
vector until the system clock starts. From the user’s C dsPIC30F
perspective, the device will appear to be in Reset until
a system clock is available.
Note 1: External Power-on Reset circuit is
21.3.2 BOR: PROGRAMMABLE required only if the VDD power-up slope
BROWN-OUT RESET is too slow. The diode D helps discharge
the capacitor quickly when VDD powers
The BOR (Brown-out Reset) module is based on an down.
internal voltage reference circuit. The main purpose of
the BOR module is to generate a device Reset when a 2: R should be suitably chosen so as to
brown-out condition occurs. Brown-out conditions are make sure that the voltage drop across
generally caused by glitches on the AC mains (i.e., R does not violate the device’s electrical
missing portions of the AC cycle waveform due to bad specification.
power transmission lines or voltage sags due to exces- 3: R1 should be suitably chosen so as to
sive current draw when a large inductive load is turned limit any current flowing into MCLR from
on). external capacitor C, in the event of
The BOR module allows selection of one of the MCLR/VPP pin breakdown due to Elec-
following voltage trip points: trostatic Discharge (ESD) or Electrical
Overstress (EOS).
• 2.0V
• 2.7V
• 4.2V Note: Dedicated supervisory devices, such as
• 4.5V the MCP1XX and MCP8XX, may also be
used as an external Power-on Reset
Note: The BOR voltage trip points indicated here circuit.
are nominal values provided for design
guidance only.
When MPLAB ICD2 is selected as a Debugger, the In- 1. If EMUD/EMUC is selected as the Debug I/O pin
Circuit Debugging functionality is enabled. This func- pair, then only a 5-pin interface is required, as
tion allows simple debugging functions when used with the EMUD and EMUC pin functions are multi-
MPLAB IDE. When the device has this feature enabled, plexed with the PGD and PGC pin functions in
some of the resources are not available for general all dsPIC30F devices.
use. These resources include the first 80 bytes of Data 2. If EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/
RAM and two I/O pins. EMUC3 is selected as the Debug I/O pin pair,
then a 7-pin interface is required, as the
One of four pairs of Debug I/O pins may be selected by
EMUDx/EMUCx pin functions (x = 1, 2 or 3) are
the user using configuration options in MPLAB IDE.
not multiplexed with the PGD and PGC pin
These pin pairs are named EMUD/EMUC, EMUD1/
functions.
EMUC1, EMUD2/EMUC2 and MUD3/EMUC3.
In each case, the selected EMUD pin is the Emulation/
Debug Data line, and the EMUC pin is the Emulation/
Debug Clock line. These pins will interface to the
MPLAB ICD 2 module available from Microchip. The
selected pair of Debug I/O pins is used by MPLAB
ICD 2 to send commands and receive responses, as
well as to send and receive data. To use the In-Circuit
Debugger function of the device, the design must
implement ICSP connections to MCLR, VDD, VSS,
PGC, PGD, and the selected EMUDx/EMUCx pin pair.
DS70082G-page 164
TABLE 21-7: DEVICE CONFIGURATION REGISTER MAP
File Name Addr. Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
dsPIC30F
Note: The control bits in the OSCCON and FOSC registers may differ from those shown above. Please refer to the specific device data sheet for details.
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Preliminary
2004 Microchip Technology Inc.
dsPIC30F
22.0 INSTRUCTION SET SUMMARY Most bit oriented instructions (including simple rotate/
shift instructions) have two operands:
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
• The W register (with or without an address
reference source. For more information on the CPU, modifier) or file register (specified by the value of
peripherals, register descriptions and general device ’Ws’ or ’f’)
functionality, refer to the dsPIC30F Family Reference • The bit in the W register or file register (specified
Manual (DS70046). For more information on the device
instruction set and programming, refer to the dsPIC30F by a literal value, or indirectly by the contents of
Programmer’s Reference Manual (DS70030). register ’Wb’)
The dsPIC30F instruction set adds many The literal instructions that involve data movement may
enhancements to the previous PICmicro® instruction use some of the following operands:
sets, while maintaining an easy migration from • A literal value to be loaded into a W register or file
PICmicro instruction sets. register (specified by the value of ’k’)
Most instructions are a single program memory word • The W register or file register where the literal
(24-bits). Only three instructions require two program value is to be loaded (specified by ’Wb’ or ’f’)
memory locations. However, literal instructions that involve arithmetic or
Each single-word instruction is a 24-bit word divided logical operations use some of the following operands:
into an 8-bit opcode which specifies the instruction • The first source operand, which is a register ’Wb’
type, and one or more operands which further specify without any address modifier
the operation of the instruction. • The second source operand, which is a literal
The instruction set is highly orthogonal and is grouped value
into five basic categories: • The destination of the result (only if not the same
• Word or byte-oriented operations as the first source operand), which is typically a
register ’Wd’ with or without an address modifier
• Bit-oriented operations
• Literal operations The MAC class of DSP instructions may use some of the
• DSP operations following operands:
• Control operations • The accumulator (A or B) to be used (required
operand)
Table 22-1 shows the general symbols used in
describing the instructions. • The W registers to be used as the two operands
• The X and Y address space pre-fetch operations
The dsPIC30F instruction set summary in Table 22-2
• The X and Y address space pre-fetch destinations
lists all the instructions along with the status flags
affected by each instruction. • The accumulator write back destination
Most word or byte-oriented W register instructions The other DSP instructions do not involve any
(including barrel shift instructions) have three multiplication, and may include:
operands: • The accumulator to be used (required)
• The first source operand, which is typically a • The source or destination operand (designated as
register ’Wb’ without any address modifier Wso or Wdo, respectively) with or without an
• The second source operand, which is typically a address modifier
register ’Ws’ with or without an address modifier • The amount of shift, specified by a W register ’Wn’
• The destination of the result, which is typically a or a literal value
register ’Wd’ with or without an address modifier The control instructions may use some of the following
However, word or byte-oriented file register instructions operands:
have two operands: • A program memory address
• The file register specified by the value ’f’ • The mode of the Table Read and Table Write
• The destination, which could either be the file instructions
register ’f’ or the W0 register, which is denoted as
’WREG’
†
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note: All peripheral electrical characteristics are specified. For exact peripherals available on specific
devices, please refer the the Family Cross Reference Table.
VDD
LV10
LVDIF
(LVDIF set by hardware)
VDD
Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2
VDD/2
RL Pin CL
VSS
CL
Pin RL = 464 Ω
CL = 50 pF for all pins except OSC2
VSS 5 pF for OSC2 output
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
OS20
OS30 OS30 OS31 OS31
OS25
CLKOUT
OS40 OS41
I/O Pin
(Input)
DI35
DI40
VDD SY12
MCLR
Internal SY10
POR
SY11
PWRT
Time-out
SY30
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
SY20
SY13
SY13
I/O Pins
SY35
FSCM
Delay
VBGAP
0V
TxCK
Tx10 Tx11
Tx15 Tx20
OS60
TMRX
TABLE 24-21: TYPE C TIMER (TIMER3 AND TIMER5) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
TC10 TtxH TxCK High Time Synchronous 0.5 TCY + 20 — — ns Must also meet
parameter TC15
TC11 TtxL TxCK Low Time Synchronous 0.5 TCY + 20 — — ns Must also meet
parameter TC15
TC15 TtxP TxCK Input Period Synchronous, TCY + 10 — — ns N = prescale
no prescaler value
Synchronous, Greater of: (1, 8, 64, 256)
with prescaler 20 ns or
(TCY + 40)/N
TC20 TCKEXTMRL Delay from External TQCK Clock 2 TOSC — 6 TOSC —
Edge to Timer Increment
Note: Timer3 and Timer5 are Type C.
QEB
TQ10 TQ11
TQ15 TQ20
POSCNT
ICX
IC10 IC11
IC15
OCx
(Output Compare
or PWM Mode) OC11 OC10
OC20
OCFA/OCFB
OC15
OCx
MP30
FLTA/B
MP20
PWMx
MP11 MP10
PWMx
TQ36
QEA
(input)
TQ31 TQ30
TQ35
QEB
(input) TQ41 TQ40
TQ31 TQ30
TQ35
QEB
Internal
QEA
(input)
QEB
(input)
Ungated
Index TQ50
TQ51
Index Internal
TQ55
Position
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SP31 SP30
SP40 SP41
SP36
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SP35
SP20 SP21
SP40 SP30,SP31
SP41
SSX
SP50 SP52
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SP20 SP21
SP35
SP30,SP31 SP51
SP41
SP40
SP50 SP52
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SP35
SP20 SP21
SP52
SP30,SP31 SP51
SDIX
MSb IN BIT14 - - - -1 LSb IN
SP41
SP40
SCL
IM31 IM34
IM30 IM33
SDA
Start Stop
Condition Condition
SDA
Out
SCL
IS31 IS34
IS30 IS33
SDA
Start Stop
Condition Condition
SDA
Out
CA10 CA11
CXRX Pin
(input)
CA20
AD50
ADCLK
Instruction
Execution BSF SAMP BCF SAMP
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
AD61
AD60
DONE
ADIF
ADRES(0)
ADRES(1)
1 2 3 4 5 6 8 9 5 6 8 9
AD50
ADCLK
Instruction
Execution BSF ADON
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
TSAMP TSAMP
AD55 AD55 TCONV
DONE
ADIF
ADRES(0)
ADRES(1)
1 2 3 4 5 6 7 3 4 5 6 8 3 4
XXXXXXX dsPIC30F2010
XXXXXXX 30I/MM-ES
YYWWNNN 040700U
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard device marking consists of Microchip part number, year code, week code, and traceability code.
For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
XXXXXXX dsPIC30F4011
XXXXXXX 30I/MM-ES
YYWWNNN 040700U
XXXXXXXXXX dsPIC30F
XXXXXXXXXX 4011-30I/PT
XXXXXXXXXX
YYWWNNN 0448017
XXXXXXXXXX dsPIC30F
XXXXXXXXXX 5015-30I/PT
XXXXXXXXXX
YYWWNNN 0436017
XXXXXXXXXXXX dsPIC30F6010
XXXXXXXXXXXX -30I/PF
YYWWNNN 0436017
E E2
EXPOSED
METAL
PAD
D D2
2 b
1
OPTIONAL ALTERNATE L
INDEX INDEX
TOP VIEW AREA INDICATORS BOTTOM VIEW
A1
A
2
n 1 α
E A2
L
c
β A1 B1
eB B p
E
E1
p
B
2
n 1
h
α
45°
c
A A2
φ
β L A1
E1
2 α
n 1
A A2
L
c
β B1
A1
eB B p
E
E1
#leads=n1
D1 D
2
1
B
n
CH x 45 °
α
A
φ
β A1 A2
L
(F)
E
E1
#leads=n1
D1 D
2
1
B
n
CH x 45°
α
A
c
L φ A2
β A1
(F)
D1 D
B 2
1
n
α
A
A1
c φ A2
β L
(F)
E
E1
#leads=n1
D1 D
2
B 1
n
CH x 45°
A α
c
β φ A2
L A1
(F)
D1 D
B
2
1
n
α
A
A1
c φ A2
β L
(F)
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N
Questions:
2. How does this document meet your hardware and software development needs?
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d s P I C 3 0 F 2 0 1 0 AT- 3 0 I / P F - E S
Custom ID (3 digits) or
Trademark Engineering Sample (ES)
Architecture
Package
PT = TQFP 10x10
PT = TQFP 12x12
Flash PF = TQFP 14x14
P = DIP
SO = SOIC
Memory Size in Bytes
SP = SPDIP
0 = ROMless ML = QFN 6x6 or 8x8
1 = 1K to 6K
2 = 7K to 12K S = Die (Waffle Pack)
3 = 13K to 24K W = Die (Wafers)
4 = 25K to 48K
5 = 49K to 96K
6 = 97K to 192K Temperature
7 = 193K to 384K
I = Industrial -40°C to +85°C
8 = 385K to 768K
9 = 769K and Up E = Extended High Temp -40°C to +125°C
Speed
Device ID 20 = 20 MIPS
30 = 30 MIPS
Example:
dsPIC30F2010AT-30I/PF = 30 MIPS, Industrial temp., TQFP package, Rev. A
08/24/04