Information Engineering and Technology Faculty

German University in Cairo

Design of High Performance

Successive Approximation Register
Analog to Digital Converter

Bachelor Thesis

Author: Mahmoud Ahmed Ashraf

Supervisor: Dr Eman Azab & Eng. Ahmed Salah
Submission Date: 15 May, 2016
 Information Engineering and Technology Faculty
German University in Cairo

Design of High Performance

Successive Approximation Register
Analog to Digital Converter

Bachelor Thesis

Author: Mahmoud Ahmed Ashraf

Supervisor: Dr Eman Azab & Eng. Ahmed Salah
Submission Date: 15 May, 2016
 This is to certify that:

(i) the thesis comprises only my original work towards the Bachelor Degree

(ii) due acknowledgement has been made in the text to all other material used

Mahmoud Ashraf
15 May, 2016
Acknowledgments
It is an honor to have this chance to express my gratefulness and appreciation to
everyone who supported me throughout this journey towards my bachelor degree
in electronics.

Firstly, I thank Allah (SWT) for helping me to reach this point in my life. Without
Allah, nothing would have been accomplished. I wish from Allah to keep me guided
so I can continue learning and leaving impact with the knowledge I have.

It was my pleasure to work with Eng. Ahmed Salah and such a successful company
“Silicon Vision”. I would like to thank Dr. Eman Azab for her support throughout the
project, she was always encouraging us and giving us that confidence to continue the
project and improve our technical skills.

In addition to that I would like to thank my friends and partners in this project as we
all went through tough times in order to acquire that knowledge and capability to
understand and achieve an output.

Finally, I will be forever thankful to my family for their love and prayers which I will
never forget, nothing would have been accomplished without their continuous
guidance and support.

IV
Abstract
This thesis presents a 1.2 V 9-bit Successive approximation register (SAR) analog
to digital converter (ADC) design dedicated to the low power applications. It uses
a switchback switching scheme in the digital to analog converter (DAC) to reduce
power consumption. This thesis work also includes a general discussion about
ADCs followed by a brief one about SAR ADCs. This bachelor project report
covers the implementation of the SAR ADC as well as background information and
design of the control logic, comparator, capacitive array, and switches that meet
our specifications.

V
List of Content
Chapter ONE ................................................................................................................................. 12
1.1 Motivation ............................................................................................................................. 12
1.2 Aim of the Project ................................................................................................................... 13
1.3 Thesis Organization................................................................................................................ 13
Chapter TWO ................................................................................................................................ 14
2.1 ADC as a black box ........................................................................................................................ 14
2.1.1 Introduction ............................................................................................................................... 14
2.2 Classifications of Signals.......................................................................................................... 15
2.3 Efficiency and Performance measurements of Converters ........................................................ 17
2.4 Sampling ................................................................................................................................ 18
2.4.1 Sampling with no-aliasing: ......................................................................................................... 18
2.4.2 Sampling with aliasing................................................................................................................ 19
2.4.3 Oversampling ............................................................................................................................. 20
2.5 Quantization........................................................................................................................... 20
2.5.1 Oversampling and quantization ................................................................................................. 21
2.5.2 Quantization error spectra......................................................................................................... 21
2.5.3 Sampling of quantization errors ................................................................................................ 22
2.6 Conversion Systems ................................................................................................................ 22
2.6.1 Anti-Alias Filtering ...................................................................................................................... 23
2.6.2 Sample and Hold amplifer.......................................................................................................... 23
2.7 Specifications of converters ................................................................................................... 27
2.7.1 DC specifications ........................................................................................................................ 27
2.7.2 Dynamic specifications............................................................................................................... 31
CHAPTER THREE ...................................................................................................................... 35
3.1 Successive Approximation Register Different Types and Architectures ..................................... 35
3.1.1 Successive Approximation A/D Input Types .............................................................................. 36
3.1.2 Successive Approximation A/D Different Architectures ............................................................ 37
3.2 S/H and DAC Block (Capacitive array) ...................................................................................... 38
3.2.1 Charge Redistribution Method ................................................................................................. 39
3.2.2 Different Topologies.................................................................................................................. 41
3.2.3 Limitations................................................................................................................................. 41

VI
 3.3 Comparator ............................................................................................................................ 43
3.3.1 Comparator Design .................................................................................................................... 43
3.3.2 “Pre-amplifier + Latch” approach .............................................................................................. 44
3.3.3 Comparator limitations .............................................................................................................. 46
3.4 SAR logic ........................................................................................................................................ 47
Chapter FOUR .............................................................................................................................. 48
3.1 DAC Capacitive Array .............................................................................................................. 48
3.2 Bootstrapped Switch .............................................................................................................. 56
Chapter FIVE ................................................................................................................................ 59
5.1 Block Design Simulation .......................................................................................................... 59
5.2 Dynamic Performance Evaluation............................................................................................ 61
Chapter SIX .................................................................................................................................. 63
6.1 Conclusion .............................................................................................................................. 63
6.2 Future Work ........................................................................................................................... 63
References ..................................................................................................................................... 65

VII
List of Figures
Figure 2.1: The process flow operation ....................................................................................... 14
Figure 2.2: The Quantization process ........................................................................................... 15
Figure 2.3: The Base-band operation ............................................................................................ 16
Figure 2.4: The Band-pass operation ............................................................................................ 16
Figure 2.5: Definition of non-aliasing .......................................................................................... 19
Figure 2.6: Definition of aliasing ................................................................................................. 19
Figure 2.7: Quantization amplitude .............................................................................................. 21
Figure 2.8: Quantization of converter transfer function ............................................................... 22
Figure 2.9: Amplitude of quantization error ................................................................................. 22
Figure 2.10: Converter as a building blocks ................................................................................. 23
Figure 2.11: Zero Hold operation ................................................................................................. 24
Figure 2.12: Acquisition time ....................................................................................................... 25
Figure 2.13: Aperture time ............................................................................................................ 25
Figure 2.14 Error effect on the Hold stage ................................................................................... 26
Figure 2.15: DNL transfer function .............................................................................................. 28
Figure 2.16: INL transfer function ................................................................................................ 29
Figure 2.17: Definition of offset error .......................................................................................... 30
Figure 2.18: Definetion of SFDR and SNR ................................................................................. 32
Figure 3.1: Single-Ended Inputs ................................................................................................... 36
Figure 3.2: Pseudo-Differential Input ....................................................................................... 37
Figure 3.3: Fully Differential Inputs ............................................................................................ 37
Figure 3.4: Type 1 SAR ADC..................................................................................................... 37
Figure 3.5: Type 2 SAR ADC...................................................................................................... 38
Figure 3.6: Redistribution Phase Step-1 ..................................................................................... 39
Figure 3.7: Redistribution Phase Step-2 ..................................................................................... 40
Figure 3.8: Charge redistribution ................................................................................................ 40
Figure 3.9: Parasitic capacitance.................................................................................................. 42
Figure 3.10: open-loop and regenerative latch ........................................................................... 44
Figure 3.11: Pre-amplifier and Latch approach ......................................................................... 44
Figure 3.12: Latch circuit ............................................................................................................ 45

VIII
Figure 3.13: Linear response....................................................................................................... 46
Figure 4.1: Design Steps ............................................................................................................... 49
Figure 4.2: 4-bit split DAC (a) Shematic (b) Simulation result .................................................... 50
Figure 4.3: 8-bit split DAC (a) Shematic (b) Simulation result .................................................... 51
Figure 4.4: 8-bit split DAC (a) Shematic (b) Simulation result ............................................. 52
Figure 4.5: Split DAC Schematic ................................................................................................. 53
Figure 4.6: One unit cell of DAC................................................................................................. 55
Figure 4.7: Bootstrapped Switch (a) Shematic (b) Simulation result ........................................... 57
Figure 4.8: Block Diagram of Split DAC and Bootstrapped Switch Full System ........................ 58
Figure 5.1: Schematic of SAR ADC ............................................................................................. 59
Figure 5.2: (a) Output of the SAR ADC (b) DAC voltage ouput. ................................................ 60
Figure 5.3: FFT cadence simulation ............................................................................................. 61

IX
List of Tables
Table 1: Capacitor Array sizes ...................................................................................................... 54
Table 2: DAC switch sizes ............................................................................................................ 55
Table 3: Unit sizes of DAC ........................................................................................................... 56
Table 4: Bootstrapped sizes .......................................................................................................... 56
Table 5: SAR ADC Specifications ............................................................................................... 62

X
List of Abbreviations
DC Direct Current
AC Alternating Current
GND Ground
MOSFET Metal Oxide Silicon Field Effect Transistor
PMOS Positive-channel MOS
NMOS Negative-channel MOS
CMOS Complementary Metal Oxide Semi-conductor
SAR Successive Approximation Register
ADC Analog to Digital Converter
INL Integral Non-Linearity
DNL Differential Non-Linearity
DFF Delay Type Flip Flop
DL Delay Line
DR Dynamic Range
ENOB Effective Number of Bits
FOM Figure of Merit
FFT Fast Fourier Transform
HD Harmonic Distortion
LSB Least Significant Bit
MSB Most Significant Bit
SNR Signal to Noise Ratio
SNDR Signal to Noise and Distortion Ratio
SFDR Spurious-Free Dynamic Range
SINAD Signal to Noise and Distortion Ratio
DAC Digital to Analog Converter
BWC Binary-Weighted Capacitor

XI
 CHAPTER ONE
Introduction
In the first chapter in this thesis we will start by stating the reason this project has
been done and its importance. A brief description about the field of the project
and what we are targeting to achieve.

1.1 Motivation

In the real world, most data are characterized by analog signals. In order to
manipulate the data using a microprocessor, we need to convert the analog signals
to the digital signals, so that the microprocessor will be able to read, understand
and manipulate the data.

Analog-to-Digital Converters translate the analog quantities into digital language,

used in information processing, computing, data transmission and control systems.
ADCs are key components for the design of power limited systems, in order to keep
the power consumption as low as possible. The purpose of the ADC is to convert a
continuous analog signal into a discrete or quantized time varying signal. The
analog signal could be voltage, current, or charge, and is continuous in time and in
amplitude.

In this bachelor project, we describe the design of a medium speed low power
Successive Approximation Register Analog-to-Digital Data Converter with
specified aspects. Several ADC topologies exist. Some of the most popular designs
include - ADCs, flash ADCs, and SAR ADCs. By far the most common ADCs
are SAR ADCs. The main reason comes down to simplicity and design
specifications. The Successive Approximation Register (SAR) ADC is a common
architecture for its moderate resolution, relatively quick conversion time, and
simple circuit complexity.

12
1.2 Aim of the Project

This project is targeting design of low power ADCs with moderate resolution and
medium sampling frequency. It consumes low power due to its simple structure.

In this thesis, the main target is to design a low power 9-bit Successive
Approximation Register Analog-to-Digital Data Converter with input dynamic
range = 1VPP, operates at fs= 30MS/s and implemented in 130nm CMOS
technology.

1.3 Thesis Organization

This thesis is organized as follows: In chapter two, literature review generally about
the A/D converter, its static and dynamic performances. In chapter three, SAR ADC
is discussed with its main sub-blocks. The proposed split capacitive DAC is
introduced in chapter four and its advantages over conventional DAC. Simulation
results are reported in chapter five followed by conclusion and future work in
chapter six.

13
 CHAPTER TWO
Analog to Digital Converter Literal Review
In this chapter the general concepts about the analog to digital converter. Moving
on to an over-view of the basic building blocks internally of the ADC.

2.1 ADC as a black box

Thinking of the analog to digital converter most importantly we think about how
many number bits representing the output of this converter which we call it the
Resolution of the converter like for example if we have 8-bit converter then at zero
analog point of the I/P signal, the output will be (00000000) which is 8 bits of the
converter and so on. In the following part, the basic parameters in the converters
will be discussed.

2.1.1 Introduction

Analog signal is formatted using three separate processes; sampling, quantization

and encoding.

Figure 2.1: The process flow operation

14
 o Sampling

Analog signal is sampled every TS seconds, Ts is referred to as the sampling

interval and fs = 1/Ts is called the sampling rate or sampling frequency. There are
different types of sampling but we are going to use Flat-Top sample and hold which
is easy to be implemented using Sampling and holding Operation takes a slice of
the waveform but cuts off the top of the slice horizontally the top of the slice does
not preserve the shape of the waveform.

o Quantization

Quantization means giving analog signals a number of amplitude-discrete levels,

meaning it approximate the sampled points into a defined level.

Figure 2.2: The Quantization process

o Encoding

Each level of the quantized signal is given a number of bits according to the
resolution of the converter (which will discuss it shortly).

2.2 Classifications of Signals

In an analog to digital converter with its varies types different signal conditions
will be found.

15
o Analog Signal

Analog Signals are continuous-time and continuous-amplitude signals, basically

there is no limitation in bandwidth and amplitude.

o Discrete-time Signal

Baseband Signal: has its spectrum centered on the origin at f=0 and zero elsewhere,
its range between {-Fm, Fm} meaning the Fm indicates the maximum frequency of
this signal. The negative part is due to mirroring this signal to fit in the whole scale.
Band-pass Signal: A carrier frequency is used to shift the frequency spectrum of
transmitted signals. Baseband signal w(t) may be transformed into bandpass signals
through multiplication by a carrier [1].

Figure 2.3: The Base-band operation

Figure 2.4: The Band-pass operation

o Amplitude-discrete Signals

In continuous-time system, the amplitude can be quantized into discrete amplitude

levels, resulting in this type of signals.

16
 o Digital Signals

They are obtained if the signal is sampled at discrete time intervals and the
amplitude is quantized in the discrete amplitude levels.

2.3 Efficiency and Performance measurements of Converters

A/D and D/A converters perform digitalization or reconstruction of analog signals

The efficiency of such system can be measured by measuring its resolution,
dynamic range and signal to noise ratio. It has been said before that the number of
bits defining the type of this converter and defining the output bits of it.

Moreover, in an analog system the bandwidth is limited by the device and the
element performance which will introduce noise to the system. Noise is generated
in active and passive components which limits the dynamic range of an analog
system. The ratio between the maximum allowable analog signal and the noise
determines the dynamic range of the system. The Signal-to-noise (S/N) ratio also
one of the main aspects that defines the efficiency of the converter which is the
measurement of the maximum dynamic range of the system. Performance measures
can be divided into two groups, static and dynamic measurements [1].

o Static Performance

The differential non-linearity (DNL) and integral non-linearity (INL) are often used
as static performance measures; may not give all information needed to characterize
the converter.

o Dynamic Performance

The dynamic performance is determined by signal-dependent errors as non-linear

slewing, clock feed through (CFT), glitches, settling errors, etc. The signal-to-noise

17
 ratio (SNR), total harmonic distortion (THD), spurious-free dynamic range (SFDR)
and signal-to-noise-and-distortion ratio (SNDR) are commonly used as dynamic
performance measures [1].

2.4 Sampling

In this part we are going to talk about the sampling process in more details and its
probability of introducing errors. The Sampling process is defined by sampling
frequency or sampling rate fs is the average number of samples obtained in one
second (samples per second) thus fs = 1/T. In practice, the continuous signal is
sampled using an analog-to-digital converter (ADC) a device with various physical
limitations due to its limitations various types of distortion can occur due to the
sampling operation .one of the main distortion happens is “aliasing “and we are
going to discuss it shortly in the following part. The bandwidth of the band-pass
signal is our scoop of interest in the sampling process as there is direct relation
between the sampling rate and the bandwidth of the signal. The relation between
the sampling rate and the bandwidth of the signal will be discussed in the upcoming
parts.

2.4.1 Sampling with no-aliasing:

In case of the input signal as shown in figure (a) its band bandwidth is much smaller
than the Nyquist which ≤ fs/2 with sampling frequency (fs), then no aliasing occurs.
When the signal is sampled with a sampling frequancy fs then replica of the sign
band around sampling frequancey and its multiples appears. No aliasing appear
due to the pervious reason mentioned before, and it has been considered as an ideal
case.

18
 Figure 2.5: Definition of non-aliasing

2.4.2 Sampling with aliasing

In case the sampling frequency is not chosen high enough or the bandwidth of the
input signal exceeds ½ the sampling frequency then aliasing occurs. It is seen that
in case the input signal frequency larger than ½ the sampling frequency, the signal
part above fs/2 is aliased in the base band. This aliasing part can never have reversed
so to avoid aliasing the higher sampling frequency or smaller signal band is needed.
In other cases, aliasing part can’t be avoided and we are going to discuss this point
in details in part (2.5 Quantization) [3].

Figure 2.6: Definition of aliasing

19
2.4.3 Oversampling

When the sampling frequency is much higher than the maximum signal frequency
this is operation is called “oversampling”. Oversampling improves the resolution,
reduces noise, helps avoid aliasing and phase distortion.

2.5 Quantization

In this part errors caused by quantization and its effect on the input signal will be
discussed. Let’s consider a signal entering the ADC and getting quantized, Dout
represents the digitalized value of the analog input signal Va and qe represents the
quantization error. The quantization error represents the difference between the
analog input signal Va divided by Rref and the quantized signal Dout when a finite
number of quantization levels is used.

𝑉𝑎
= Dout + 𝑞𝑒
𝑅𝑟𝑒𝑓

The quantization of analog signals into a number of amplitude-discrete levels

places limitation on the accuracy of the signal. The amplitude-discrete levels are
called “quantization step”. To calculate the relation between the quantization step
qs and the input signal Vin, we want first to calculate the quantization step which is
the number of steps a signal is quantized into and those number are expressed in a
number of bits n. To explain the quantization step more clearly, the quantization of
the signal at amplitude level Aj. A signal Aj + ɛ is ideally quantized into level Aj as
𝒒𝒔 𝒒𝒔
long as the value of ɛ is between − <𝒙< . Form this example signals that
𝟐 𝟐

are somewhat larger than Aj + ɛ are quantized to the next quantization level Aj+1.

Finally Quantization of signals results in quantization errors; this error character

implies that under no circumstances should be a correlation between the analog
input signal and sampling clock. If a correlation exists, then the quantization errors
20
 appear at known points in the frequency spectrum which are multiplies of the signal
frequency. The ratio between the input signal frequency and the sampling
frequency should be an irrational number to avoid this correlation [3].

Aj+1

Figure 2.7: Quantization amplitude

2.5.1 Oversampling and quantization

As result of oversampling there is an effect upon the quantization error as the

quantization error density is reduced. When a large oversampling is used, then the
quantization steps are reduced with a factor equal to the oversampling ratio.
To summarize when oversampling increase, the quantization power decreases
which increase the dynamic range of the system. [3]

2.5.2 Quantization error spectra

Quantization can be defined as an error power that reduces the dynamic range of
the converter system. Suppose we have a ramp input signal and its quantized. Its
error signal can be determined as a saw tooth with amplitude qs and 2n repetition.

21
 Figure 2.8: Quantization of converter transfer function

Figure 2.9: Amplitude of quantization error

2.5.3 Sampling of quantization errors

The sampling of quantization error occurs always in ADC or DAC, the error
components above half the sampling frequency are floded back into the base band.
When correlation between the signal frequency and ampling frequency exists, the
quantization error components fold back at the multiplies of signal frequany and
then add or subtract to give the final quantization error.

2.6 Conversion Systems

When an anlaog-to-digital is applied in a complete system usign digial signal

processing then extra components must be added, this is the ADC as in system
level. In this part we are going to dicsuss the ADC as a system level [3].

22
 Figure 2.10: Converter as a building blocks

2.6.1 Anti-Alias Filtering

The filter at the input of the ADC limit the input signal band. In many cases this
signal band is a low-pass band which is easy to implement. In the bandpass case
the high frequency band is converted into a low-pass frequency band and then
converted into a digital signal.

2.6.2 Sample and Hold amplifer

Sample and hold amplifer is added to the system to sample the input signal and hold
the signal information at specific sampled value during the time in which the
converison a digital number is performed. Sample and hold amplifer is divided into
two modes sampling mode and hold mode, Intially the amplifer at the sampling
mode, it tracks the signal and sample it at defined sampling value then the amplifer
is switched to the hold mode to hold the information of the sampled value and gives
extra time to the ADC to perform the conversion between the input analog signal
to the digital analog signal [3].

o Zero-order hold operation

The Zero-order hold operation introduces an amplitude distortion where the

length of the output pulses of the sample-and-hold amplifer increases about the
sampling time so amplitude distortion occurs.

23
 Figure 2.11: Zero Hold operation

o Timing errors and other defectes in Sample-and-Hold amplifier:

The error in sample-and-hold amplifer is mainly concered with synchronization

time of the system to be able to sample the signal. Now various types of timing that
affect the performance of the amplifer will be discussed.

1) Acquisition Time

Genrally the acquisition time of a system is the time difference between the moment
of a command is given and the moment system respond to this command. This
timing is one of the important timings that affect the sample-and-hold amplifier.
The acquisition time also measure the maximum applicable sampling frequance of
a sample-and-hold amplifier and after the acquisition time is elapsed the system can
switch into hold mode. The accpeted error introduced by this timing is between the
input signal and the output signal of the system must bt within a specific number
[2].

24
 Figure 2.12: Acquisition time

2) Aperture Time

Another timing important for sample-and-hold amplifier as it’s the time difference
between the ‘hold’ command and the real sample taken by the system as it
determines the minimum time required to elapse before the sampling command can
be given. Differences in apreature time usually called “ apreature time uncertainty”.
The variation in time between the “ hold “ command and “ sample “ command can
be result in fractional changes in the signal-to-noise ratio of the system which we
will discuss it in details later [2].

Figure 2.13: Aperture time

25
3) Sample-to-hold step

The sample-to-hold step is a change in the analog output signal in a sampler-and-

hold amplifier at the moment the amplifier changes from sample mode to hold mode
due to a charge feed-through in the switch meaning an extra charge is leaked from
the switch and added to the hold signal. This extra charge we call it “hold step” and
it introduces an error which can be seen as an extra offset. To avoid such offset we
can apply on the sample-and-hold amplifier a control signal which force the hold
step to be zero. Also its applicable by changing the design of the circuitry to
miminize the hold step and to make it independent oof the input signal level [3].

4) Droop rate

In the hold mode of the sample-and-hold amplifier the output signal stored on the
hold capacitor, The voltage across this capacitor is measured using a small circuit
supplied with bias current. This bias current and other current discharges leacked
are all gathered up and minmize the voltage across the capacitor we call this leakage
“Droop rate” , the total droop rate during the conversion must be kept small. If the
droop rate is too high, a larger capacitor is needed to keep the droop rate within 1
LSB specification. To estimate the total leakage current Ileakage can be done from
this equation [3].
𝐼𝑙𝑒𝑎𝑘𝑎𝑔𝑒
𝑉𝑑𝑟𝑜𝑜𝑝 = 𝑇
𝐶ℎ𝑜𝑙𝑑 𝑐𝑜𝑛𝑣𝑒𝑟𝑠𝑖𝑜𝑛

Figure 2.14 Error effect on the Hold stage

26
 5) Signal Feed-Through During Hold Mode

In the hold mode, The input signal must be disconnected from the signal stored in
the hold capacitor. But practically what happen is some feed-through of the input
signal onto the signal in the hold capacitor due to the capacitive coupling over the
sample switch. To avoid this feed-through the architecture of the sample-and-hold
amplifier must be configured in a way that a maximum attenuation between the
input signal and the signal hold in the hold capacitor [3].

6) Noise in Sample-and-Hold Amplifiers

Generally any shifting between two different states causes a momentary noise
value, the same thing happens in the sample-and-hold amplifier at the moment the
system switches from track into hold mode this noise is present at the sampling
moment. Its impossible to avoid this sampling noise so its important to design the
circuitry in a way that peak value of the noise is small or limited in a defined
bandwidth.

2.7 Specifications of converters

To be able to design a converter it’s important to know what specifications should

it include to be able to serve whatever specific application the user want to perform.
The specifications of any converter is divided into DC specifications and Dynamic
specifications.

2.7.1 DC specifications

o System linearity

Discussing the concept of non-linearity, the width of the output code of the ADC
is the LSB, the voltage difference between each output code must be uniform,
27
equal to the value of the LSB and can be calculated from this equation, As 2𝑁
represents the total output code of the ADC and 𝑉𝑟𝑒𝑓 is a refrenece voltage.

𝑉𝑟𝑒𝑓
𝐿𝑆𝐵 =
2𝑁

The deviation in the size of codes rather than the LSB (non-uniform size) this is
called the differential non-linearity (DNL), Then non-unifromallity of steps cause
a difference in the spacing between each step of the output. On the other hand
another type of non-linearity which is the intergral no-linearity (INL) which is the
deviation of the function straight line, This straight line is the best fit of all points
of each step, So the INL is determined by measuring the voltage across the all code
transitions and compare it with the ideal if a difference exists then INL error exists.
Clearly seen from the following figure, this non-linearity causes distortion and may
affect the dynamic range of the system [2].

Figure 2.15: DNL transfer function

28
 Figure 2.16: INL transfer function

o Offset

Any device practically like input amplifier, output ampifier and compartors intially
have a built-in offset current and offest voltage. This offset caused by matching the
components of the circuit and it results in non-zero input or output voltage, current
or digital code although there is a zero signal apllied to the system. To calculate
such offset it crossponds to the average of all errors in the converter and its derived
in the following equation [2].

2𝑁 −1
1
𝑋𝑜𝑓𝑓𝑠𝑒𝑡 = 𝑁 ∑ ( 𝑋 ~ 𝑎,𝑘 − 𝑋𝑎,𝑘 )
2
𝑘=0

The effect of the offset on the function of the ADC in the following figure, it can
be seen that the offset is a shift (left or right) of the origianl function by a certain
value listed in the ADC data-sheet.

29
 Figure 2.17: Definition of offset error

o Missing Codes

Missing codes are output digital codes that are not produced for any input voltage,
usually due to large DNL. In some converters, missing codes can be caused by non-
monotonicity of the internal D/A.

o Temperature dependence

In designing a converter we need to take into consideration the tempreture , as

linearity must be maintained for a system over a large tempreture range to keep
distortion and signal-to-noise ratio within the specific range listed in the data sheet
of the converter. If we have varitaion of tempreture in form of ∆T. All specifications
are performed at a specific tempreture around 25𝑜 𝐶 [3].

o Supply voltage

In any converter its attacted with its specifications its supply voltage needed and
if any variation happened in the supply voltage must not exceed ± 5 tolerance.

30
2.7.2 Dynamic specifications

In some applications the DC specifications are not efficient enough to characterize

the performance of a converter, So the more efficient characterization is in the
frequency domain which we call Dynamic specifications.

o Signal-to-Noise Ratio

It’s the most important dynamic specification , the S/N ratio depends on the
resolution of the converter. It’s defined as the maximum dynamic range of the
converter, the S/N is calculated for sine wave input with maximum amplitude and
it’s the ratio between the frequency of the sine wave and the sampling frequency,
it should be equal irrational number.However if a sine wave applied to the system
with small amplitude the S/N ratio will decrease with the same ratio of input signal
decrease. The S/N ratio can be calculated with this equation.

𝑆/𝑁𝑚𝑎𝑥 = 6.02 + 1.76 𝑑𝐵

The S/N of an actual converter includes non-ideal effects and it can be determined
by measuring the output singal and S/N can be measured for the single tone as the
ration between the power of the fundamental and the total noise power [2].

𝑆𝑖𝑔𝑛𝑎𝑙 𝑝𝑜𝑤𝑒𝑟
𝑆𝑁𝑅 = 10 log( )
𝑇𝑜𝑡𝑎𝑙 𝑛𝑜𝑖𝑠𝑒 𝑝𝑜𝑤𝑒𝑟

o Spurious Free Dynamic Range

It’s the ratio between the maximum signal component and the largest distortion
component as shown in this figure. The input signal in this figure is sinsuoidal wave
appears as the fundamental wave , also other harmonics appear due to the nosie

31
 floor produced by the non-linearities in the ADC. These harmonics may be floded
from higher frequencies due to the sampling process [3].

o Signal-to-noise and disortion ratio (SNDR)

It’s the ratio of the power of the fundamental and the total noise and distortion
power whithin a certin frequencey band [1].

𝑆𝑖𝑔𝑛𝑎𝑙 𝑝𝑜𝑤𝑒𝑟
𝑆𝑁𝐷𝑅 = 10 𝑙𝑜𝑔 ( )
𝑁𝑜𝑖𝑠𝑒 𝑎𝑛𝑑 𝐷𝑖𝑠𝑡𝑜𝑟𝑡𝑖𝑜𝑛 𝑃𝑜𝑤𝑒𝑟

Figure 2.18: Definetion of SFDR and SNR

o Harmonic Distortion

The non-linearity of the converter produces what so-called harmonic distortion as

it’s the power ratio between the k-th harmonic and the fundamental.

𝑘 𝑡ℎ 𝐻𝑎𝑟𝑚𝑜𝑛𝑖𝑐 𝑃𝑜𝑤𝑒𝑟
𝐻𝐷𝑘 = 10 log( )
𝑆𝑖𝑔𝑛𝑎𝑙 𝑃𝑜𝑤𝑒𝑟

32
o Total Harmonic Distortion

It’s the ratio of the total harmonic distortion power and the power of the
fundamental in a certain frequency band.

𝑇𝑜𝑡𝑎𝑙 𝐻𝑎𝑟𝑚𝑜𝑛𝑖𝑐 𝐷𝑖𝑠𝑡𝑜𝑟𝑡𝑖𝑜𝑛 𝑃𝑜𝑤𝑒𝑟

𝑇𝐻𝐷 = 10 log ( )
𝑆𝑖𝑔𝑛𝑎𝑙 𝑝𝑜𝑤𝑒𝑟

o Effective Number Of Bits (ENOB’s)

It’s a method of comparing between the analog-to-digital converters of the same

number of bits together but with different circuit designs having different
performance. This comparison includes the dynamic range of the
converter,quantization errors, distortion errors and circuit noise [1]. The ENOB’s
are defined in the following equation

𝑆𝑁𝐷𝑅𝑚𝑒𝑎𝑢𝑟𝑒𝑑 − 1.76
𝐸𝑁𝑂𝐵 =
6.02
o Glitches

A glitch is generated during a major carry code transition as the new code appears
before or after the former code disapper, The largest glitches generated by a major
carry transition around the MSB level. A sharp glitch at the output results in
disortion which decrease the signal-to-noise ratio. When oversampling is used to
obtain larger dynamic range thus S/N ration, the distortion produced by the glitches
counteract this increase. A solution to reduce the glitch error is the addition of
“diglitcher“ circuit at the output of the converter but such circuit uses analog storage
element to hold the output singal durning the code transition is hard to design, so
practically is to use data-latch and bit-switch to minmize the glitch error [1].

33
o Noise

Thermal noise produced from resistors or amplifiers or bit currents that also will be
added to the quantization noise. Thermal noise exhibits itself as a deviation from
the theoretical maximum signal-to-noise ratio that an ideal converter can have.
Generally, noise can take place in the system from the presence of comparators in
the converter system as in order to be able to check if that input voltage is larger or

smaller compared to Vref voltage that is the only voltage capable to switch on the

system. That comparator represents a noise in the whole system.

However, the converter is not always performing in a perfect way so when an error
take place, a “Bit Error Rate” (BER) appears in the system. The comparator will
not be able to define the input it will neither be identified as 0 logic nor a 1 logic.
So that the comparator adds noise to the system in addition with the noise from
resistors or amplifiers or bit currents, also minimum reference voltage step size in
a parallel type of converter must be at least between 6 to 7 times the rms noise
voltage of the comparator and BER is a factor that must be taken into consideration
in designing the comparator [3].

34
 CHAPTER THREE
Literature Review about SAR ADC
In this chapter SAR A/D converter and its internal blocks, it is common architecture
for its moderate resolution and simplicity of the circuit will be discussed.

 Introduction:

Successive approximation register (SAR) analog-to digital converters require

several comparison cycles to complete one conversion; it is used for medium-high
resolution applications. Moreover, it is preferable to use SAR ADC for high rate,
low power, and area efficiency applications. The majority of SAR ADCs have an
effective resolution between 5 to 12 bits. The common SAR ADC consists of
binary-weighted capacitor array, SAR logic block and a comparator.

The SAR ADC performs a successive search on the sampled input which result in
a digitalized output of this signal, capacitor array sample the input signal and the
comparator is driven by the capacitor array and the reference voltage leading to a
result fed to the control logic. In the upcoming parts different architectures and
types of SAR ADC will be handled, going deep into details through each block the
SAR ADC has.

3.1 Successive Approximation Register Different Types and Architectures

SAR ADC has many different input types we are going to move on each one of
them also will discuss the different architectures of the SAR ADC.

35
3.1.1 Successive Approximation A/D Input Types

o Single-Ended Inputs

An ADC with single-ended input, it digitalizes its input relative to ground as it

reduces complexity and power dissipation. Single-ended inputs can be either
Unipolar or bipolar, where the Unipolar swings only above GND and the Bipolar
swings above or below GND.

Figure 3.1: Single-Ended Inputs

o Pseudo-Differential Input

This type also digitalize the differential analog input voltage (IN+ - IN-) over a
limited range, it also has a unipolar input signal, bipolar input signal and true
bipolar input signal. In unipolar input signal the differential input voltage over a
span of 0V to VFS. The IN+ is measured with respect to signal ground reference level.
In the IN+ pin is allowed to swing from GND to VFS while IN- pin is restricted to
around GND. On the other hand, the bipolar digitalize the differential analog input
voltage over a span of ±VFS/2. The IN+ is measured with respect to the signal mid-
scale reference level. In the IN+ pin is allowed to swing from GND to VFS while IN-
pin is restricted to around VFS/2. Moreover, the true bipolar digitalize the
differential analog input voltage over a span of ±VFS. The IN+ is measured with
respect to the signal ground reference level. In the IN+ pin is allowed to swing from
GND to VFS while IN- pin is restricted to around GND.

36
 Figure 3.2: Pseudo-Differential Input

o Fully Differential Inputs

In the fully-differential inputs digitizes the differential analog input voltage over a
span of ±VFS , in this range the IN+ and IN- should be driven 180◦ out-of-phase with
respect to each other and both allowed to swing from GND to VFS. While in the
fully differential true bipolar ADCs both IN+ and IN- pins are allowed to swing
above and below GND to ±VFS.

Figure 3.3: Fully Differential Inputs

3.1.2 Successive Approximation A/D Different Architectures

o Separate DAC and S/H circuit

Figure 3.4: Type 1 SAR ADC

37
 In this type the S/H circuit has its own separate block. The drawback of this
approach is that it consumes high power due to separate S/H circuit

o Combine DAC and S/H circuit

Figure 3.5: Type 2 SAR ADC

This architecture contains a capacitive DAC which also operates as S/H circuit,
this block uses the charge redistribution which achieved by using binary-weighted
capacitor array. The output of the DAC is compared to VCM using the comparator,
the main advantage of this approach is its low power consumption due to DAC and
S/H are both operate inside the capacitive array [11].

3.2 S/H and DAC Block (Capacitive array)

We are going to use the SAR ADC topology which contain both S/H and DAC just
in one block which is the capacitor array. The capacitor array minimizes the
complexity of the circuit and consumes less power.

The capacitor array contains N+1 number of capacitors where N is the number of
bits of the ADC with a binary scaled capacitance from 2𝑁−1 per bit plus a dummy
capacitor. The idea behind the dummy capacitor is to reduce the charge injection
and we will discuss it in details in the limitation part. The total capacitance of the
array equals 2𝑁 𝐶 where C is the unit of the capacitor. While dealing with the
capacitor array we have three modes of operation sampling mode, hold mode,

38
charge distribution mode and through an example we are going to discuss each one
of them. The capacitor array will sample the input signal Vin which is from 0V to
Vref, in the sampling mode all bottom plate switches of the capacitors will be
connected to Vin and the top plate switches to the ground. In the hold mode, the
bottom plat switches disconnected from the Vin and connected to the ground in
parallel with keeping the top plate switches to ground too, causing the node VA to
be –Vin to keep holding the input signal on the capacitor array.

In order to study this topology into more details let’s assume having 3-bit SAR
ADC, then the total capacitance of the array will be 23 = 8𝐶 and it contains 4
capacitors (4C, 2C, C, Cdummy). Firstly, during the sampling phase; the total charge
on the capacitors will be 𝑸 = 𝟐𝑵 𝑪 (𝟎 − 𝑽𝒊𝒏 ), then we move to hold mode to hold
the Vin samples in the capacitors by connected the bottom plate to the ground, due
to this conversion the voltage on the top plate after sampling equals -Vin [13].

3.2.1 Charge Redistribution Method

From this point the redistribution phase starts by producing the most significant bit
(MSB) by connecting the largest capacitor in the array to the Vref and the other
𝑽𝒓𝒆𝒇
capacitors to ground, the resulting voltage on the top plate is 𝑽𝒙 = − 𝑽𝒊𝒏 .
𝟐

Figure 3.6: Redistribution Phase Step-1

This node voltage is compared with signal ground. If this node is smaller than zero,
then this means that Vin is greater than Vref/2 and the MSB is “1”, similarly if the
voltage of this node is greater than zero it shows that Vin is smaller than Vref/2 and
the MSB is “0” . If the output is “1”, the MSB capacitor will remain connected to
Vref and the next largest capacitor in the array which is in our case 21 C connected
39
also to Vref. On the other hand, if the output is “0” then the MSB capacitor will be
connected to ground and 21 C capacitor will be connected to Vref as seen in this
figure, this process is repeated N=3 times until the digital output is produced.

Figure 3.7: Redistribution Phase Step-2

Figure 3.8: Charge redistribution

The voltage node Vx is determined by the law of conservation of energy as Qcurrent

= Qsampled. Qcurrent is the energy stored in the capacitor array while current switching,
however Qsampling is the charge stored in the array during sampling So we achieved
an equation that we can derive Vx no matter how many capacitors or the resolution
of the converter, where Cv is the group capacitance connected to Vref, Cg the group
capacitance connected to ground and N is the resolution of the converter [12].

𝐶𝑣 𝑉𝑟𝑒𝑓
𝑉𝑥 = −𝑉𝑖𝑛 +
∑𝐶

40
3.2.2 Different Topologies

The topology we used in our example is Binary-weighted capacitor array, and

it’s the commonly used topology for its simplicity but the occupied area and power
consumption of the BWC is increased with the increase of the resolution.

Moreover, another topology is introduced which is Two-stage weighted capacitor

array which is proposed to moderate the size of the capacitance in the BWC. In
this approach the BWC array is divided into two smaller BWC and a coupling
capacitor added in between. This architecture reduces the occupied area and power
consumption.

Lastly another approach is introduced beside the other two topologies which is C-
2C capacitor array which is an extension for the TWC array but in its
configuration, the capacitor sizes is highly reduced. As result, this type can achieve
higher speed while consuming less power. The power consumption of this topology
increases linearly on the contrary to BWC in which the power rises exponentially.
The main drawback of this architecture is the decrease of the linearity due to
parasitic capacitance [12].

3.2.3 Limitations

The major limitations in this type of architecture are slow speed due to large node
capacitance, which is seen at the inverting terminal of the comparator and being
sensitive to parasitic capacitance. In this part we are going to discuss more
limitations in this topology and how to improve it to increase the performance of
our SAR A/D converter.

o Parasitic capacitance

Parasitic capacitance affect with a major scope in determining the accuracy of a

41
 charge scaling DAC, as according to Figure3.9. As every capacitor in the capacitive
array is associated with parasitic capacitance on each plate as it contributes with
little overall charge error.

Figure 3.9: Parasitic capacitance

o Sampling Switch

Switches used in implementation of the capacitor array are MOS transistors which
introduce number of non-ideal effects in sampling and overall performance of the
A/D converter. One of the important non-ideal effects is non-zero on resistance, the
on resistance Ron derived from the square law of this equation.

𝟏
𝑹𝒐𝒏 =
𝑾
µ 𝑪𝒐𝒙 𝑳 (𝑽𝒊𝒏 − 𝑽𝒕𝒉 )

The on-resistance has a non-linear relationship with the input voltage which can
introduce distortion. To reduce this distortion, we can use the bootstrapped switch.
The bootstrapped switch used to ensure a constant on-resistance to minimize non-
linear charge injection [11].

Moreover, the MOS transistor has its own parasitic capacitance which we need to
take into consideration as it introduces an inject charge into the sampling capacitor
and degrade linearity. When the MOS transistor is on there is a small voltage drop
on the drain and the source, when it’s off a finite amount of charge is injected into

42
 the source and the drain terminals. This is a result of charge migrating from the
inversion layer as the transistor switched off. Long channel lengths and slow clock
transition can increase the amount of the injected charge; to avoid it we can use a
dummy transistor or transmission gate (TG) switch as the majority of the charges
is absorbed by this kind of switch. Another solution is obtained by bottom-plate
sampling technique which adds a signal independent early switch to isolate the
injected charge to the parasitic or bottom-plate terminal of the capacitor.

3.3 Comparator

The comparator is an essential part of SAR ADC and by choosing the compatible
design that suits the A/D converter, it would enhance its performance. In the SAR
ADC, the comparator is used to compare between the sampled value of the input
signal and the output voltage signal from the DAC block; according to which signal
is greater than the other the comparator gives a digital output in form of zero or one.

The speed, accuracy, power, offset and resolution are the main key factors that
should be taken into consideration while designing a comparator as they define its
performance and this might affect the whole performance of the ADC. Moreover,
in designing of comparator we seek low power, low offset and high resolution but
of course most of the time this can’t be achieved all together. So trying through the
comparator design to keep the high resolution and maintain as much as lowering
either power or offset [12].

3.3.1 Comparator Design

Comparators can be either be inverting or non-inverting comparator. The speed is

a very important factor in designing the comparator and it has its own limitations,
the speed limitations of the comparator is defined by two factors which are the
propagation delay and the Slew rate. The propagation delay defines the speed of
the comparator as how fast the comparator decides and it also affects the speed of

43
 the ADC. Adding that the slew rate is limiting the speed of the comparator, while
the accuracy of the comparator is measured by the minimum input voltage
difference which is detectable by the comparator which is called the resolution,
limiting factors of the resolution are expressed in noise and input offset voltage.
In designing the comparator take into consideration its static performance which
are the gain, offset, resolution and noise also its dynamic performance which are
propagation delay and slew rate. Our target from the comparator design is to have
either high speed, high resolution or high offset cancellation [11].

Figure 3.10: open-loop and regenerative latch

3.3.2 “Pre-amplifier + Latch” approach

High capacitance
node
Figure 3.11: Pre-amplifier and Latch approach

Originally the circuit design of the comparator consists of an output signal coming
from the capacitor array entering the latch, this direct connection due to high
capacitance node between the capacitor output and latch input causes an offset
voltage signal and a kickback noise which will be discussed later on in the
limitation part. The addition of the pre-amplifier is used to amplify the differential
input. The importance of the presence of such pre-amplifier before the latch reduces

44
the latch offset by the gain of the pre-amplifier, it acts as offset cancelation so that
the only offset is only due to the pre-amplifier. Basically the pre-amplifier consists
of an op-amp, and the higher the gain of this op-amp the better the performance,
however the gain is inversely proportional to the bandwidth of the input signal.

To improve the pre-amplifier, gain in parallel with maintaining the speed, using
cascaded low gain pre-amplifier stages with the same structure and gain value to be
able to achieve wide bandwidth amplifiers to take a small input signal and amplify
it without suffering slew rate limited [11].

Figure 3.12: Latch circuit

The comparator is a cascaded system needed to maintain its linear response. By

using the approach of using pre-amplifier followed by a latch it was noticed that,
the step response of the pre-amplifier is negative exponential. On the other hand,
latches have a step response with a positive argument in exponential so the pre-
amplifier is needed before the latch to compensate the time of the slow response of
the latch at the beginning of the process.

45
 Figure 3.13: Linear response

Analyzing this response, having a very small input signal, a long time for the latch
is required to reach the region where the slope is steep. So adding the pre-amplifier
avoids this slow rise rate of the exponential response of the latch and increase the
accuracy of the comparator.

3.3.3 Comparator limitations

In the practical comparator, many limitations affect its performance like offset,
metastability and kick-back noise.

o Offset

The basic comparator topology employing a preamplifier followed by a latch circuit.

Input offset can be reduced by using a pre-amplifier; however, the pre-amplifier
will increase power consumption. Either add a high-gain preamplifier at the
expense of decreasing speed is needed to reduce the latch input offset or add
number of cascaded low gain pre-amplifier. The offset voltage of the preamplifier
can be auto zeroed once we add the capacitor array before the pre-amplifier. The
dc input offset voltage depends on the matching and is reduced by auto zeroing.

o Metastability

Normally the latch has a specific interval of time which is half the period where it

46
 can generate a logic level, when the input voltage is very close to the reference
voltage it takes time more than its interval to produce a logical level which result
in a metastable state. In other words, metastability is an error takes place when the
latch can’t make a decision with the time allocated. Normally due to the input signal
is small. Metastability can be reduced by increasing the gain of the comparator by
preceding it with an amplifier to keep the signal to the latch as large as possible
under any condition.

o Kick-back noise

Kick-back noise (clock feed through) is in fact the voltage disturbance at the
differential input pair of the comparator due to large variation of voltage at internal
nodes. The change in the operation regions of the transistors accompanied with
change in the gate charge causing input voltage variation, this kickback noise will
be stored on the capacitive sampling array [12].

3.4 SAR logic

Successive approximation register ADC is mainly the brain of the converter as it

is the most critical one in making the entire converter to work in an organized way,
this block determines the value of bits based on digital output comes from the
comparator, also processes it to its final output stage also sends the switching
signals to the DAC at the correct intervals in order to get the conversion done at the
right time. Mainly the SAR logic operates in N cycles, this N is determined
according to the design used, in the first cycle SAR is in reset mode and all outputs
is zero, in the last cycle the SAR is storing the results of the complete conversion.
In general, there are two different architectures proposed to design the SAR logic,
the first approach consists of a ring counter and a shift register. The second
approach contains number of flip-flops and some combinational logic [11].

47
 CHAPTER FOUR
Digital to Analog Converter Design Details
This chapter includes the design of the proposed capacitive DAC array process
and the design of the bootstrapped switch with their results and simulations.

3.1 DAC Capacitive Array

A. Capacitive Array Design Strategy

The SAR ADC has a simple structure, low power consumption and fast conversion
rate. The overall accuracy and linearity of the SAR ADC is determined mainly be
the internal DAC. One of the popular DAC architectures is charge redistribution
DAC specially the binary weighted array that we discussed in chapter three.

The binary weighted array DAC has an inherent sample-and-hold function which
saves a lot of area and power consumption when the ADC is fabricated on a chip.
However, the sizes of DAC’s capacitors increase exponentially with the number of
bits, also DAC settling time. For example, if the unit capacitance C were 0.5pF and
designing a 12-bit ADC, the MSB capacitor will be 1024pF which is relatively
large, leading to difficulty of matching of the capacitors with each other [15].

One method of reducing the size of the capacitors is to use a different architecture
of the charge redistribution DAC which is split capacitive array that will be
discussed in this chapter and implement in our proposed SAR ADC. So we started
first by designing a 4-bit binary-weighted DAC and then upgrade it to 8-bit till we
reach it our split capacitive topology. If the simulation of the 4-bit is correct then
it’s easily to design 8-bit split DAC.

48
In case of the 8-bit binary weighted, the total input capacitance is equal to 256C
and the total area is 256 times the unit capacitor area. However, the split
capacitive array DAC is implemented and composed of two sub-binary weighted
arrays, LSB array and MSB array, each array will contain 4-bit matched together
by split capacitor (Csplit). The split capacitor has a fractional value equal to (16/15)
C. The total input capacitance in this case is 31C, which is about 8 times smaller
than that of the binary weighted array, however the split capacitor being fractional
causes poor mismatch with the other capacitors. The enhanced topology is to
replace the split capacitor value to be equal to the unit capacitor and removing the
dummy capacitor in the LSB side. However due to the lack of the dummy capacitor
1LSB gain error occurs [18].

Figure 4.1: Design Steps

49
- Trail (1): 4-bit BWC and its simulation result.

(a)

(b)

Figure 4.2: 4-bit split DAC (a) Shematic (b) Simulation result

50
 - Trail (2): 8-bit BWC and its simulation result.

(a)

(b)

Figure 4.3: 8-bit split DAC (a) Shematic (b) Simulation result

51
- Trail (3): 8-bit Split and its simulation result.

(a)

(b)

Figure 4.4: 8-bit split DAC (a) Shematic (b) Simulation result

52
 Split Capacitive Array (DAC) – Part 1 – LSB Binary Weighted Array

53
Figure 4.5: Split DAC Schematic
Split Capacitive Array (DAC) – Part 2 – MSB Binary Weighted Array
The value of the unit capacitor of the DAC (Cunit) is properly sized according to matching
and noise (KT/C), the unit capacitance selected to be 80fF and upon this size we designed
the rest of the capacitors in multiple of this number.

Table 1: Capacitor Array sizes

Capacitor Value

LSB C0 = Cu C

LSB C1 2C

LSB C2 4C

LSB C3 8C

Split Capacitor Csplit = Cu C

MSB C4 C

MSB C5 2C

MSB C6 4C

MSB C7 8C

C total 31C

B. DAC Switches Logic

Transmission gates are used to reduce charge injection effect, because NMOS and
PMOS have inverted polarity. The positive charge in NMOS can cancel out the
negative charge in PMOS. The idea is to have all the switches to have the same Ron,
however this causes possible transient when switches are toggled. So in our case,
we will size the switches proportionally to the capacitor sizes.

54
 Figure 4.6: One unit cell of DAC

The figure above represents the unit cell, first Q2 and Q1 was sized such that the
Ron of NMOS (when gate is VDD) equal to the Rop of PMOS (when gate is gnd),
then the unit cell was multiplied for each bit.

Capacitor Switch Sizes

LSB Bit 8 1 unit

LSB Bit 7 2 units
LSB Bit 6 4 units
LSB Bit 5 8 units
MSB Bit 4 1 unit
MSB Bit 3 2 units
MSB Bit 2 4 units
MSB Bit 1 8 unit

Table 2: DAC switch sizes

55
Since resistance value is proportional to 1/size, by the sizes above we could make
sure R1C1 = R2N C2 = R2P C2, then when switches changes there is no RC settling
transient. Finally, this is the main units to operate the DAC in a functional way.

Table 3: Unit sizes of DAC

Unit Split Unit cell Sizes

Capacitor Capacitor

80 fF 80 fF Q2 (NMOS) = 150n/130n
Q1 (PMOS) = 3.5u/130n

3.2 Bootstrapped Switch

Here is the design bootstrapped switch [14] used to sample the input voltage.

Unit cell Sizes Power Consumption

NMOS = 10u / 130n 6.6n W
PMOS = 10u /130n

Table 4: Bootstrapped sizes

(a)

56
 (b)

Figure 4.7: Bootstrapped Switch (a) Shematic (b) Simulation result

57
This is the full block diagram of booth DAC and bootstrapped switch connected
together. In the following chapter we are going to simulate this whole diagram
integrated inside the whole ADC.

Figure 4.8: Block Diagram of Split DAC and Bootstrapped Switch Full System

58
 CHAPTER FIVE
SAR ADC Simulations and Results
This chapter will include the full design of the SAR ADC with its proposed split
capacitive array, the chosen design of the bootstrapped switch, proposed
comparator design and its ideal control logic with their details, results and
simulations.

5.1 Block Design Simulation

In the following figure, the full schematic of the 9-bit SAR ADC is present, having
the Split DAC, dynamic latched comparator, ideal control.

Figure 5.1: Schematic of SAR ADC

59
 (a)

(b)

Figure 5.2: (a) Output of the SAR ADC (b) DAC voltage ouput.

60
5.2 Dynamic Performance Evaluation

As discussed in chapter three to evaluate the performance of the ADC we need to

evaluate the dynamic performance by calculating SFDR, SINAR and ENOB. For
this purpose, a sinusoidal wave with fin = 498.04 KHz which is applied to the input
of the ADC. The simulation is preformed to 1024 samples with sampling frequency
30MS/s. Then FFT to the output signal and by preforming some post processing
the SFDR, SINAR and ENOB are calculated. The FFT of 9-bit SAR ADC output
is shown in Figure (5.3). The simulation results show that the ADC have SFDR =
46.07, SINAD = 41.26 and ENOB= 6.65.

Figure 5.3: FFT cadence simulation

61
Table 5 summarize the performance parameters of the designed SAR ADC.

Specification (Unit) Experiment

Result

Technology (nm)
130

Supply voltage (V)

1.2

Input CM Voltage (V)

0.6

Input Range (Vp-p)

1

Sampling Capacitance
(pF) 5

Sampling Rate (MS/s)

30

Resolution (bit)
9

SFDR(dB)
46.07

SINAD(dB)
41.26

ENOB (bit)
6.56

Table 5: SAR ADC Specifications

62
 CHAPTER SIX
Conclusion and Future Work
In this thesis last chapter conclusion and future work will be handled.

6.1 Conclusion

Design state for each block by its own is not a difficult stage, the more difficult one
is the integration part as some loading problems will appear enabling the block of
getting out it optimum output. The conversion speed is limited by settling time and
control logic constraints. Some part in the whole ADC design will need to be
modified to fit with the whole design, so the problem is not from handling each part
by its one but it is in getting the optimum results from the whole integrated SAR
ADC. In this bachelor project an ideal low power SAR ADC with input dynamic
range = 1VPP, operates at fs= 30MS/s and implemented in 130nm CMOS
technology was successfully implemented using the proposed design of split
capacitor array which decrease the power consumption of mainly the DAC and
increase the linearity of the system.

6.2 Future Work

As future work, several improvements can be brought to the circuit in order to

increase the performances. We are targeting to improve our SAR ADC design in
order to be able to handle much more high speed through a study of the most
suitable design for Track and Hold circuit to be inserted in the circuit in order to
improve its performance; this block will increase the sampling rate, unable us to
increase the sampling frequency of the whole ADC and increase the accuracy of
our ENOB.

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Addition to trying to implement our proposed design of SAR ADC on different
technology, currently it is built by components from the standard 130nm CMOS
technology; this would help a lot to decrease the current flowing through it and
power consumption. The last important part that we still have to work on, is the
layout of the whole circuit and the post layout simulations in order to see the real
behavior and performances of the ADC.

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