1 2 3 4

m
VCC

R8
20K

co
A A
SCL
SDA
VIN U5 2.8V Power VCC AVDD
WEN 1 5
VIN OUT
2 R5
C9 C10 C11 GND C12 C13
3 4 0R
R6 R7 10UF 10uF 100nF EN BYT 100nF 100nF
U1

.
C1 1k 1k 1 5 PAM3101DAB28 C14
A VCC VIN 100uF
100nF 2
B

cu
C2 U2 3 4
GND Y
100nF AVDD A1 A3
AVDD SIO_C
VCC F1 A2 SN74LVC1G00
DOVDD SIO_D
P1
C3 3.3V VCC
VIN 1
100nF V1 C2 D1 VSYNC U3
VREF1 VSYNC 2
C4 V2 B2 D2 HREF 1 28 D0 SCCB Clock SCL
VREF2 HREF DI0 DO0 3
100nF E1 PCLK 2 27 D1 SCCB Data SDA

m
PCLK DI1 DO1 4
3 26 D2 Frame Synchro VSYNC
DI2 DO2 5
C5 DVDD C1 4 25 D3 Line Synchro HREF
B DVDD DI3 DO3 6 B
100nF B3 5 24 FIFO Write Enable WEN
F3
AGND
B4 C_D0 6
WE RE
23 XCLK R1 no solder CMOS CLK XCK
7
DOGND D0 GND GND 8
A4 C_D1 7 22 OE FIFO Read Address Reset RRST
D1 TST OE 9

er
B1 B5 C_D2 VSYNC 8 21 RRST R2 1K FIFO Chip Select CS OE
PWDN D2 WRST RRST 10
VCC E2 A5 C_D3 9 20 RCLK FIFO Read Clock RCLK
STROBE D3 WCK RCK 11
F5 C_D4 10 19
D4 VIN VDD DEC VCC 12
E5 C_D5 11 18 D4 R3 FIFO Output Data D0
R4 D5 DI4 DO4 13
E3 F4 C_D6 12 17 D5 0R FIFO Output Data D1
10K XCLK D6 DI5 DO5 14
C6 E4 C_D7 13 16 D6 FIFO Output Data D2
D7 DI6 DO6 15
F2 14 15 D7 FIFO Output Data D3

ow
#RESET DI7 DO7 16
FIFO Output Data D4
100nF 17
AL422B FIFO Output Data D5
18
OV7670 FIFO Output Data D6
C7 C8 19
FIFO Output Data D7
100nF 100nF 20
Header 2x10
U4
1 4
NC VCC VCC
.p
C C
2 3 XCLK
GND VOUT
X_24MHZ
w
w
w

Title OV7670 + AL422B ( FIFO) Camera Module(

. V2.0 )
D D

Size Number 1 Revision REV2.0

A4
Date: 2012-5-21 Sheet of
File: D:\OV7670+FIFO\7670.SCHDOC Drawn By: _
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