136 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 18, NO.
1, FEBRUARY 2005
Investigation of Gross Die Per Wafer Formulas
Dirk K. de Vries, Member, IEEE
Abstract—Different forms of gross die per wafer formulas are
investigated with respect to the accuracy in which they model the
exact gross die per wafer count, as a function of die area and die as-
pect ratio. Coefficients are given with which the different formulas
provide a sufficiently accurate model. To model the aspect ratio
dependence, it is found that the mean of die width and die height
should be used as a parameter.
Index Terms—Gross die per wafer (GDW), potential good die,
yield.
I. INTRODUCTION
G ROSS die per wafer (GDW) formulas (also called “po-
tential good die per wafer formulas”) serve as a base for
communication between IC foundry or wafer fabrication facility
(fab) and designer [1]. Such formulas give an estimate of ap-
proximately how many die of a given area (and aspect ratio)
will fit on a wafer. Alternatively, one could say that GDW for-
mulas are used to estimate how much wafer area is lost due to
roundness of the wafer and to the fact that dies have to be placed
on a regular grid, as determined by sawing.
The importance of a standardized GDW calculation lies first
in having a common and objective reference for product yield
reporting, rather than the more arbitrary count of testable or
tested die. Secondly it includes determining required wafer vol-
umes and product price agreements. The actual placement of
dies on the wafer is usually defined by the wafer fab through
optimization algorithms such as given in [2] and [3], taking into
account the exact alignment marks, process equipment clamps,
etc. However, these algorithms differ between fabs and do not
lend themselves to straightforward standardization or exchange.
Hence, GDW formulas are in use to have a simple and (poten-
tially) accurate approximation.
At present, a range of different formulas is used across
semiconductor manufacturing companies. These formulas can
give substantially different GDW estimates for a single die size,
which is an undesirable situation in view of the objectives given
above. GDW formulas are usually considered as confidential
information, and for this reason there are not many publications
in the field, either on the derivation of the formulas or on their
accuracy [1], [4]. The aim of this paper is to establish the accu-
racy of several forms of GDW formulas. A simple algorithm is
used to determine the exact count of GDW (excluding the effect
of clamps etc.) and the GDW formulas are compared with this
exact count. The analysis is restricted to wafers with no flat, as
is appropriate for 200- and 300-mm wafers.
Manuscript received January 3, 2003; revised June 3, 2004.
The author is with Philips Semiconductors, 38926 Crolles Cedex, France
(e-mail: dirk.de.vries@philips.com).
Digital Object Identifier 10.1109/TSM.2004.836656
0894-6507/$20.00 © 2005 IEEE
II. PUBLISHED MODELS
Due to process equipment related effects at the edge of the
wafer, a certain width along the edge is not considered to yield
reliable die. GDW formulas assume an effective wafer radius
, which is the physical radius minus a fixed edge exclusion,
typically in the range of 1 to 5 mm.
Because dies are placed on a periodic grid, it is the die pitch
rather than the net area of the die which determines the number
of GDW. We designate (die pitch die pitch ) as , i.e.,
the die area including the scribe lane.
We first treat models in which the GDW is derived as
multiplied by a correction factor.
Ferris–Prabhu gives the following formula [1]:
(1)
in which is the maximum of die width and die height. Ferris-
Prabhu uses an unpublished algorithm for verification, which
is especially biased toward large die areas ( 120 die/wafer).
However, certain symmetry assumptions appear to be present
in the algorithm, since the tabulated exact count always gives
odd numbers as result. This appears to be an undesired artifact.
Trapp et al. [4] give a formula without provision for effects
of aspect ratio variation
(2)
In an alternative approach, a correction term rather than a cor-
rection factor is assumed
(3)
This form is comparable to (2) written in three terms
(4)
and to the expansion of the Taylor series of (1) for square die
(5)
Note that the factor in the second term is quite different from
the corresponding factor in (4).
Another approximation using correction terms is given by
Muijen [5]. Muijen takes the aspect ratio into account and es-
timates for a random, i.e., nonoptimized placement
(6)
DEVRIES: INVESTIGATION OF GROSS DIE PER WAFER FORMULAS 137

TABLE I
EXACT COUNT OF GDW AS A FUNCTION OF DIE AREA (ROWS) AND
DIE ASPECT RATIO (COLUMNS) FOR R = 147 mm. DIE AREA,
INCLUDING SCRIBE, IN mm

The formula in use at Philips Semiconductors is based on an
approximation of an analytic formula derived by Rey [6].
Fig. 1. Natural logarithm of GDW correction factor versus die edge. Diamond
symbols represent the exact GDW counts. Ferris-Prabhu formula ((1), dashed
line) overestimates GDW. Equation (2) (solid line) severely underestimates
GDW.

III. EXACT COUNT ALGORITHM

To have an objective basis to judge the GDW formulas, an
exact count algorithm has been constructed. The algorithm, for
which an implementation is given in the Appendix, is based on
the assumption that in the optimum situation the die layout can
be shifted so that two corners in one row touch the edge of the
wafer. (Obviously, the exposure pattern to be chosen in practice
should optimize by maximizing the distance to the edge, taking
into account alignment marks and possibly clamps of certain
types of process equipment, etc. [2], [3].)
The output of the algorithm for the GDW as a function of
die area and aspect ratio is given in Table I. We have taken
mm which corresponds to a 300-mm wafer with Fig. 2. Aspect ratio variation: natural logarithm of the GDW correction factor
versus (H + W )=2. Dashed line is the behavior using the 1.16 coefficient found
3-mm edge exclusion (for every millimeter of edge exclusion, from the square die investigation.
approximately 1.3% of effective wafer area is lost). The influ-
ence of the aspect ratio is especially significant for dies with
large area and aspect ratio 2. A graphical analysis follows in When expanding these formulas, the third die area indepen-
the next section. dent term falls in the discretization noise caused by the exact
placement; either formula is closely approximated by the two-
IV. COMPARISON OF MODELS AND EXACT COUNT term formula

We first investigate the results for square dies, again taking
mm. In the Ferris-Prabhu approach, the correction
factor is modeled as an exponential function. We plot the natural
logarithm of the exact correction factor versus die edge in Fig. 1.
Over a very large range of die areas, an exponential model gives
an adequate approximation. However, the coefficient used in (1)
overestimates the GDW for square dies. A least squares fit of an
exponential function gives the modified formula
(7)
Also displayed in Fig. 1 is the Trapp formula [(2), solid
line]. Clearly, this formula severely underestimates the number
of GDW. However, in the die area range investigated here,
the shape of the curve is almost identical to the exponential
formula. An easy correction is multiplying the term in (2)
by an appropriate constant 1
(8)
(9)
V. EFFECT OF ASPECT RATIO ON GDW
The effect of aspect ratio variation on the number of GDW
has been investigated for five die sizes in a wide die area range.
The aspect ratio has been varied in steps of 0.1 between 1.0 and
10.0. As before, we fix mm.
To combine the different curves in a single formula, different
expressions in dimension “length” have been investigated,
namely , the die diagonal length
and the average edge length . Fig. 2 shows that
provides a good parameter to estimate the GDW
correction factor. Plotted against the other investigated length
measures, the exact GDW counts for nonsquare dies fall on
nonoverlapping curves depending on the die area.
The GDW count of rectangular dies as a function of
follows exactly the same curve as the GDW count for
138 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 18, NO. 1, FEBRUARY 2005

Fig. 3. VBA implementation of the exact GDW count algorithm.

square dies as a function of . Thanks to this, one can simply APPENDIX

replace in (7) and (8) by and in (9) by
An implementation written in Microsoft Excel’s Visual Basic
. It should be noted that although the vertical
for Applications (VBA) of the exact count algorithm is shown
axis of Fig. 2 has been chosen in accordance with (1), the dif-
in Fig. 3. The function DieFit determines how many die fit in a
ferent models all give very similar results provided that the same
row, taking into account odd/even die number constraints. (Note
length expression is applied.
that the VBA function Sqr calculates square root, not square).
The function GDWXY finds the GDW by determining total die
VI. CONCLUSION
counts for each possible number of die in the “touching row,”
The investigated GDW formulas perform well in approxi- i.e., the row for which the corners of the outermost dies touch
mating the exact GDW count, provided that the correct coeffi- the wafer edge. For each value of , the first loop counts the
cients are used. In this study, the following formulas have been dies in the rows below the touching row; the second loop counts
found to give accurate results: the dies above the touching row for those rows of which the die
centers are below the wafer center; and the third loop counts
dies which have their center above the wafer center. The func-
tion GDW optimizes for horizontal versus vertical placement of
rectangular die.

Differences between models are negligible with respect to the

variation due to the discrete nature of the exact count. ACKNOWLEDGMENT
If it is considered necessary to include a provision for the die
The author would like to thank J. Jacques and W. Rey for
aspect ratio, the GDW formulas should include as
technical discussions.
parameter

REFERENCES
[1] A. V. Ferris-Prabhu, “An algebraic expression to count the number of
chips on a wafer,” IEEE Circuits Devices Mag., pp. 37–39, Jan. 1989.
DEVRIES: INVESTIGATION OF GROSS DIE PER WAFER FORMULAS 139

[2] C.-F. Chien, S.-C. Hsu, and J.-F. Deng, “A cutting algorithm for opti- Dirk K. de Vries (M’01) received the M.S. degree in
mizing the wafer exposure pattern,” IEEE Trans. Semiconduct. Manu- technical physics from the University of Technology,
fact., vol. 14, pp. 157–162, May 2001. Eindhoven, The Netherlands, and the Ph.D. degree
[3] G. D. Croft, R. L. Lomenick, D. L. Youngblood, and J. M. Johnston, “Die in physics from the Ruhr University, Bochum, Ger-
counting algorithm for yield modeling and die per wafer optimization,” many, in 1992 and 1995, respectively.
in Proc. SPIE, vol. 3216, 1997, pp. 186–196. Since joining Philips in 1996, he has been active
[4] Semiconductor Technology Handbook, Technology Associates, Portola in the field of semiconductor manufacturing yield.
Valley, CA, 1993. O. D. Trapp, L. J. Lopp, R. A. Blanchard. From 1996 to 2002, he held yield engineering,
[5] N. N. Muijen, “Philips Central TEO Tech. Note ER8191,”, May 1968. yield management, and yield consulting functions
[6] W. J. J. Rey, “How many chips per wafer? Derivation of the number of in Philips Semiconductors, Nijmegen. In 2002, he
potential good dice per wafer,” Philips Nat. Lab. Rep. 6230, Jun. 1995. joined Philips Semiconductors, Crolles, France,
where his activities cover yield improvement and yield systems.