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Electrical, Control and Communication Engineering
a = V cos ( t ) ; (2)
III. COMPONENT SIZING
2
b = V cos t − ; (3) The component sizing for the system shown in Fig. 1 is
3 performed as follows:
2
c = V cos t + , (4) A. DC Capacitor Voltage
3
The DC capacitor voltage basically depends upon the PCC
where V is the peak value of the PCC voltage per phase. voltage [41]. The relationship between the PCC voltage and the
The voltage relationship between the PCC and the inverter DC capacitor voltage [35], [41] can be shown as follows:
(STATCOM) is expressed as follows:
2 2VLL
a ia ia ea VDC = , (11)
= R i + L d i + e . (5)
3MI
b b dt
b b
where MI and VLL represent the modulation index (set as unity)
c ic ic ec and the line-to-line rms PCC voltage, respectively.
Transforming (5) into a d–q reference frame, it can be written Here, the value of the reference DC voltage is selected to be
that 800 V.
d id − R L id d − ed B. DC Capacitor
L = + .
dt iq −L − R iq q − eq
(6)
The VSC of the STATCOM is rated for 25 kVA, hence the
From Eq. (6) it can be seen that the voltage equations of each rms value of the system current would be
axis are cross-coupled. In order to facilitate the decoupled 25 103
control of d–q axes source current components, the equivalent I rms = . (12)
3VLL
control signals are derived from the inner current control loop
and the decoupled d–q axes reference inverter (STATCOM) The capacitance value of the DC capacitor [35] may be
voltage can then be expressed as follows: formulated as
0.9 I rms
ed* = d − Liq − d ; (7) C= , (13)
0.02 4fVDC
eq* = q − Lid − q , (8)
where f is the nominal supply frequency.
where ed* and eq* are the reference values of the STATCOM Here, the capacitance of the capacitor is selected to be 3200 µF.
voltages and
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Fig. 9. Bode plot of the open-loop transfer function of the outer DC voltage
control loop.
Fig. 8. Block diagram representation of the DC voltage control loop.
The block-diagram representation of the outer DC voltage
control loop is depicted in Fig. 8. Using the block diagram of
the outer DC voltage control loop, the open-loop transfer
function can be expressed as follows:
Kpo K 1 + To s 1
GV,OL ( s ) = , (24)
sT To s 1 + Te s
where Tν = Kpo/Kio; (25)
T = 2C/3; (26)
K = νd/VDC, (27)
Fig. 10. Step responses of the DC voltage control loop.
and Te is the sum of the time lag associated with the control
delay in the outer DC voltage control loop (= 10Tsample) and the Using (24), (30)–(31), it is possible to obtain the closed-loop
time constant of the approximated first-order closed-loop transfer function of the outer DC voltage control loop as
transfer function of the inner current control loop (= 2Tw), i.e.
1 + a 2Te s
GV,CL ( s ) = . (32)
Te = 2Tw + 10Tsample. (28) ( aTe s + 1) ( a 2Te2 s 2 + a ( a − 1) Te s + 1)
The desired goal of the outer DC voltage control loop is The open-loop Bode plots and step responses of the outer DC
system stability and optimum regulation. It can be observed voltage control loop for different values of parameter ‘a’ are
from (24) that the outer DC voltage control loop has a pole at shown in Figs. 9–10, respectively.
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Step response
Crossover Closed
GM, PM, Damping
Tuning criterion Kpi Ti frequency, loop Settling
dB ° ratio Overshoot,
rad/s stable? time,
%
ms
SO with a = 2 3.8744 0.00260 –∞ 36.9 769 Yes 0.5 43.4 10.8
SO with a = 3 2.5829 0.00585 –∞ 53.1 513 Yes 1.0 24.9 15.4
SO with a = 4 1.9372 0.01040 –∞ 61.9 385 Yes 1.0 17.3 26.6
The PI controller parameters, the gain and phase margins as Case 1: Performance Under Balanced Non-Linear Load
well as the settling time and the percentage peak overshoot in
In this case, the performance of the proposed STATCOM
the step responses are listed in Table I. It can be observed that,
control method is analysed under balanced non-linear load
with an increase in parameter ‘a’, the phase margin and the
which is constituted by three single-phase diode-rectifiers that
settling time both increase whereas the overshoot decreases.
separately feed impedances of similar values, i.e.
With increased phase margin, also the robustness of the system
(20+j18.85) Ω. One can observe from Fig. 11(a) that the
increases [35]. It is found that the DC voltage control loop
capacitor voltage is maintained at its reference value, i.e. 800
offers reasonable performance when a = 3. Hence, the value of
volts. The observed three-phase PCC voltage is sinusoidal (see
parameter ‘a’ is chosen equal to 3 for the tuning of the outer DC
Fig. 11(b)). The non-linear load current profiles for all three
voltage PI controller. The symmetric optimum PI tuning
phases are shown separately in Fig. 11(c). These non-linear
criterion corresponding to a = 3 results in a phase margin equal
load currents are compensated by the inverter (STATCOM).
to 53.1° while the settling time is observed to be 15.4 ms with
The compensating STATCOM current profiles for all three
an overshoot of 24.9 %.
phases are shown separately in Fig. 11(d). Fig. 11(e) shows the
TABLE II compensated source current profiles which are nearly
SIMULATION PARAMETERS sinusoidal. Moreover, it is noticeable that similar currents are
Parameter Value
carried by each phase since the non-linear loads connected at
the PCC are balanced. The harmonic spectra and the THDs of
VLL 415 V
F 50 Hz
the load and source currents are also shown in Figs. 11(f)–(h)
R 1.8 Ω for all three phases. Further, the magnitudes and THDs of the
L 3.91 mH load and source currents for Case 1 are listed in Table III.
C 3200 µF
VDC 800 V Case 2: Performance Under Unbalanced Non-Linear Load
Kpi 26.06
In this case, the performance of the proposed STATCOM
Kii 12 000
Kpo 2.5829
control method is analysed under unbalanced non-linear load
Kio 445.327
which is constituted by three single-phase diode-rectifiers
connected between the phases a–b, b–c and c–a, respectively;
which separately feed impedances of different values, i.e.
VI. SIMULATION VERIFICATION
(12 + j18.85) Ω, (20 + j1.885) Ω and (28 + j0.1885) Ω at the
Having tuned the inner and outer PI controllers with the help DC sides, respectively. Although a small ripple in DC voltage
of the modulus optimum and symmetric optimum criteria, is apparent in Fig. 12(a), caused by the unbalanced non-linear
respectively, a few case studies are presented using MATLAB load currents, still the capacitor voltage is maintained at its
simulation to exemplify the success of the proposed reference value, i.e. 800 volts, in this case as well. The observed
STATCOM control method as follows: three-phase PCC voltage is sinusoidal (see Fig. 12(b)). The
non-linear load current profiles for all three phases are shown
Case 1: Performance under balanced non-linear load; separately in Fig. 12(c). Even under unbalanced non-linear load
Case 2: Performance under unbalanced non-linear load; connected at the PCC, the STATCOM effectively compensates
Case 3: Performance under unbalanced non-linear load with the non-linear load currents, and the compensating STATCOM
a switched unbalanced linear resistive load. current profiles for all three phases are shown separately in
Fig. 12(d). Fig. 12(e) shows the compensated source current
A stiff AC supply system with a negligible grid impedance profiles, which are nearly sinusoidal. Moreover, it is noticeable
has been considered in this paper. The uncontrolled diode- that different load currents are drawn from each phase since the
bridge rectifier is usually employed as non-linear load in non-linear loads connected at the PCC are unbalanced.
simulations as well as experimental setups due to the fact that it However, the currents supplied by the source are almost
results in the worst harmonic current distortions [4], [45], [46]. balanced. The harmonic spectra and the THDs of the load and
Also in this study, the uncontrolled diode-bridge rectifier has source currents are also shown in Fig. 12(f)–(h) for all three
been used in constituting the non-linear load. Further, the phases. Further, the magnitudes and THDs of the load and
system parameters used in the simulation are listed in Table II. source currents for Case 2 are listed in Table III.
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Electrical, Control and Communication Engineering
(a)
(b)
(f)
(c)
(g)
(d)
(h)
Fig. 11. The performance of the proposed STATCOM control under balanced
non-linear load: (a) DC capacitor voltage; (b) voltage at PCC; (c) load current
profiles separately for all three phases; (d) STATCOM (inverter)
compensating current profiles separately for all three phases; (e) compensated
source current profiles separately for all three phases. Harmonic spectra of
load currents and compensated source currents for (f) phase a; (g) phase b; (h)
phase c.
(e)
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Electrical, Control and Communication Engineering
(a)
(b)
(f)
(c)
(g)
(d)
(h)
Fig. 12. The performance of the proposed STATCOM control under
unbalanced non-linear load: (a) DC capacitor voltage; (b) voltage at PCC; (c)
load current profiles separately for all three phases; (d) STATCOM (inverter)
compensating current profiles separately for all three phases; (e) compensated
source current profiles separately for all three phases. Harmonic spectra of
load currents and compensated source currents for (f) phase a; (g) phase b; (h)
phase c.
(e)
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Electrical, Control and Communication Engineering
(a)
(b)
(f)
(c)
(g)
(d)
(h)
Fig. 13. The performance of the proposed STATCOM control under
unbalanced non-linear load with a switched linear resistive load: (a) DC
capacitor voltage; (b) voltage at PCC; (c) load current profiles separately for
all three phases; (d) STATCOM (inverter) compensating current profiles
separately for all three phases; (e) compensated source current profiles
separately for all three phases. Harmonic spectra of load currents and
(e) compensated source currents for (f) phase a; (g) phase b; (h) phase c.
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Electrical, Control and Communication Engineering
(a)
(b)
(c)
Fig. 14. Capability of the proposed STATCOM control for supporting reactive power during a voltage sag condition: (a) voltage at PCC; (b) q-axis source current
component (reactive current); (c) reactive power support to the source (grid).
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