rtltxbuf.ischeduling.

idisvld: drop signal

oilkvld,
oilkdat,
oilkid,//ILKN ID
oilknob,
oilksop,//start of seg
oilkeop,//end of seg
oilksos,//segment first
oilkeos,//segment end
oilklen,//length of segment

//-------------------------------------------------------
//08-06-2020
//------------------------------------------------------
- ilkn block test:
+ update new code to GIT
+ fab2cli:
+ sar: almost pass
++ odu0:
+++ meta length 8096: failed

+ cep: almost pass

+++ vc4:
++++ 1 channel: pass
++++ 64 channel, FC en=1 : failed -> Nhon checking
++++ 64 channel, FC en=0 : pass

+ eth: pass

+ odu0 force err, 64 flow:

++ 64 odu#0 skew ui: failed -> liem checking

+ mix 16 odu0 + 2 odu2, 16 vc4_16c + 4 toh_stm64, 4 flow xge: pass

+ 64 odu#0, interleave segment: pass

+ 12 10 Ge, interleave segment: pass
+ 64 odu#0, rd cfg and compare: pass
+ 64 odu#0 , align err cnt, align 4err cnt

+ cli2fab:
+ cep:
+++ vc4:
++++ 1 channel: pass
++++ 64 channel, FC en=1 :
++++ 64 channel, FC en=0 :

+++ vc4_4c
++++ 1 channel : pass
++++ 16 channel: pass

+++ vc4_16c:
++++ 1 channel :
++++ 10 channel :

+++ toh_stm1
+++ 1 channel:
+++ 68 channel:
 +++ toh_stm4
+++ 1 channel:
+++ 68 channel:

+++ toh_stm16
+++ 1 channel:
+++ 36 channel:

+++ toh_stm64
+++ 1 channel:
+++ 12 channel:

+++ mix all cep

+ eth:
+++ 10G:
++++ 1 channel: failed
++++ 12 channel:

- Build PDA_CLA block test: 100%

+ update test plan for check cla cnt, pda cnt: 100%
+ update dut_check_seq: 100%
+ update scb for check cnt: 100%

- Txbuf re-sim: update env done, wait simulator on and start re-run
+ update test plan for cnt: 100%
+ update scb for check cnt: 100%
+ update dut_check_seq: 100%

- Update FC1200, FC1600 force err

++ review FC1200: DONE
++ loss of sync: (L1 tx)
+++ force block_lock = FAILED & hi_ber = TRUE (hdr 2 bit): 100%
+++ loss of signal
++ code violation:
+++ table 10: transmission word type -> force value != 1E, 33, b4, 2d,
4b, 55, 66, 78, ff: 100%
+++ table 11: valid control code value -> force value != 'h00 (idle),
'h06 (lpi): 100%
force value 'h1e (err) before
send idle followed by sof:
+++ table 12: valid order code value -> force value != 'h0 (Primitive
Sequence), 'hf (Primitive Signal)
++ ttt
+++ 513b block: force F, FC, POS, CB_type: 100%
+++ super block: force crc24: 100%

++ review FC1600

//-------------------------------------------------------
//15-06-2020
//------------------------------------------------------
- ilkn block test:
+ update new code to GIT
+ fab2cli:
+ sar: almost pass
++ odu0:
 +++ meta length 8096: failed

+ cep: almost pass

+++ vc4:
++++ 1 channel: pass
++++ 64 channel, FC en=1 : failed -> Nhon checking
++++ 64 channel, FC en=0 : pass

+ eth: pass

+ odu0 force err, 64 flow:

++ 64 odu#0 skew ui: failed -> liem checking

+ mix 16 odu0 + 2 odu2, 16 vc4_16c + 4 toh_stm64, 4 flow xge: pass

+ 64 odu#0, interleave segment: pass

+ 12 10 Ge, interleave segment: pass
+ 64 odu#0, rd cfg and compare: pass
+ 64 odu#0 , align err cnt, align 4err cnt

+ cli2fab:
+ cep:
+++ vc4:
++++ 1 channel: pass
++++ 64 channel, FC en=1 :
++++ 64 channel, FC en=0 :

+++ vc4_4c
++++ 1 channel : pass
++++ 16 channel: pass

+++ vc4_16c:
++++ 1 channel :
++++ 10 channel :

+++ toh_stm1
+++ 1 channel:
+++ 68 channel:

+++ toh_stm4
+++ 1 channel:
+++ 68 channel:

+++ toh_stm16
+++ 1 channel:
+++ 36 channel:

+++ toh_stm64
+++ 1 channel:
+++ 12 channel:

+++ mix all cep

+ eth:
+++ 10G:
++++ 1 channel: failed
++++ 12 channel:

- Build PDA_CLA block test: 100%

 + update test plan for check cla cnt, pda cnt: 100%
+ update dut_check_seq: 100%
+ update scb for check cnt: 100%

- Txbuf re-sim: update env done, wait simulator on and start re-run
+ update test plan for cnt: 100%
+ update scb for check cnt: 100%
+ update dut_check_seq: 100%

- Update FC1200, FC1600 force err

++ review FC1200: DONE
++ loss of sync: (L1 tx)
+++ force block_lock = FAILED & hi_ber = TRUE (hdr 2 bit): 100%
+++ loss of signal
++ code violation:
+++ table 10: transmission word type -> force value != 1E, 33, b4, 2d,
4b, 55, 66, 78, ff: 100%
+++ table 11: valid control code value -> force value != 'h00 (idle),
'h06 (lpi): 100%
force value 'h1e (err) before
send idle followed by sof:
+++ table 12: valid order code value -> force value != 'h0 (Primitive
Sequence), 'hf (Primitive Signal)
++ ttt
+++ 513b block: force F, FC, POS, CB_type: 100%
+++ super block: force crc24: 100%

++ review FC1600
++ fec eth:
++ ttt