Professional Documents
Culture Documents
KT14203
Computer
Architecture
and
Organization
Presented by:
Dr. Mohd Hanafi Ahmad Hijazi
SKTM, UMS
Slides, with minor modifications, taken from
William Stallings Computer Organization and
Architecture, 9th Edition
+
Chapter 3
A Top-Level View of Computer
Function and Interconnection
+
Computer Components
Hardwired program
The result of the process of connecting the various components in
the desired configuration
+
Hardware
and Software
Approaches
Software
• A sequence of codes or instructions Software
• Part of the hardware interprets each instruction and
generates control signals
• Provide a new sequence of codes for each new
program instead of rewiring the hardware
Major components:
• CPU I/O
• Instruction interpreter Components
• Module of general-purpose arithmetic and logic
functions
• I/O Components
+ • Input module
• Contains basic components for accepting data
and instructions and converting them into an
internal form of signals usable by the system
• Output module
• Means of reporting results
Memory Memory buffer MEMORY
address register (MBR)
register (MAR) • Contains the data
• Specifies the to be written into
address in memory memory or
for the next read or receives the data
write read from memory
MAR
Processor- Processor-
memory I/O
Data
Control
processing
Instruction-
execution
Scan me!
+
Instruction Cycle State Diagram
+
Classes of Interrupts
Program Flow Control
+
Transfer of Control via Interrupts
+
Instruction Cycle With Interrupts
+
Program
Timing:
Short I/O
Wait
+
Program
Timing:
Long I/O
Wait
Instruction Cycle State Diagram
With Interrupts
Transfer of
Control
Multiple
Interrupts
+
+ Time Sequence of E me
Multiple Interrupts x p
a l
+
I/O Function
I/O module can exchange data directly with the processor
An I/O
module is
allowed to
exchange
data
Processor Processor
directly
reads an Processor reads data Processor
with
instruction writes a from an I/O sends data
memory
or a unit of unit of data device via to the I/O
without
data from to memory an I/O device
going
memory module
through the
processor
using direct
memory
access
A communication pathway Signals transmitted by any
connecting two or more one device are available for
devices reception by all other
• Key characteristic is that it is a devices attached to the bus
I
n
shared transmission medium • If two devices transmit during the
same time period their signals will
overlap and become garbled
n
e
Typically consists of multiple
t
communication lines Computer systems contain a
number of different buses B c
• Each line is capable of
transmitting signals representing
that provide pathways
between components at e
binary 1 and binary 0
various levels of the u t
r
computer system hierarchy
s i
c
System bus
o
o
• A bus that connects major The most common computer
computer components (processor,
memory, I/O) interconnection structures
are based on the use of one
or more system buses n
n
Data Bus
Data lines that provide a path for moving data among system
modules
Used to designate the source or Used to control the access and the
destination of the data on the use of the data and address lines
data bus
If the processor wishes to Because the data and address lines
read a word of data from are shared by all components there
memory it puts the address of must be a means of controlling their
the desired word on the use
address lines
Control signals transmit both
Width determines the maximum command and timing information
possible memory capacity of the among system modules
system
Timing signals indicate the validity
Also used to address I/O ports of data and address information
The higher order bits are
used to select a particular Command signals specify operations
module on the bus and the to be performed
lower order bits select a
memory location or I/O port
within the module
Bus Interconnection Scheme
+
Elements of Bus Design
Timing of
Synchronous
Bus
Operations
Timing of
Asynchronous
Bus
Operations
+
Point-to-Point Interconnect
Principal reason for change At higher and higher data
was the electrical rates it becomes
constraints encountered increasingly difficult to
with increasing the perform the synchronization
frequency of wide and arbitration functions in a
synchronous buses timely fashion