Analysis of Via To Via Crosstalk For Single Ended Signals in The Time & Frequency Domains PDF

ANALYSIS OF VIA TO VIA CROSSTALK FOR
SINGLE ENDED SIGNALS IN THE TIME &

FREQUENCY DOMAINS
FADI DEEK, MENTOR A SIEMENS BUSINESS.

ERIC BOGATIN, TELEDYNE LECROY
CHUCK FERRY, MENTOR A SIEMENS BUSINESS
CRISTIAN FILIP, MENTOR A SIEMENS BUSINESS
MELINDA PIKET-MAY, UNIVERSIT Y OF COLORADO AT BOULDER
Originally presented at DesignCon 2019. Reprinted with permission.
W H I T E P A P E R
P C B D E S I G N
w w w . m e n t o r . c o m
Analysis of Via to Via Crosstalk for Single Ended Signals in the Time & Frequency Domains
ABSTRACT
At today’s fast switching data rates via to via crosstalk through the PCB cavities can be more profound than trace to
trace coupling.
This work offers an analysis of the physical basis of the root cause behind via to via coupling using simulations and
measurements of test boards to illustrate the principles. Based on the root cause, methods to mitigate the noise are
explored and demonstrated.
The return current of a signal passing through a via will generate a radial wave that propagates through the cavity
and as a result encounter the impedance of the cavity. With this root cause identified, the coupling between the
vias is broken into three constituents: the radial wave coupling, excitation of cavity structural resonances and
excitation of lumped resonances. Lumped resonances result from the interaction of the cavity with components
such as DC blocking capacitors and return vias. Each of the three mechanisms is analyzed to provide an
understanding of its electrical signature and contribution to the overall crosstalk.
Novel designs for physical test boards and SMA launch fixtures are used to isolate the effects of the via to via
coupling. To explain the concepts and demonstrate the validity of the results, S-Parameters are captured using an
Anritsu Shockline MS46524B network analyzer (VNA) and time domain measurements are collected using a
Teledyne LECroy WavePro HD 12-bit scope. Correlation to simulations using HyperLynx is also provided to further
validate the results.
AUTHOR(S) BIOGRAPHY
Chuck Ferry manages a product engineering group at Mentor a Siemens Business focused on architecting system
level signal and power integrity analysis solutions. He has spent the last 21 years tackling a broad range of high
speed digital design challenges spanning from system level mother board design to multi-gigabit channel analysis
incorporating detailed characterizations of the IC, packages, connectors and multiple boards. Chuck graduated
Magna cum laude from the University of Alabama with a B.S.E in electrical engineering and continued graduate
course work in the areas of signal processing and hardware description languages
Cristian Filip joined Mentor Graphics Corporation in 2014 as a Product Architect for high-speed products. His
interest includes high-speed serial link design, modeling and simulations of DDR memory interfaces as well as
power integrity. Prior to joining Mentor, Cristian was a Senior Hardware Engineer specializing in signal and power
integrity at General Dynamics Canada in Ottawa. Cristian holds a M. Eng. In Electronics and Telecommunications
from the Polytechnic University, Timisoara, Romania and is member of Professional Engineers Ontario. He has
co-authored the “BER-and COM-Way of Channel-Compliance Evaluation: What are the Sources of Differences?” and
“Efficient Sensitivity-Aware Assessment of High-Speed Links Using PCE and Implications for COM” papers and won
the DesignCon Best Paper Award in 2016 and 2018.
Eric Bogatin is currently a Signal Integrity Evangelist with Teledyne LeCroy, Dean of the Teledyne LeCroy Signal
Integrity Academy, an Adjunct Professor at the University of Colorado - Boulder in the ECEE dept and the editor of
the Signal Integrity Journal. Bogatin received his BS in physics from MIT and MS and PhD in physics from the
University of Arizona in Tucson. He has held senior engineering and management positions at Bell Labs, Raychem,
Sun Microsystems, Ansoft and Interconnect Devices. He has written six technical books in the field and presented
classes and lectures on signal integrity worldwide. In 2011, his company, Bogatin Enterprises, which he founded
with his wife, Susan in 1990, was acquired by Teledyne LeCroy. After concluding his live public classes in 2013, he
devoted his efforts into creating the Signal Integrity Academy, a web portal to provide all of his classes and training
content online, for individuals and for companies
Fadi Deek received his B.S degree in computer and communications in 2005. That same year, he joined Fidus
Systems as a design engineer. He designed circuit boards at Fidus for three years. In 2010, he received his M.S. in
w w w. m e nto r. co m
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Electrical Engineering from the University of Arkansas in Fayetteville. He then joined Mentor, A Siemens Business, as
a Corporate Marketing Engineer. In 2013, Fadi became a corporate application engineer supporting the HyperLynx
and the Analog Mixed Signal tool suites. In parallel, he is also pursuing his Ph.D. at the University of Colorado in
Boulder specializing in Signal and Power Integrity.
Melinda Piket-May (S’89, M’92, SM’99 of IEEE) received her BSEE from the University of Illinois - Champaign in 1988
and her MSEE and PhD in Electrical Engineering from Northwestern University in 1990 and 1993. She is a tenured
member of the ECEE Department at the University of Colorado Boulder which she joined in 1993.
INTRODUCTION
Today’s high-speed requirements have imposed tight constraints for PCB design. Engineers are continuously trying
to minimize the board size and number of layers to reduce cost. In order to support the multi-functional products,
more components need to be densely placed within the ever shrinking real estate of the PCB. Moreover, signal
switching has become faster than ever before generating high bandwidth signals that need to share the same
reference planes with other signals.
Applications such as internet of things (IoT) where digital and analog signals can interfere with each other have
isolation requirements that can reach -100 dB. Other digital applications that employ, for example, PAM-4 encoding
schemes have isolation requirements close to -50dB.
Due to the above mentioned, noise sources coming from the interaction of vias with cavities can no longer be
ignored.
THEORY AND ANALYTICAL MODEL

As a signal propagates on a transmission line, its return current is well known to be located on the adjacent
reference plane. In the case the signal needs to switch layers through a via, the return current will need to do that
as well.
Consider a bare cavity that has no return vias or DC blocking capacitors as shown in Figure 1. The return current
can only pass through the cavity as a displacement current. This phenomena is the same manner that a current
propagates through a capacitor, and in addition, the return current in the cavity will propagate.
Figure 1 Signal Via passing through PCB cavity
As the return current switches from layer to layer it spreads out radially between the planes of the cavity. Thus, the
return current encounters the impedance of the cavity.
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IMPEDANCE OF A CAVITY
Although a PCB cavity is composed of two adjacent planes with a dielectric in between, the impedance of the
cavity is capacitive only at low frequency.
Frequency domain parameters such as Z-Parameters or S-Parameters provide an insightful means to inspect the
impedance profile of a cavity.
To explain what the impedance profile of a PCB cavity might look like, a simulation was run for a 2 layer cavity. The
dielectric medium used was Dk = 4.3 and a dielectric thickness was 20 mils. The board height was 2 inches and its
width 3.5 inches. A probe is placed at the center of the cavity with each terminal connected to 1 plane of the
cavity.
Figure 2 Example PCB probed from center
A simulation is run up to 5GHz and the resulting Z-parameter is shown in Figure 3. As expected, the cavity will
behave as a capacitor at low frequencies. As a wave propagates through the cavity it will see the inductance of the
conductor planes [1]. This inductance in series combination with the capacitance of the cavity creates a series
resonant dip at 269 MHz. Beyond that self-resonance the cavity becomes mostly inductive. However, since the
cavity is a resonant structure standing waves will start to build up inside the cavity. The plot in Figure 3 shows the
effect of those resonant modes as high impedance peaks.
Figure 3 Z-parameter of 3.5x2 inche 20 mil thick cavity
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Those standing waves are resonant modes depend on the height, the width and the dielectric medium inside the
cavity. They can be predicted using equation 1 shown below
eq(1)
where ωres is the resonant frequency and v is the speed of light in the medium, m and n are the modal indices.
In real world situations, several components such as DC blocking capacitors and voltage regulator models perturb
the impedance of the cavity. For example, a DC capacitor will have a total mounting inductance composed of the
inductances of the vias connecting the pads of the capacitor to the planes of the cavity, the traces routed to the
vias, the pads of the component footprints and the actual capacitor itself. This total mounting inductance will
combine in parallel with the inter-plane capacitance of the cavity and cause parallel resonant peaks in the
Z-Parameter profile. This will be shown more in the measured results in the next section.
TWO LAYERS BOARD SETUP

In order to isolate the effect of coupling through the PCB cavity a variety of 2 layer boards were designed with
copper planes on top and bottom. The dielectric medium thickness is fixed at 20 mils for all the different variations.
The length and width of the boards are also fixed to 3.5 inches x 2 inches respectively. An example of a simple
board is shown in Figure 4. The via in the center of the board, marked as U1, clears away from both planes. The
purpose of the discrete components is to mimic the effect of any decoupling capacitors and the voltage regulator
modules (VRM).
Figure 4 Two Layer PCB. Top graphic: Top view; Bottom graphic: Crossectional view
In order to probe the via using a vector network analyzer (VNA) SMA connectors are soldered to the surface mount
pads on each of the Top and Bottom layers. Each SMA connector’s reference pins connect to only 1 plane as shown
in the top graphic of Figure 4 and Figure 5. Hot glue melt was later used to provide better mechanical stability of
the SMA as shown in the bottom graphic of Figure 5. The latter setup was measured with the VNA.
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Figure 5 Manufactured 2 layer board. Top graphic: SMA mounting scheme; Bottom graphic: Measured board with glue
Several variations of this 2 layer board were built, measured and analyzed as discussed in later sections of this
paper.
VALIDITY OF SMA CONNECTOR SETUP

Although the SMA connectors are meant to be soldered as through-hole components, it was important that the
pins were only soldered to the surface of each plane layer. The main reason behind doing that is to remove any
influence of the return pins between the PCB cavity and the center conductor via. In addition, by keeping the PCB
planes isolated forces the return current of the signal that propagates through the center via to pass through the
cavity as a displacement current. This allows us to see the true effect of the bare cavity impedance on any signal
propagating on a signal-via that passes through that cavity.
However, because of this surface mount setup, an impedance discontinuity is introduced by the section of the SMA
in which the center conductor propagates through air. This section has a higher impedance than 50 ohms. In order
to minimize that impedance discontinuity, we made sure the glue filled the entire area around the center
conductor. This made the SMA connection to be more capacitive which helped in reducing the impedance of that
section.
In order to observe the impact of the SMA’s, a pair of them were soldered back to back as shown in Figure 6. As can
be seen, one configuration had glue surrounding the center conductor and the other had no glue. The two
configurations were measured using the VNA and the S-Parameters were converted into a TDR impedance plot
shown in Figure 7. The plots show that the impedance of the SMA section with no glue surrounding the center
conductor is almost 90 ohms, at the rise time of about 100 psec. The configuration with glue shows an impedance
of 71 ohms at the same rise time. This had a big impact on the quality of the insertion loss (IL) and return loss (RL).
As can be seen in Figure 8, the case when the glue was used the RL was still below -10dB in magnitude all the way
up to 10 GHz. On the other hand the return loss of the configuration without glue crossed the -10dB point at
around 2 GHz.
In addition to the glue, mounting the SMA to the PCB pads added more capacitance and made the discontinuity
impedance even smaller. This will be discussed in more detail shortly.
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Figure 6 SMA measurement setup. Left configuration has glue; right configuration has no glue
Figure 7 TDR Impedance converted from measured S-Parameters. Blue is without glue, red is with glue. Effective rise time is about
100 psec, using a 10 GHz measurement.
Figure 8 Measured magnitude in dB of IL and RL. Blue is without glue, red is with glue
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FREQUENCY DOMAIN ANALYSIS

Frequency domain analysis presents a convenient way to look at the impedance behavior of the cavity as discussed
in an earlier section. For that purpose S-Parameters were captured using an Anritsu Shockline MS46524B 4 port
VNA. The different variations of the 2 layer boards which include: a bare board with only 1 center signal via,
multiple signal vias, DC blocking capacitors and a stitching via close to the aggressor signal vias.
BARE BOARD
The first simple setup to be considered is shown in the bottom graphic of Figure 5. Ports 1 and 2 of the VNA were
connected to the top and bottom SMAs respectively as shown in Figure 9 below. Initially no discrete components
were populated on the board.
Figure 9 VNA measurement setup
Looking at the measured S-Parameters, the insertion loss S21 and return loss S11 are plotted in Figure 10 from
500KHz up to 10 GHz. As expected the |S21| is close to 0dB at DC whereas |S11| is a very low number. A resonant
peak appears at around 8 MHz as shown in the close up image.
This resonance is due to the loop inductance of the VNA cables resonating in parallel with the interplane
capacitance of the cavity. It is an artifact of the measurement setup since there is no DC path between the two
planes that make up the cavity and the return paths of the two VA cables.
This loop inductance of the roughly 1 meter diameter loop made by the two cables is estimated as about 3 m
circumference x 3 nH/mm, or about 0.9 uH.
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From the resonant frequency, the extracted inductance is 1.17uH using equation (2) below. This is in close
agreement to what is expected
eq(2)
Moving up higher in frequency, the cavity becomes more reflective. The magnitude of the measured |S11| crosses
the -10dB point at around -4.5dB and becomes higher than |S21| at around 7.6GHz. This is expected due to the
impedance of the spreading inductance of the cavity in addition to the inductance of the center via and SMA
conductor. A comparison of the |S11| and |S21| for the bare board, in red, and the back to back SMA, in green, is
shown in Figure 11. As the figure shows when mounted on the board, the SMAs and bare cavity are less reflective
than just the back to back SMAs filled with glue. This can be seen clearly up to 4.42GHz which is when the
impedance of the cavity dominates that of the SMAs.
Figure 10 Measured magnitude in dB of S-Parameters of Bare Board. Red is |S11|, blue is |S21|
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Figure 11 Measured |S21| and |S11|. In red bare board, in green SMA
Excellent agreement between measurement and simulation using HyperLynx is shown in Figure 12. The measured
results, shown in red, have the SMA models de-embedded from them. The simulation plots, in blue, show the
effect of the cavity on the return path of the via without any SMA models connected to the vias. The agreement
strongly validates the measured results.
Figure 12 Measured vs Simulated magnitude in dB of S-Parameters of Bare Board. Red is de-embedded measurements, blue is
simulated using HyperLynx
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The energy that is trapped in the cavity will be mainly absorbed by losses in the modal resonances. Therefore, the
best means to measure the location of the cavity resonances is to use a power loss parameter. This can be
calculated, for example, for port 1 as provided by equation (3) below
eq(3)
The plots in Figure 13 compares the power loss with the insertion loss for the bare cavity. It shows perfect
agreement as far as the location of the resonances is concerned. This means that the insertion loss plots can also
be used to measure the frequency location of the resonances. The first 4 resonant modes are marked on the graph
as well.
To predict the resonant frequencies and their respective indices, equation (1) is used. Since the signal via is located
in the center of the cavity, only the even indexed resonances will be excited.
The results in the first column in Table 1 shows the first 5 resonant modes calculated using a fixed Dk = 4.3. This
value is the Dk provided by the PCB vendor.
Figure 13 Bare board. Red is measured |S21|, Orange is calculated |Sloss|
The first thing to notice is that the modes with indices (0,4) and (2,2) appeared to be combined in the measured
plot of Figure 13. This is because the difference in frequency between these 2 modes is only 30 MHz and thus they
appeared as 1 degenerate mode that has the combined energy of both modes. This can be seen clearly in the
|Sloss| plot of Figure 13 where the 3.35GHz mode has a greater magnitude than the 2.87 GHz mode although it is
higher in frequency. Since loss is frequency dependent and should increase with frequency, higher frequency
modes should have greater |Sloss| magnitude than lower frequency modes. The close up image in the bottom right
corner of Figure 13 shows a slight deviation in the slope of the |Sloss| curve. It is close to the 3.3 GHz resonance
where the (0,4) mode would be.
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Table 1 Cavity modal resonances
The second important fact that Table 1 conveys is that using the vendor provided fixed Dk = 4.3 value in equation
(1) does not predict the resonant frequencies with high accuracy. This is shown in the left most 2 columns of the
table. The biggest difference is almost 2% for the (2,4) modal index between those 2 columns.
Using the modal indices and the measured resonant frequencies, the Dk at each frequency can be extracted. The
right most two columns shows the extracted Dk value and the new calculated frequency resonance rounded to
the second decimal.
BOARD WITH 5 VIAS

For the purpose of capturing via to via coupling through the cavity a 2 layer board with the same dimensions and
properties as the one discussed above is constructed. Instead of 1 via, 5 signal through vias were spread around
different locations of the board as shown in Figure 14. How the location of each via was chosen will be discussed
shortly.
Figure 14 Two layer board with 5 through vias. Coordinates in inches
In order to understand how to probe such a configuration the equivalent circuit is drawn in Figure 15. Via 1
represents any via that would be connected to the VNA ports. Since there are only 4 ports on the VNA used, ports
1 and 2 are always connected to the top and bottom SMAs of the center via located at (1.775,1.025). This via will be
used as the aggressor via.
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Figure 15 Equivalent Circuits. Via 1 represents vias connected to VNA, Via 2 represents vias not connected to VNA
The remaining two VNA ports will be swapped between the other 4 victim vias. The main question is whether to
terminate or leave open the other SMAs that are not connected to the VNA. In order to minimize reflection back to
ports 3 and 4 from open ended vias, all the victim vias that are connected to the VNA have 50 ohm terminations.
The other victim vias cannot be left open since they will become resonators passing through the cavity and
coupling energy out, at their resonant frequency. Instead one 50 ohm termination is used to dampen those
resonators. That 1 termination is only connected to one SMA of the victim via and the other SMA is left open. This
prevents loading the cavity with a 100 ohm resistor in shunt.
In order to see the effect of the resonators the |S21| of the board with 5 vias is plotted in Figure 16.
Figure 16 Measured |S21| and |S11|. Blue is board with 4 vias terminated, green with 4 vias left open
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In both measurements, ports 1 and 2 of the VNA were connected to the top and bottom SMAs of the center via in
both situation. However, for the blue plot, the victim vias were terminated using 50 ohms at one end whereas for
the green plot the victim vias were left open. Given the SMA stub length of 0.92 inches, and an estimated Dk of 2.5
for the SMA path, the ½ wave resonance of the SMA stub is about 4.1GHz.
These stub resonances are seen at 3.88GHz, close to what is expected, where the open ended vias with SMA stubs
attached, resonate and cause the extra dip in the green |S21| plot. The blue plot shows that resonance completely
damped out by the 50 ohm terminations. As a result, the VNA measurements were taken with terminations placed
at any open vias.
For the purpose of probing the sensitivity of the via location to the different modal resonances, the via coordinates
were chosen according to the plots in Figure 17. The spatial distribution of the voltage amplitude is plotted for the
first 4 modes of indices (0, 2), (2,0), (0,4) and (2,2) which correspond to the 1.65 GHz, 2.89 GHz and 3.35 GHz
degenerate mode respectively.
Figure 17 Spatial Distribution of voltage amplitude for the first 4 resonant modes
As can be seen from the plots, each mode has locations on the board where it has a peak voltage and other
locations where it is a 0V. This means if a via is located in 0V node it would be insensitive to that mode. If that via is
located anywhere else then it would be sensitive to that mode with varied intensity.
For example, via U4 is located along the 0V line of the modal resonances (2,0), (0,2) and (2,2). This means if via U1
excites those modes from the center via U4 should have little coupling at the 1.65GHz, 2.87 GHz and the 3.35 GHz
frequencies. Vias U2, U3 and U5 should couple to all those 4 modes since they are not located at 0V nodes.
To explain this using the measured S-Parameters, the magnitude of the coupling coefficient between aggressor via
U1 and all the other vias is plotted in Figure 18. A close up at the first resonance mode of 1.65GHz is shown in that
image. As expected the coupling coefficient to via U4 in blue is the least between all the vias. On the other hand,
U5 is located at a voltage peak of that mode and thus has the highest coupling. In comparison to U5, vias U2 and
U3 are located further away from the voltage peaks and thus there coupling is less.
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Figure 18 Magnitude of Coupling coefficients for (2,0) mode. In orange between U1 and U2, in red between U1 and U3, in blue
between U1 and U4, in green between U1 and U5
BOARD WITH 3 VIAS AND RETURN PATH VIA NEAR AGGRESSOR

A second perturbation to the bare board is to add a return path via close to the aggressor center through via. To
explain the full effects of the return via the PCB configuration shown in Figure 19 is used. The return via is 70 mils
diagonally away from the center via and shorts the planes on top and bottom.
Figure 19 Bare board with 3 vias and return path via near center aggressor
The return via should provide a low impedance return path for the aggressor current. However the via itself has an
inductance which will add to the spreading inductance of the wave radiating out from the center via. This net
inductance will create a parallel resonance with the inter-plane capacitance. Also, since the return via is really close
to the excitation, less of that initial energy is going to be dissipated into the cavity. Thus, each resonant mode
should absorb less energy compared to the case with no return path vias.
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In this board configuration, ports 1 and 2 of the VNA were connected to the SMAs on each side of the center via.
Ports 3 and 4 were connected to the bottom SMAs of vias U2 and U3 respectively. The top side SMAs of vias U2
and U3 were terminated with 50 ohms.
With the shorting via between the plane, the 1.1 uH cable loop inductance is shorted out, so it should not be
present in the insertion loss for this configuration. Instead, a higher frequency parallel resonance should be present
due to the shorting via’s inductance and cavity capacitance. Assuming the via loop inductance is about 1 nH/mm x
0.5 mm = 0.5 nH, the parallel resonant frequency should be about 387 MHz.
The measurements of the |S21| and calculated |Sloss| through port 1 for the board with the return via and the
previous board with 5 vias without any stitching is compared in Figure 20.
Figure 20 Red and purple are |S21| and |Sloss| for board with 3 through vias and one return via, Blue and cyan are |S21| and |Sloss|
for board with 5 vias
Looking at the cavity resonances, it can be seen that the depth of the dips is less in the red |S21| stitched board vs
the blue |S21| board with no stitching vias. The power loss parameters can help clarify this effect better. The purple
plot is the |Sloss| parameter for the board with the stitching. The cyan plot is |Sloss| for the board with no stitching.
It can be seen that the resonances peak higher in the cyan plot when compared to the purple plot. This is because
more energy couples into the cavity and gets absorbed by the resonant modes when there is no return via. The
existence of the return via restricts the coupling of energy into the cavity and thus the resonant modes have less
energy available to absorb.
Secondly, we see the 8 Mhz resonance is gone, and the 374 MHz resonance is present, close to the estimate of 387
MHz due to the shorting via and the cavity.
Another effect of the stitching via is that it adds a new shorting boundary condition at the center of the cavity. This
has the effect of shifting the frequency location of the resonant modes to slightly higher frequencies.
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BOARD WITH 5 VIAS AND 10NF CAPACITOR

In the practical situation when the two planes of a cavity are of a different potential, using return vias is not an
option. Instead DC blocking capacitors are used to provide the AC path. As discussed in the theoretical section, the
mounting inductance of a capacitor will have the biggest effect at low frequencies. A close analogy can be drawn
here between the inductance of the return path via discussed earlier and the mounting inductance of the
capacitor. The only difference is that the capacitor’s mounting inductance will be higher than that of stitching via.
The expected impact from the DC blocking capacitor connected between the two planes should be to introduce a
low-frequency self-resonant impedance profile and shift the parallel resonant frequency lower, due to the higher
inductance between the two planes.
To explore those effects, a 10 nF DC blocking capacitor was soldered to the C1 component in the bottom right
corner of the board with 5 vias in Figure 14. The VNA is connected to the board in the same manner as discussed
earlier. The measured |S21| and calculated |Sloss| for the new board configuration is shown in red and purple
respectively in Figure 21.
These are results are compared to the cases with no DC blocking capacitors and are plotted in the blue and cyan
colors for |S21| and |Sloss| respectively.
Beyond its self-resonance frequency, the DC blocking capacitor starts behaving like an inductor. It creates a parallel
resonance peak dominated by the interaction between its total mounting inductance and the inter-plane
capacitance at 200MHz. This is as expected due to its higher inductance between the two planes compared to the
single shorting via.
In addition to the above effect, the mounting inductance of the DC blocking capacitor introduces 2 new
resonances at 1.75GHz and another at 3.03GHz. These new modes absorb energy away from their neighboring
cavity resonances that are at 1.65 GHz and 3.35GHz. This effect can be seen in the |Sloss| plots were the peaks of
the cavity resonances in the purple plot for the case with the capacitor is below the cyan plot which is for the case
with no capacitors.
The reason that those new resonances are showing at those specific frequencies is because the vias connecting
the capacitor is changing the boundary conditions at that specific location. This is creating a new low impedance
boundary condition that is 79 mils away from the right vertical edge of the board in the X-direction and 43 mils
away from the bottom horizontal edge of the board in the Y-direction. The boundary conditions are a lower
impedance of about 20 Ohms and open at all others.
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Figure 21 Red and purple are |S21| and |Sloss| for board with 5 vias and capacitor, Blue and cyan are |S21| and |Sloss| for board
with 5 vias
The coupling between the center aggressor via and the other victim vias due to the 200 MHz LC resonance is
shown in Figure 22.
Figure 22 Magnitude of Coupling coefficients at 200 MHz resonance for board with C1 = 10nF. In black is |S21|, in orange between
U1 and U2, in red between U1 and U3, in blue between U1 and U4, in green between U1 and U5
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As can be seen from the figure all the different victim vias couple with almost the same magnitude. This is due to
the fact that the entire cavity responds to the LC resonance exactly the same, no matter where the victim via on
the board is.
TIME DOMAIN ANALYSIS

A Teledyne LECroy WavePro HD 12-bit scope with an 8GHz bandwidth was used to capture time domain
measurements of the coupling between the different vias. The scope has the capability to source a 300 ps 0.5 Volt
rising edge into a 50 Ohm load. Its source impedance is 50 ohms. The bandwidth of such a signal can be calculated
using the equation B.W. = 0.35/R.T. where R.T. is the rise time in ns. This yields a B.W. = 0.35/0.3 = 1.17 GHz.
The scope has 4 channels and a source channel. Both the source channel and channel 1 were connected to each
SMA of the center via U1 in all the measured boards. For the victim vias, a 50 ohm termination was always present
on one SMAs. The other SMAs either had a scope channel connected to it or was terminated with another 50 ohm
SMA.
When the scope is connected to the board with no shorting via between the planes, the return current is
ultimately connected through the cables of the scope, which are also 1 meter long. We expect to also see a
resonance at about 8 MHz, corresponding to the parallel resonance of the cavity capacitance and the roughly 1 uH
of cable loop inductance.
The measured received waveform through the cavity, at U1 is shown in Figure 23. As can be seen the voltage
settles at 500 mV. The 8 MHz resonance that was measured using the VNA is excited and generates ringing of half a
period of 70 ns.
Figure 23 Scope excitation source measured from the bottom SMA connected to U1
BOARD WITH 5 VIAS

When the step edge signal passes through the aggressor via, it excites the entire cavity with the parallel resonance.
All regions of the cavity resonate with the same voltage so the noise picked up on each of the victim vias should
be the same.
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Figure 24 Scope measurement of coupling between vias. In orange between U1 and U2, in red between U1 and U3, in blue
The measured couple noise measured between the center via and the 4 other victim vias is shown in Figure 24. The
DC offset between the different waveforms is due to the slight DC offset of the scope channels. The peak
amplitude varies between 1.8 mV to 2 mV at each via. The 8 MHz, 70 ns half period, oscillation of the cavity is the
mechanism which couples noise in each victim via.
A close up of the first 5 ns of the coupled noise in Figure 25 reveals more about the features contributing to the
coupled noise. First as can be seen, the orange waveform which is the signal measured at via U2 arrives the earliest
in time since it is the closest via to the aggressor U1. The farthest away is U3 and arrives the latest in time as shown
in the blue waveform.
Since the bandwidth of the source signal is only up to 1.17 GHz, the first resonant mode at 1.65 GHz will be barely
excited. The second mode at 2.88 GHz will have even less energy. The ringing on the victim vias U2 in orange, U3 in
blue and U5 in green waveforms is measured to have a period of 630 ps which is almost 1.6GHz.
Victim via U4 is located at a 0V node and is insensitive to that mode. However, the ringing on the U4 waveform has
a period close to 320 ps. This corresponds to almost 3.125 GHz which is actually the (0,4) mode which also gets
excited but to a much lesser degree.
20
Figure 25 Scope measurement of coupling between vias. In orange between U1 and U2, in red between U1 and U3, in blue
A close up into the coupling between vias U1 and U5 is shown in Figure 26. The blue plot is the result of the
simulation using HyperLynx and shows excellent agreement to the measured waveform using the Scope. Both
measured and simulated results show that the ringing on the coupled waveform is due to the 1.65GHz cavity
resonance.
Figure 26 Scope measurement vs simulation of coupling between vias U1 and U5. Blue is simulated using HyperLynx, green is
measured
21
Next the 10 nF capacitor is soldered to the board. Energy in the aggressor step edge signal at 200 MHz will couple
into the cavity, excite the cavity-capacitor inductance resonance at 200 MHz, and be picked up by the victim vias.
Since the entire cavity contributes equally to this resonance, each victim via should see the same noise.
The measured waveforms in Figure 27 show the effect of the oscillations that have a half period of 2.5ns which
corresponds to a frequency of 200 MHz.
Figure 27 Scope measurement of coupling between vias with C1 =10nF. In orange between U1 and U2, in red between U1 and U3,
in blue between U1 and U4, in green between U1 and U5
The amplitude of the coupled to noise to all the 4 victim vias is almost the same no matter what their location is.
The peak to peak voltage measured is 16 mV which is almost 3%. This is generated by 1 via driving the cavity with
only 1 step edge.
BOARD WITH 3 VIAS AND RETURN PATH VIA NEAR AGGRESSOR

The board with 3 vias and a return path via shown in Figure 19 was stimulated and measured with the scope. The
source channel and channel 1 of the scope were connected to the top and bottom SMAs of the center via.
Channels 2 and 3 of the scope were connected to vias U2 and U3 from one side and the other side terminated with
50 ohms.
The parallel resonance introduced by the via was measured with the VNA to be 374 MHz. We expect the step edge
to stimulate this cavity resonance and all the victim vias to pick up equal energy at this frequency. There might also
be additional coupling at the higher structural modal resonances.
As can be seen in Figure 28, oscillations of a period 2.6ns build up and have a maximum peak to peak voltage of ~
6mV. The excitation of the higher frequency cavity resonant modes is barely visible on the oscillating waveform.
This is due to the effect of the stitching via that reduced the amount of energy that propagates through the cavity
and excites the resonant modes.
22
Figure 28 Scope measurement of coupling between vias on board with return vias. In blue between U1 and U2, in red between U1
and U3
CONCLUSION
The impedance of a PCB cavity has a complex profile in the frequency domain. At low frequencies it behaves as a
capacitor and at higher frequencies it is inductive with resonant modes.
A 2 layer board with isolated planes provides a great test case to isolate the effects of the cavity on a signal
propagating on a via passing through the cavity. Surface mount SMAs provide a good means to probe the cavity
without introducing any perturbations on the cavity’s impedance.
Adding DC blocking capacitors or return path vias perturbs the impedance of the cavity. Due to the inductance of
such elements, new parallel resonances will be introduced.
When driven by a signal with sufficient bandwidth the resonances get excited and oscillations build up. The VNA
measurements showed the location of the resonances and the scope measurements showed how those
resonances can get excited by a 300 ps signal.
When excited, the low frequency resonances due to the return vias or the DC blocking capacitors will generate a
noise that will be picked up anywhere across the cavity. This means separating the aggressor and victim vias will
have no effect on that coupled noise. The high frequency cavity resonances can be avoided by placing victim vias
close to 0V nodes. The location of those nodes can be located by looking at spatial distribution plots. The
magnitude of the coupled noise presented in this work reached a maximum of 3% of the excitation signal.
However, this is due to only 1 single via switching only once with a low bandwidth signal. In practical situations
signals will have higher frequency bandwidth and multiple vias will be switching simultaneously and for longer
periods of time. This will yield much higher noise levels that will cause many design margins to be exceeded.
23
REFERENCES
1. E. Bogatin, L. Smith, Principles of Power Integrity for PDN Design Simplified. Prentice Hall, 2017.
2. F. Deek, M. Piket-May and E. Bogatin, “Transfer Impedance Drop off in Power/Ground Plane Cavities,” 2018 IEEE
Symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity (EMC, SI & PI), Long Beach,
CA, 2018, pp. 105-109.
3. HyperLynx,https://www.mentor.com/pcb/hyperlynx/
For the latest product information, call us or visit: w w w . m e n t o r . c o m

©2018 Mentor Graphics Corporation, all rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation and may
be duplicated in whole or in part by the original recipient for internal business purposes only, provided that this entire notice appears in all copies.
In accepting this document, the recipient agrees to make every reasonable effort to prevent unauthorized use of this information. All trademarks
mentioned in this document are the trademarks of their respective owners.
MGC 06-19 TECH18270-w

Analysis of Via To Via Crosstalk For Single Ended Signals in The Time & Frequency Domains PDF

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ANALYSIS OF VIA TO VIA CROSSTALK FOR

SINGLE ENDED SIGNALS IN THE TIME &

FADI DEEK, MENTOR A SIEMENS BUSINESS.

Originally presented at DesignCon 2019. Reprinted with permission.

THEORY AND ANALYTICAL MODEL

Figure 1 Signal Via passing through PCB cavity

Figure 2 Example PCB probed from center

Figure 3 Z-parameter of 3.5x2 inche 20 mil thick cavity

TWO LAYERS BOARD SETUP

VALIDITY OF SMA CONNECTOR SETUP

FREQUENCY DOMAIN ANALYSIS

Figure 9 VNA measurement setup

Figure 13 Bare board. Red is measured |S21|, Orange is calculated |Sloss|

Table 1 Cavity modal resonances

BOARD WITH 5 VIAS

Figure 14 Two layer board with 5 through vias. Coordinates in inches

BOARD WITH 3 VIAS AND RETURN PATH VIA NEAR AGGRESSOR

BOARD WITH 5 VIAS AND 10NF CAPACITOR

TIME DOMAIN ANALYSIS

BOARD WITH 5 VIAS

BOARD WITH 3 VIAS AND RETURN PATH VIA NEAR AGGRESSOR

For the latest product information, call us or visit: w w w . m e n t o r . c o m

MGC 06-19 TECH18270-w

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