CONCEPTS OF SIGNAL INTEGRITY:

IMPEDANCE

MENTOR, A SIEMENS BUSINESS

W H I T E P A P E R

P C B D E S I G N

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Concepts of Signal Integrity: Impedance

INTRODUCTION
Successful signal integrity analysis depends on a fundamental concept: impedance. Without a thorough
understanding of the impedance values that a signal encounters along the way, designers cannot maintain good
signal quality from source to receiver.

In this paper, we’ll define the difference between characteristic and instantaneous impedance and explore the
essential principles of impedance and design-controlled impedance using transmission lines as an example. We’ll
investigate the impedance of two of the most common transmission lines, striplines and microstrips, using an
advanced high-speed analysis tool to explain how the different parameters of each transmission line type affect
time delays and characteristic impedance.

The output impedance of the driver is the first impedance a signal sees as it propagates from the source. This paper
equips the reader with an easy way to derive the output impedance.

Finally, the parasitics of the package leads and the on-die capacitance can also have a great effect on the signal
quality, especially at high speeds. In order to understand their effect, those features are extracted from the IBIS
model.

CHARACTERISTIC IMPEDANCE VS. INSTANTANEOUS IMPEDANCE

A transmission line, or a trace on a printed circuit board with its associated return path, is electrically defined by
two properties: its characteristic impedance, or Z0, and its time delay, TD.

As a signal propagates down the signal and return path, it will continuously encounter an instantaneous
impedance. This means the signal will apply a voltage and drive a current through each infinitesimal section of the
transmission line as shown in Figure 1.

Figure 1: Signal traversing a transmission line.

The impedance the signal sees is the instantaneous impedance. In a uniform transmission line, the instantaneous
impedance is the same each step along the transmission line. That single impedance value is the characteristic
impedance of the transmission line. This means that a non-uniform transmission line is characterized by more than
one impedance.

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A STRIPLINE EXAMPLE
So, what elements of the transmission line can affect its impedance? To answer the question, a stripline
configuration will be used.

For the analysis covered in this section, the embedded field solver in HyperLynx® LineSim® was used to model
several types of transmission lines, wires, cables and connectors. One of the options available is a stripline modeler
shown in Figure 2.

Figure 2: Stripline modeler.

HOW DOES EACH TERM AFFECT THE Z0 AND THE TD?

The two dielectric height parameters will affect the capacitance per length of the trace by the following rough
approximation, C = εw/H, where ε is the material permittivity, w is the width of the conductor, and H is the height
or the separation between each conductor. By decreasing any of the heights H1 or H2, the capacitance will
increase.

The connection between the characteristic impedance and the capacitance per length is Z0 =√(L/C). Any increase in
the capacitance per length will decrease Z0.

Also, the width of the trace, if increased, will decrease Z0 since it will increase the capacitance per length.

Another factor that will affect the capacitance per length is the dielectric constant. From the capacitance
approximation, any increase in ε will increase the capacitance per length.

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Concepts of Signal Integrity: Impedance

The length of the conductor will not affect Z0 since, as mentioned before, the instantaneous impedance is constant
in a uniform transmission line.

Other parameters will have some effect on the impedance, but it will be minimal. As an experiment, Table 1 shows
the impact on characteristic impedance from a 10% change in each parameter. The initial nominal values of the
parameters produced a 49.6-ohm impedance. To capture the new impedance, only one parameter was changed at
a time and then reset to its initial value. Only H1 was varied, since the impact of H2 would be identical.

We would expect that the things that affect capacitance per length the most would have the biggest impact. An
item like dissipation factor should have no impact on the characteristic impedance at all.

As can be seen from Table 1, the dielectric constant and line width had the biggest impact whereas the loss
tangent had no impact at all.

Parameter Initial value for 10% increase New Z0 % change in Z0

Z0 = 49.6
T 1.35 1.485 49 1.2
W 5 5.5 47.6 4
H1 7 7.7 50.7 2.2
Er 4.3 4.73 47.2 4.8
Lt 0.02 0.022 49.6 0

Table 1: Comparison of parameter effect on Z0 due to 10% increase.

When it comes to the time delay, TD, the characteristic impedance will have no impact. Only the length of the
transmission line and the dielectric constant are expected to have an effect. The velocity of the signal can be
calculated using v=c/√(ε_r) where c is the speed of light in air. This formula shows that the velocity and the
dielectric constant are inversely proportional. Other than that, the rest of the parameters should have no impact on
the TD.

To explore this, another experiment was conducted to determine which parameter might have a bigger impact. A
10% increase was applied to each of the parameters. Starting from a 527 ps TD, the results are shown in Table 2.
Note that the length of the stripline had the biggest impact on the TD. An increase in the dielectric constant
slowed down the velocity and thus the transmission line appeared to be longer. Other parameters had no impact
at all, exactly as expected.

Parameter Initial value for 10% increase New TD % change in TD

TD = 527 ps
L 3 3.3 579.8 10
T 1.5 1.65 527 0
W 5 5.5 527 0
H1 7 7.7 527 0
Er 4.3 4.73 552.8 4.9
Lt 0.02 0.022 527 0

Table 2: Comparison of parameter effect on TD due to 10% increase.

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Concepts of Signal Integrity: Impedance

Another handy rule of thumb is the approximate ratio of the line width to the dielectric thickness that would
achieve 50 ohms. Using the stripline modeler, a few values were calculated for a stripline. The width of the trace
(W) and the total dielectric thickness (b) that is measured between the two reference planes were chosen so as to
keep a constant 50-ohm impedance.

The ratio W/b is plotted in Figure 3 versus b in the left plot and versus W in the right plot. As can be seen the ratio
varies slowly starting around 0.33. As a rough estimate, the ratio of line width to total dielectric thickness as 1/3 is a
starting point when designing the stack up of the stripline layers.

Figure 3: Ratio of width vs. total dielectric thickness W/b for a 50 ohm stripline: left plot is vs. b, right plot is vs. W.

DRIVER OUTPUT IMPEDANCE

A signal source can be simply modeled as a Thévenin equivalent voltage source as shown in Figure 4. Both models
have an output impedance ZS that will affect the signal being transmitted onto the transmission line.

Figure 4: Driver model: left, the Thévenin model, right, the Norton model.

A simple way to measure the driver output impedance is simply by using a voltage divider circuit. We first measure
the unloaded output voltage. Then we add a resistive load. As the resistance of the load is varied, we observe its
value when the output voltage drops 50%. This value of resistance is the output resistance of the driver.

First, it is important to find the unloaded output voltage level of the driver. In order to do that, an open-ended
driver was placed on the schematic and assigned to the desired buffer model as shown in U1.AF24 in Figure 5.

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Figure 5: Output impedance measuring circuit.

Every model has three different corners of operation: typical, slow-weak and fast-strong. A simulation was run and
the results are shown in Figure 6. As can be seen in red, the output of the driver of a fast-strong falling edge starts
at 1.4 V and settles at 0V. The rising edge of a typical corner starts at 0 V and settles at a voltage level of 1.2 V.

Figure 6: Output voltage of open ended driver: In red, falling edge fast-max corner; in blue, rising edge typical corner.

Note that the package model was intentionally removed from the driver model so that a clean waveform can be
generated. The package effect will be discussed in a later section.

Now that the output voltage is known, a resistor load is placed at the output of the receiver. The goal is to vary the
resistor value to measure an output voltage of 1.2/2 = 0.6 V. As a start a 50-ohm value is assigned to the resistor
and the simulation is run. The output voltage level is shown in blue in Figure 7 as 781 mV. In order to bring that
voltage level closer to 600 mV the load resistor needs to be decreased. A few more values are taken and a
resistance of 32 ohms came very close to our target.

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An important point to keep in mind is that a driver will not have a single output impedance. Instead, in each of its
operating corners the typical slow-weak, fast-strong might exhibit different output impedances. The pull-up, for a
rising edge, and pull-down, for a falling edge, transistor circuitry might show differences as well. A similar analysis
was done simulating the model at its fast-strong corner using a falling edge. The red plots in Figure 7 show that to
achieve a voltage level of 1.4/2 = 700 mV a 32-ohm load is needed as well. It happens to be that this model is
symmetric.

Figure 7: Driver output voltage when resistor value is swept: In blue, typical operating corner; in red, fast operating corner.

DRIVER FEATURES AND PACKAGE EFFECTS

In the previous section, the driver was used with its package information extracted from the IBIS model. However,
in real design simulations, the package parasitic effects, the transistor parasitic capacitances and the on-die
capacitance effects should be taken into considerations.

Before digging deeper into these effects, the output waveform shown in Figure 6 should be analyzed. Looking at
the blue curve for a rising edge simulation, everything looks as expected except for a small dip between 200 ps
and 260 ps. A close-up of the dip is shown in Figure 8. Where could this dip be coming from when all the driver
parasitics have been commented out?

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Figure 8: Driver dip intrinsic to model.

The answer is simply to look inside the IBIS model and examine the “raw” V-t curves. The model data is plotted in
Figure 9. The plots represent that data measured by the model vendor and show that the dip is inherent to the model
itself. Another important piece of information that the plot in Figure 9 shows is that the driver has an internal initial
delay before it starts driving the signal. For the typical corner graph, that initial delay is close to 200 ps. This is another
important factor to keep in mind, especially when doing timing analysis.

Figure 9: Rising waveform of model as captured by vendor.

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Concepts of Signal Integrity: Impedance

Another important feature of the receiver in the IBIS model is the C_ comp. This is a capacitance value that models
the input gate capacitance, the ESD protection diodes and the I/O pad sizes. Thus, a signal reaching the receiver
will see such a capacitance. On the other hand, when a signal reaches a driver model it will also see the C_comp
capacitance.

In this case, the capacitances are due to the parasitic capacitances of a transistor and the metal to substrate
capacitance on the die. Even though those two capacitances are of different values, the IBIS standard uses only one
parameter to model both. An important note to keep in mind is that as the model is driving a signal, it does not see
the C_comp. However, when a signal reflects from somewhere and comes back to the driver, the signal will see
and interact with C_comp.

The impact of the C_comp input capacitance on the receiver will be to add to the RC rise time of the signal the RX
sees. To simulate the effect of the C_comp parameter inside a receiver, the following circuit shown in Figure 10 is
used.

Figure 10: Left circuit is driving into an open circuit; middle circuit is driving into receiver with C_comp, while right circuit is used to
reverse-engineer C_comp value.

The left circuit drives into a really high-value resistor which acts like an open circuit. The large resistor is used to
model the high impedance state of a model when in the receiving state. In the middle circuit the driver is
connected to a receiver that has a C_comp value of 1pF. The right circuit is used to reverse-engineer the value of
C_comp, by modeling it as a capacitor and turning it off in the model.

A rising edge simulation is run and plotted in Figure 11. The blue plot shows the output of the driver when
connected to the 10k resistor. Its 10-90 rise time is measured to be 30.5 ps. On the other hand, when the driver is
connected to the receiver model U3.48 the driver now has to charge a capacitor when it reaches the receiver. Thus
its 10-90 rise time slows down to 93.7 ps as shown in the red plot.

One way of measuring what the value of C_comp is to use the circuit on the right in Figure 11. By varying the
capacitance value to 1 pf, the green dashed line overlapped the red plot almost exactly.

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Figure 11: C_comp effect when: In blue, driver connected to high impedance; in red, driver connected to receiver with C_comp; and
in dashed green, driver connected to capacitor and high impedance.

Now that the effect of C_comp is understood, the package effects will be investigated. Package parasitics are
usually modeled inside an IBIS model using RLC values as shown in Figure 12. The IBIS standard can model package
parasitics using an RLC matrix. Simulators typically convert the RLC elements into a uniform transmission line model
with the equivalent characteristic impedance and time delay.

Figure 12: Excerpt from IBIS model for the package section.

To investigate the package effects, the right circuit in Figure 13 is the driver with no package parasitics driving an
open circuit. The middle circuit is the same driver with the package parasitics driving an open circuit. The RLC
values of the driver are shown in Figure 12.

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Figure 13: Circuit to investigate package effects.

The results of the simulation are plotted in Figure 14; blue is the U1.AF24 circuit with no package, and the red is the
U2.AF24 circuit with the package. So, where did all that ringing in the red plot come from? Currently, since the
package is being modeled as a transmission line, there is an impedance and a TD that comes into play. All that
ringing is due to the reflections bouncing back and forth on that package transmission line.

To calculate the Z0 and TD of that transmission line, the following formulas are used: Z0 = √(L/C) = 46.4 Ω and TD =
√(L*C) = 130 ps, based on the IBIS package model. A transmission line with the calculated Z0 and TD is now added
to the model with no package as shown in the left circuit of Figure 13. The results are also plotted in Figure 14 in
dashed green lines. This shows how simple it is to reverse engineer the values of the package parasitics.

Figure 14: Simulations of package effects: In blue, model without any packages; in red, model with RLC package
parasitics; and in dashed green, transmission line matching circuit.

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CONCLUSION
This paper introduced the basic concepts of characteristic impedance and instantaneous impedance. A stripline
modeler was used to show how the different parameters of the geometry can affect the impedance and time
delay of both a stripline and a microstrip.

We also introduced some of the features of an IBIS model. The driver output impedance was calculated using the
voltage divider method. The C_comp on-die capacitance was shown to slow down a switching edge, and the
package parasitics were shown to behave as a short transmission line.

We hope the information in this paper helps you better manage potential signal integrity issues in your next PCB
design.

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