908 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 65, NO.
7, JULY 2018
Investigation of a Voltage-Mode Controller for
a dc-dc Multilevel Boost Converter
Wentao Jiang, Satyajit Hemant Chincholkar, and Chok-You Chan
Abstract—The multilevel dc-dc boost converter (MBC) is well
known for its simple circuit structure and high voltage gain.
Several controllers have been previously employed for their out-
put voltage regulation. However, due to the non-minimum phase
nature of the MBC, these controllers use both the inductor cur-
rent and output voltage as feedback variables. This increases
the complexity of the controller design and cost of implemen-
tation. In order to overcome these drawbacks, a voltage-mode
controller for the regulation of the MBC is proposed in this
brief. By using the generalized reduced-order state–space model
of the converter and frequency-domain techniques, the stability of
the voltage-controlled converter system is analyzed. In addition,
some simulation and experimental results illustrating the ability
of the proposed controller to regulate a 3x dc-dc multilevel boost
converter in the presence of load and line voltage variations are
provided.
Index Terms—DC-DC multilevel boost converter, output
feedback controller, stability analysis.
I. I NTRODUCTION
C-DC converters are used in many industrial and com-
D mercial applications such as electric vehicles, renewable
energy systems, aerospace equipment, etc. [1]. In many of
such applications, the dc-dc converters are expected to pro-
vide the necessary output voltage regulation [1]–[4]. Recently,
the regulation problem of the boost-type dc-dc converters has
attracted the attention of many control system researchers.
Most of the state-of-the-art controllers for the boost-
type dc-dc converters are based on an indirect control
approach [5]–[7]. In such type of control, the output volt-
age is regulated via the inductor current control. This scheme
offers several advantages such as improved settling time and
increased control bandwidth [8]. However, the main disadvan-
tage of the current-mode controller used in [5] and [6] is that
it requires the knowledge of the nominal load resistance of
the converter to compute the control signal. As such, it can-
not be employed in applications wherein the load resistance is
unknown. To address this, an adaptive current-mode controller
is given in [7]. However, just like the case of the traditional
current-mode controller, this controller requires the sensing
of at least one inductor current for feedback purposes. This
not only increases the complexity of the controller but also
Manuscript received May 3, 2017; revised June 18, 2017; accepted
June 30, 2017. Date of publication July 5, 2017; date of current version
June 27, 2018. This brief was recommended by Associate Editor H. H.-C. Iu.
(Corresponding author: Wentao Jiang.)
The authors are with the School of Electrical and Electronic Engineering,
South Spine, Nanyang Technological University, Singapore 639798 (e-mail:
wjiang003@e.ntu.edu.sg).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2017.2723660
1549-7747 c 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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increases the implementation cost due to the current sensing
circuitry.
Sliding-mode controller (SMC) is another widely used con-
troller for the dc-dc boost converters as it offers the simplicity
of implementation and the robust performance against load
and line variations [9], [10]. However, the main drawback of
the traditional hysteresis-modulation (HM)-based SMC is that
it leads to a variable switching frequency in its implementa-
tion. This leads to excessive switching losses, inductor losses
and electromagnetic-interference (EMI) generation [10]. If
a pulse-width-modulation (PWM) based SMC is used to
solve this problem, it might require two current sensors for
its implementation [7]. This may not be suitable for some
applications wherein there are power density constrains to
accommodate the current sensor. Apart from those, a novel
non-singular fixed-time terminal SMC for the nonlinear system
is given in [11].
Recently, in [12]–[14] some passivity-based output feed-
back controllers were proposed for several dc-dc boost con-
verters. Even though these controllers were found to give
stable output responses over a wide range of operating condi-
tions, the selection of the controller gains mainly relied on
a trial and error approach. Considering all this, to design
a suitable controller for the boost-type dc-dc converters using
a minimum number of state variables is still an open problem,
and some further investigations are required to address it.
In this brief, a voltage-mode controller is proposed for the
regulation of a dc-dc multilevel boost converter (MBC) [15].
Despite the non-minimum phase obstacle presented by this
boost-type dc-dc converter, the regulation of the output volt-
age is achieved without employing the current sensor. The
controller design is carried out using the classical frequency
domain technique, and the Bode-plot approach is used to
directly select the controller gains based on system’s phase
margin and gain margin criteria. The feasibility of the con-
troller is also shown. Finally, some experimental results are
provided to validate the effectiveness of the proposed con-
troller to regulate a 3x MBC in the presence of load and line
voltage disturbances.
II. M ODEL OF THE DC-DC M ULTI -L EVEL
B OOST C ONVERTER
Figure 1 shows the topology of the Nx MBC. This
converter has been widely adopted in power generation
systems [16], [17]. In contrast to some other existing high-
order dc-dc converters [18], [19], this converter uses a single
active switch which not only reduces the losses in the con-
verter but also simplifies the modelling and theoretical design
of the controller.
The generalized reduced-order averaged state-space model
of the MBC operating in continuous conduction mode
JIANG et al.: INVESTIGATION OF VOLTAGE-MODE CONTROLLER FOR dc-dc MULTILEVEL BOOST CONVERTER 909

Fig. 2. Frequency responses of GL (s) using different values of KP1 .

Fig. 1. Circuit diagram of Multi-level boost converter.

Using (4) and (5), the open-loop transfer function GL (s) of

is given by [15]:
the resulting controlled system is given as:
diL 1−u E  
=− vo + (1) KP1 s + KKP1I1
(b1 s + b0 )
dt NL  L  GL (s) = Gplant (s)GC (s) = −   (6)
dvo 1 N s a2 s2 + a1 s + a0
= (1 − u)iL − vo (2)
dt C(1 + u) R Now, consider the following set of converter parameter
where iL and vo represent the inductor current and output volt- values:
age of the converter and N is the level of the MBC. Also, E and E = 5 V, V d = 25 V, L = 1 mH,
R represent the input voltage and load resistance, respectively,
and L and C are the inductor and capacitor values respectively. C = 1 mF, = 500 , N = 3 (7)
Here, u is the control signal, such that u ∈ (0, 1). Substituting (7) in (6), the Bode-plot of the loop-gain GL (s)
Now, by setting (1) and (2) to zero, the equilibrium values for varying values of KP1 is shown in Fig. 2.
of vo , iL , and u are obtained as: It can be seen that there exists a resonance peak in the
low-frequency range of the Bode-plot of GL (s). This happens
Vd2 NE
vo∞ = Vd , iL∞ = , u∞ = 1 − (3) for a wide range of controller gains. As such, it is diffi-
ER Vd cult to design a stable controlled system while ensuring the
good system dynamic response [20]. Hence, the conventional
where Vd is the desired reference output voltage of the
voltage-mode controller is not quite suitable for the regulation
converter system.
of the MBC.

III. P ROPOSED VOLTAGE -M ODE C ONTROLLER B. Proposed Control Law

In this section, the proposed voltage-mode controller for the The proposed control law to be considered is given by:
regulation of MBC is described. The limitation of the conven-
tional voltage-mode controller for the MBC is shown first in NE
u = 1− (8)
order to appreciate the significance of the proposed controller. zd
dzd 1 
= −(K1 + K2 )zd + K2 vo + K1 zd_ref (9)
A. Conventional Voltage Mode PI Controller dt Ceq

The transfer function of the conventional voltage-mode PI    

zd_ref = KP2 Vd − βvo + KI2 Vd − βvo dt (10)
control law for the dc-dc converters is given as [5], [6]:
u(s) KI1 Here, KP2 , KI2 , K1 , K2 and β are the controller gains
GC (s) = = KP1 + (4) and Ceq = C(2 − NE Vd ) is the equivalent value of the out-
e(s) s
put side capacitance of the converter. Unlike [12]–[14], the
where u(s) is the controller output, e(s) = (Vd (s) − vo (s)) is structure of the proposed controller is such that the con-
the output voltage error which is the controller input, KP1 > 0 troller design can be carried out using the classical frequency
and KP2 > 0 are controller gains and s is a complex variable. domain approach. This avoids the use of the trial and error
Now, by linearizing (1)–(2) around the equilibrium point (3) method for the selection of the controller gains. The Bode-
and applying the Laplace transform to the resulting linearized plot approach can now be employed to design the controller
system, the control input (u) to output voltage (vo ) transfer gains based on the system’s phase margin and gain margin cri-
function can be obtained as: teria. Also, note that in contrast to [5] and [6], the proposed
control law is independent of the load resistance term R. This
vo (s) b1 s + b0 allows the implementation of the proposed controller in some
Gplant (s) = =− 2 (5)
u(s) a2 s + a1 s + a0 practical applications wherein R is unknown. Figure 3 shows
the block diagram of the proposed closed-loop controlled
where b1 = LVd4 , b0 = RE2 Vd2 , a2 = RECLVd (2Vd − NE), converter system. The augmented converter dynamic shown
a1 = ELNVd2 , and a0 = E3 NR. in Fig. 3 is actually obtained by substituting (8) into the

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910 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 65, NO. 7, JULY 2018

Fig. 3. Block diagram of the proposed closed-loop MBC system.

Fig. 4. Frequency responses of GAug (s) for different sets of K1 and K2 .

reduced-order model of the MBC (1)–(2) and then combining
the resulting dynamics with the proposed control law (9)–(10).

C. Controller Design where Macd is the output  vector, I is a 3x3 identity

matrix. Setting Macd = 0 1 0 , the transfer function
Initially, in order to obtain the equilibrium point of the over- GAug (s) = ṽo (s)/z̃d_ref (s) can be obtained as:
all closed-loop system, the closed-loop converter dynamics is
analyzed. Substituting (8) and (10) into (1)–(2) and (9) and ṽo (s) c1 s + c0
setting β = 1 yields the following system dynamics: GAug (s) = = (19)
z̃d_ref (s) d3 s3 + d2 s2 + d1 s + d0
diL NE E
=− vo + (11) where
dt LNzd L
  c1 = −K1 LNVd2 , c0 = K1 NRE2 , d3 = LRCeq
2 2
Vd ,
dvo zd NE N
= iL − vo (12)
dt C(2zd − NE) zd R d2 = Ceq LVd2 (N + K1 R + K2 R),
dzd 1 d1 = Ceq NRE2 + LNVd2 (K1 + 2K2 ), d0 = K1 NRE2
= {−(K1 + K2 )zd + K2 vo + K1 [KP2 (Vd − vo ) + θ ]}
dt Ceq
From (19), it can be seen that the controller gains K1 and
(13) K2 can directly affect the frequency response of the aug-
dθ mented converter dynamics. Now, the Bode-plot method can
= KI2 (Vd − vo ) (14)
dt be applied to select the values of the controller gains for
By setting (11)–(14) to zero, the unique equilibrium point of the augmented converter system. For the purpose of illustra-
the system can be obtained as: tion, consider the converter parameter values given by (7).
 Substituting (7) into (19), we get,
Vd2
(iL∞ , vo∞ , zd∞ , θ∞ ) = , Vd , Vd , Vd (15) c1  s + c0 
ER GAug (s) = −  3 (20)
d3 s + d2  s2 + d1  s + d0 
where zd∞ and θ∞ are the steady-state values of zd and θ ,
respectively. Also, using (10), (14) and (15), the steady-state where
   
value of zd_ref is given by: c1  = − 1.5 × 105 K1 , c0  = 3 × 109 K1 , d3  = 49,
zd_ref ∞ = θ∞ = Vd (16)  
d2  = 3.5 × 104 K1 + 3.5 × 104 K2 + 210 ,
Next, the design of the augmented converter dynamics is  
presented. Linearizing the augmented converter dynamics d1  = 1.5 × 105 K1 + 3 × 105 K2 + 4.2 × 106 , d0  = c0  .
shown in Fig. 2 around the equilibrium point (iL∞ , vo∞ , zd∞ )
given by (15) and using (16), the corresponding small-signal Figure 4 shows the effects of varying the controller gains K1
model of the augmented converter system can be obtained as: and K2 on the Bode-plot of GAug (s) given by (20). The dotted
blue line shows the frequency response of GAug (s) obtained
x̃˙ = Aacd x̃ + Bacd z̃d_ref (17) using K1 = 0.1 and K2 = 0.05. It can be seen that there exists
T a small resonance peak with magnitude 5.46 dB in the low-
where x̃ = [ĩL ṽo z̃d ] , ĩL = iL − iL∞ , ṽo = vo − vo∞ , z̃d =
zd − zd∞ , z̃d_ref = zd_ref − zd_ref ∞ and matrices Aacd and Bacd frequency region of the Bode-plot. The frequency response
are given by: GAug (s) using K1 = 0.8 and K2 = 0.05 is shown by the dashed
⎡ ⎤ ⎡ ⎤
green line in Fig. 4. It can be seen that the resonance peak in
0 − LVEd E
LVd 0 the low-frequency region increased to 25.3 dB when K1 was
⎢ NE ⎥
Aacd = ⎣ Ceq Vd − Ceq R − Ceq Bacd = ⎣ 0 ⎦
N N increased. Hence, increasing K1 increases the magnitude of
R ⎦,
K2 K1 +K2 K1 the resonance peak in the low-frequency region of the Bode-
0 Ceq − Ceq Ceq
plot. The frequency response of GAug (s) using K1 = 0.1 and
Now, by applying the Laplace transform to (17) and assuming K2 = 0.3 is shown by the solid red line in Fig. 4. It is seen
x̃(0) = 0 and z̃d_ref (0) = 0, we get, that increasing K2 can suppress the resonance peak in the low-
frequency region. Since the presence of resonance peak in the
x̃(s)
= Macd (sI − Aacd )−1 Bacd (18) low frequency region of the Bode-plot of GAug (s) complicates
z̃d_ref (s) the design of the outer voltage-loop controller, a small value

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JIANG et al.: INVESTIGATION OF VOLTAGE-MODE CONTROLLER FOR dc-dc MULTILEVEL BOOST CONVERTER
Fig. 5. Frequency responses of loop gain Gv (s) for K1 = 0.1, K2 = 0.3,
KP2 = 0.7 and KI2 = 120.4.
of K1 and a large value of K2 should be used to achieve a good
resonance damping [20]. Therefore, the values of K1 and K2
used were 0.1 and 0.3, respectively to achieve a satisfactory
frequency response.
Next, the design of the outer voltage-loop controller is
addressed. From (10), the transfer function of the voltage-loop
PI controller GPI (s) is given by:
KP2 s + KI2
GPI (s) =
s presence of load changes (b). in the presence of input voltage changes.
Using (20) and (21), the open-loop transfer function of the
controlled system can be obtained as:
Gv (s) = GPI (s)GAug (s)
  
−306.12KP2 s − 2 × 104 s + KKP2I2
=   du
s(s + 87.26) s2 + 202.7s + 7.02 × 104
In order to achieve a stable and robust closed-loop output
voltage response, the following design criteria are chosen [20]:
(a) the system should have a sufficient gain margin and phase
margin to ensure robust stability; (b) high gain in the low-
frequency region of the Bode-plot to achieve a small steady-
state output error; (c) a slope of -20dB/dec near the gain
crossover frequency to ensure system relative stability.
Based on above criteria, KP2 = 0.7 and KI2 = 120.4 are
selected. The Bode-plot of the corresponding loop-gain Gv (s)
is shown in Fig. 5. It can be seen that the magnitude of the
Bode-plot in the low-frequency region, i.e., at 1 Hz, is ∼ 26 dB
which ensures a small steady-state output error and a slope of
-20dB/dec is achieved near the gain crossover frequency of
∼16 Hz. Also, the gain margin and phase margin are obtained
as 7.54 dB and 52.1◦ , respectively.
D. Controller Feasibility
Next, the feasibility of the proposed controller is investi-
gated by analyzing the internal stability of the closed-loop
system. By rearranging (8), zd can be rewritten as:
NE
zd =
1−u
Substituting (2), (9) and (23) into the derivative of (8) yields:
du (1 − u)2   1−u
= K1 zdref + K2 vo − (K1 + K2 )
dt CNE(1 + u) C(1 + u)
(24)
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911
Fig. 6. ‘Remaining dynamics’ for the voltage-controlled converter.
(21) Fig. 7. Output voltage vo of the controlled converter system: (a). in the
Using the steady-state values of vo and zdref , i.e., vo∞ = Vd
and zd_ref ∞ = Vd , in (24) gives,
 
(K1 + K2 )(1 − u) (1 − u)V d
(22) = −1 (25)
dt C(1 + u) NE
Figure 6 shows the phase-portrait of (25). It can be seen
u∞ = 1 − NE Vd is the unique stable equilibrium point of the
system.
From the preceding analyses, it is seen that the proposed
control law given by (8)–(10) locally asymptotically stabi-
lizes the reduced-order model of the converter system (1)–(2)
for appropriate values of KP2 , KI2 , K1 and K2 , and the state
variables iL and vo will asymptotically converge to their equi-
V2
librium values given by ERd and Vd , respectively for any
0 < R < ∞.
IV. S IMULATION AND E XPERIMENTAL R ESULTS
To validate the effectiveness of the proposed control law for
the MBC, some simulation as well as laboratory experiments,
were carried out. The same set of circuit parameter values as
that used in Section III, given in (7) was used to obtain the
results.
A. Simulation Results
Initially, in order to show the effectiveness of the proposed
(23)
controller over a wide range of operating conditions, some
simulations were carried out using MATLAB version R2014a.
Figures 7(a) and 7(b) show the ability of the proposed con-
troller to regulate the output voltage of the dc-dc MBC with
the load resistance ranging from R = 25  to R = 1 k
and the input voltage ranging from E = 3.5 V to E = 15 V,
respectively.
912 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 65, NO. 7, JULY 2018
Fig. 8. System output voltage vo (CH. 1) and control signal u (CH. 2) of the
controlled converter system: (a). at the start-up stage; (b). in the presence of
load changes from 500  to 250  (and vice versa); (c). in the presence of
input voltage changes from 5 V to 3.3 V (and vice versa); (d). in the presence
of reference voltage changes from 25 V to 30 V (and vice versa).
B. Experimental Results
A laboratory prototype of the 3x MBC was built. The
controller was realized using simple analog devices and the
division function was implemented using AD633 IC and
AD711 IC. Also, the switching frequency used was 40 kHz.
Figure 8(a) shows the transient output voltage response of
the system. The values of KP2 , KI2 , K1 and K2 used were
0.7, 120.4, 0.1 and 0.3, respectively, to achieve satisfactory
response. It can be seen that the output voltage rapidly reached
the desired reference voltage with a small overshoot and
a negligible steady-state error. Also, the settling time obtained
was ∼0.1 s. Figure 8(b) shows the output voltage response
when the load resistance was changed from R = 500  to
R = 250  and then back to R = 500 . The resulting dis-
turbances in the output voltage were rejected in a worst-case
settling time of ∼0.2 s with a very small overshoot of ∼8%
of the nominal output voltage.
Figures 8(c) and 8(d) show the converter output voltage
responses when the input voltage was changed from E = 5 V
to E = 3.3 V (vice versa) and when the reference voltage
was changed from Vd = 25 V to Vd = 30 V (vice versa),
respectively. Again, a fast and accurate voltage tracking was
achieved. All these results verify the ability of the proposed
voltage-mode controller to regulate the output voltage of the
3x multilevel dc-dc boost converter.
V. C ONCLUSION
A voltage-mode control law for the regulation of the dc-dc
multilevel boost converter was proposed. The structure of the
proposed controller is such that it allows the direct use of the
Bode-plot method to select the appropriate values of the con-
troller gains to ensure the system robust stability. The proposed
controller was shown to be feasible. Besides, some simulation
and experimental results for a 3x MBC verified the ability of
the controller to regulate the dc-dc converter over a wide range
of operation conditions. The proposed voltage-mode control
law can also be applied to regulate other high-order dc-dc
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boost converters, noting that its structure may slightly vary as
per the expression of an equilibrium value of the duty-cycle
of the specific converter.
R EFERENCES
[1] J. Yang, B. Wu, S. Li, and X. Yu, “Design and qualitative robust-
ness analysis of an DOBC approach for DC–DC buck converters with
unmatched circuit parameter perturbations,” IEEE Trans. Circuits Syst.
I, Reg. Papers, vol. 63, no. 4, pp. 551–560, Apr. 2016.
[2] F. Guo, C. Wen, J. Mao, J. Chen, and Y.-D. Song, “Distributed coopera-
tive secondary control for voltage unbalance compensation in an islanded
microgrid,” IEEE Trans. Ind. Informat., vol. 11, no. 5, pp. 1078–1088,
Oct. 2015.
[3] T. A. F. Theunisse, J. Chai, R. G. Sanfelice, and W. P. M. H. Heemels,
“Robust global stabilization of the DC–DC boost converter via hybrid
control,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 4,
pp. 1052–1061, Apr. 2015.
[4] L. Yang, B. Wu, X. Zhang, K. Smedley, and G.-P. Li, “Dynamic
modeling and analysis of constant on time variable frequency one-cycle
control for switched-capacitor converters,” IEEE Trans. Circuits Syst. I,
Reg. Papers, vol. 64, no. 3, pp. 630–641, Mar. 2017.
[5] S. H. Chincholkar and C.-Y. Chan, “Investigation of current-mode con-
trolled cascade boost converter systems: Dynamics and stability issues,”
IET Power Electron., vol. 9, no. 5, pp. 911–920, Apr. 2016.
[6] C. Y. Chan, “Comparative study of current-mode controllers for a high-
order boost DC–DC converter,” IET Power Electron., vol. 7, no. 1,
pp. 237–243, Jan. 2014.
[7] C.-Y. Chan, S. H. Chincholkar, and W. Jiang, “Adaptive current-mode
control of a high step-up DC–DC converter,” IEEE Trans. Power
Electron., vol. 32, no. 9, pp. 7297–7305, Sep. 2017.
[8] W. Tang, F. C. Lee, and R. B. Ridley, “Small-signal modeling of aver-
age current-mode control,” IEEE Trans. Power Electron., vol. 8, no. 2,
pp. 112–119, Apr. 1993.
[9] S.-C. Tan, Y. M. Lai, and C. K. Tse, “A unified approach to the design
of PWM-based sliding-mode voltage controllers for basic DC–DC con-
verters in continuous conduction mode,” IEEE Trans. Circuits Syst. I,
Reg. Papers, vol. 53, no. 8, pp. 1816–1827, Aug. 2006.
[10] S. H. Chincholkar and C.-Y. Chan, “Design of fixed-frequency
pulsewidth-modulation-based sliding-mode controllers for the quadratic
boost converter,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 64, no. 1,
pp. 51–55, Jan. 2017.
[11] J. Ni, L. Liu, C. Liu, X. Hu, and S. Li, “Fast fixed-time nonsingular
terminal sliding mode control and its application to chaos suppression
in power system,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 64,
no. 2, pp. 151–155, Feb. 2017.
[12] C.-Y. Chan, “Simplified parallel-damped passivity-based controllers
for DC–DC converters,” Automatica, vol. 44, no. 11, pp. 2977–2980,
Nov. 2008.
[13] C. Y. Chan, “Investigation of voltage-mode controller for cascade
boost converter,” IET Power Electron., vol. 7, no. 8, pp. 2060–2068,
Aug. 2014.
[14] S. Chincholkar and C.-Y. Chan, “Design and implementation of an out-
put feedback controller for the Cuk converter,” in Proc. 41st Annu. Conf.
IEEE Ind. Electron. Soc. (IECON), Yokohama, Japan, 2015, pp. 86–90.
[15] J. C. Mayo-Maldonado, R. Salas-Cabrera, J. C. Rosas-Caro,
J. D. Leon-Morales, E. N. Salas-Cabrera, “Modelling and control of a
DC–DC multilevel boost converter,” IET Power Electron., vol. 4, no. 6,
pp. 693–700, Jul. 2011.
[16] B. Xu, D. Chen, H. Zhang, and R. Zhou, “Dynamic analysis and
modeling of a novel fractional-order hydro-turbine-generator unit,”
Nonlin. Dyn., vol. 81, no. 3, pp. 1263–1274, 2015.
[17] B. Xu et al., “Hamiltonian model and dynamic analyses for a hydro-
turbine governing system with fractional item and time-lag,” Commun.
Nonlin. Sci. Numer. Simulat., vol. 47, pp. 35–47, Jun. 2017.
[18] S.-C. Tan et al., “Variable structure modeling and design of switched-
capacitor converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56,
no. 9, pp. 2132–2142, Sep. 2009.
[19] X. Ruan, B. Li, Q. Chen, S.-C. Tan, and C. K. Tse, “Fundamental con-
siderations of three-level DC–DC converters: Topologies, analyses, and
control,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 11,
pp. 3733–3743, Dec. 2008.
[20] J. A. Morales-Saldana, J. Leyva-Ramos, E. E. Carbajal-Gutierrez,
and M. G. Ortiz-Lopez, “Average current-mode control scheme for
a quadratic buck converter with a single switch,” IEEE Trans. Power
Electron., vol. 23, no. 1, pp. 485–490, Jan. 2008.