I.

INTRODUCTION
Switched-capacitor dc-dc converters (SCDDCs)
use capacitors and semiconductor switches to convert
Power Switched-Capacitor one dc voltage to another. They are attractive because
they use no magnetic components, are small in
DC-DC Converter: Analysis size, and are amenable to monolithic integration.
Commercially available SCDDCs include the ICL7660
and Design [1] and the LT1054 [2].
Previous attempts at analyzing SCDDCs [3—7]
have relied on state-space-averaging [8], and have
been limited to an output power of a few watts. It
was shown in [3] that the efficiency of an SCDDC
WILLIAM S. HARRIS could exceed 80% by proper choice of the capacitive
K. D. T. NGO, Member, IEEE step-down ratio. Thus, the power rating of an SCDDC
University of Florida does not have to be restricted to a “low” power rating
of a few watts, and a “medium” power rating of
several tens of watts is conceivable. In the practical
case, however, the analysis and design results in
This paper shows that a switched-capacitor dc-dc converter [3] are not directly applicable since, as shown in
(SCDDC) can be designed to process up to several tens of watts of Fig. 3(d), the assumption of linear ripple [8] does
output power at an efficiency exceeding 80%. Converter operation not hold. This is due to an exponential current spike
is analyzed by “modified state-space-averaging,” (MSSA) which
sent into the output during the discharge interval,
causing large output voltage ripple. Therefore, general
is generally suitable for analysis of converters with nonlinear
analysis and design methods for the SCDDC need to
ripple. A design procedure is presented along with experimental
be revisited.
verification. This work presents a “modified state-space-
averaging” (MSSA) technique to analyze and design
an SCDDC. Section III describes the circuit topology
and operation. Section IV analyzes the SCDDC using
the MSSA method, and suggests a design procedure
based on analysis results. Section V compares
analytical, simulation, and experimental results.
Section VI concludes the paper.

II. NOMENCLATURE
The unit system in this paper is SI (MKS). Unless
otherwise specified, the convention used is as follows.
x¤ Instantaneous value of the variable x
x Low frequency component of the variable x
X Average value of the variable x, with
switching losses taken into account
X0 Average value of the variable x, with
switching losses not taken into account.
The nomenclature used is as follows.
A Averaged state-space matrix for switching
period
A1 State-space matrix for charge interval
A2 State-space matrix for discharge interval
Manuscript received January 3, 1994; revised January 11, B Averaged state-space matrix for switching
February 6, and March 4, 1996.
period
IEEE Log No. T-AES/33/2/03146. B1 State-space matrix for charge interval
Authors’ address: Dept. of Electrical Engineering, University of B2 State-space matrix for discharge interval
Florida, Gainesville, FL 32611-6200. C Value of capacitors C2 , C3 , : : : Cn
C1 Output capacitor
0018-9251/97/$10.00 °
c 1997 IEEE Cdgo Zero-bias drain-gate capacitance of Mj

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Cgso Zero-bias gate-source capacitance of Mj u Input vector
Cj Capacitors C2 , C3 , : : : Cn v Voltage
Cm Capacitance value taken from vC1 Voltage of C1
capacitance-voltage curves of the vCj Voltage of C2 , C3 , : : : Cn
manufacturer’s data sheets, measured at a vF “On” voltage of diode
voltage Vm vdg Drain-gate voltage of MOSFET
Cp Parasitic capacitance of switching device Vd sat Minimum voltage across MC to keep it in
d Switching duty cycle saturation
d0 1¡d Vin Input voltage
DjA Diodes turned on during charge interval VjB Cathode voltage of DjB at end of charge
DjB Diodes turned on during discharge interval interval
E Energy loss due to switching VjM Drain voltage of Mj at end of charge interval
Ejdg Energy lost by the drain-gate capacitor of Mj Vlin Gate-source voltage needed to keep Mj in
during a charge-discharge cycle linear region of operation
Ejds Energy lost by drain-source capacitor of Mj Vm Voltage across junction at which capacitance
during a charge-discharge cycle across that junction measures Cm , the value
Ejgs Energy lost by gate-source capacitor of Mj taken from the manufacturer’s data sheets
during a charge-discharge cycle v0 Output voltage
EjA Energy lost by the capacitance of DjA during x State-space vector over switching period
a charge-discharge cycle xm Sampled data points of x¤ at t = mT
EjB Energy lost by the capacitance of DjB during xm+1 Sampled data points of x¤ at t = (m + 1)T
a charge-discharge cycle xm+d Sampled data points of x¤ at t = (m + d)=T
Eloss Total energy switching loss during a ® Ratio of C1 to C1 + C2 + ¢ ¢ ¢ Cn
switching period ¢Vo Output voltage ripple
f Switching frequency © A constant
gm Transconductance of MC ´ Converter efficiency
i Integer index, i = 1, 2, : : : n ´max Maximum possible converter efficiency
iMc Current through MC ¸1 Eigenvalue of matrix A1
I Identity matrix ¸2a Eigenvalue of matrix A2
Iloss Average charging current loss during charge ¸2b Eigenvalue of matrix A2
interval ¹ A constant
Ion Value of iMc during the charge interval ¾ A constant
j Integer index, j = 2, 3, : : : n ¿1 Inverse of ¸1
k Value of C1 is kC ¿2a Inverse of ¸2a
m An integer value ¿2b Inverse of ¸2b
MC Metal-oxide semiconductor field-effect ª Ratio of average charging current through
transistor (MOSFET) acting as current C1 ¡ Cn to Ion , also ratio of output voltage
source when switching losses are accounted for to
Mj Switching MOSFETs (M2 , M3 , : : : Mn ) output voltage when switching losses are not
n Number of capacitors accounted for.
N Transformation matrix relating the state
variables from beginning to end of charge
III. CIRCUIT TOPOLOGY AND OPERATION
interval
P Transformation matrix relating state variables As shown in Fig. 1, an SCDDC generally consists
from beginning to end of charge interval of n stages. The first stage consists of capacitor C1 ,
Pi Average input power which acts as a filter for the load resistor RL . Each of
Ploss Average power loss due to switching the other stages consists of a capacitor Cj , diodes DjA
P0 Average output power and DjB , and a MOSFET Mj . MOSFET MC operates
R1 Equivalent series resistance (ESR) of C1 as a current source that controls the output voltage. It
RL Load resistance is shown as a p-channel device because they can be
Resr ESR of C2 , C3 , : : : Cn driven with simpler gate drive circuitry, as compared
Ron “On” resistance of Mj with an n-channel device. The other MOSFETs and
tmax Time where peak output ripple occurs, the diodes are used as switches.
referenced from the beginning of discharge Each switching period T consists of a charge
interval interval dT (mT < t < (m + d)T), and a discharge
T Switching period, inverse of switching interval d0 T ((m + d)T < t < (m + 1)T). At the
frequency beginning of the charge interval, M2 ¡ M4 and D2B ¡

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 Fig. 1. Four-stage switched-capacitor dc-dc converter.

Fig. 2. Equivalent circuits for (a) charge and (b) discharge

intervals.

D4B are off, and MC and D2A ¡ D4A are turned on,
charging the capacitors C1 ¡ C4 . The charge circuit is
shown in Fig. 2(a). During the discharge interval MC
and D2A ¡ D4A are off, and M2 ¡ M4 and D2B ¡ D4B are
turned on, discharging C2 ¡ C4 into C1 and RL . The
discharge circuit is shown in Fig. 2(b).
Fig. 3 shows the typical waveforms of an SCDDC
switched at 100 kHz and 0.25 duty ratio. It can be
seen from Figs. 2(a), 3(a), and 3(b) that during the
charge interval, the current Ion flows through MC ,
C1 ¡ C4 , and D2A ¡ D4A , establishing a voltage at
the drain of MC which is the sum of the voltages
across C1 ¡ C4 and D2A ¡ D4A . During the discharge
interval (Fig. 2(b)), C2 ¡ C4 discharges into C1 and RL
through M2 ¡ M4 . Note that in the discharge interval
the current through M4 (Fig. 3(c)) is exponential, not
linear. The voltage ripple (Fig. 3(d)) is also obviously
nonlinear. These nonlinear waveforms necessitate the Fig. 3. For SCDD with P0 = 48 W, Vin = 55 V, Vo = 12 V, n = 4,
use of MSSA discussed in the next section. Ion = 4 A, RL = 3 −, C = 9:6 ¹F, Resr = 0:003 −, k = 9,
During the charge interval MC must remain in the Ron = 0:3 −, VF = 0:3 V, PSPICE simulation: (a) current through
saturation region, which means that the voltage across MC , (b) voltage at drain of MC , (c) current through M4 , (d) output
it must be greater than or equal to Vd sat , the saturation voltage ripple.

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voltage. This gives rise to the condition where · ¸
¤
vC1
Vin ¸ Vd sat + VC1 [(m + d)T] x¤ = ¤
: (6)
vCj
+ (n ¡ 1)(VF + Ion Resr + VCj [(m + d)T]) (1)
It is assumed that the voltages of C2 , C3 , : : : , Cn are
where the ESR of C1 has been neglected, and for a equal, allowing the simplification of an n-state system
power MOSFET [9] down to a 2-state system [3].
Ion MSSA starts with the state-space equations of the
Vd sat = : (2) equivalent circuits shown in Figs. 2(a) and 2(b). For
gm
the charge interval shown in Fig. 2(a):
The transconductance of MC is usually taken from the
manufacturer’s data sheets. x_ ¤ = A1 x¤ + B1 u¤ (7)
It appears from (1) that to keep MC in saturation,
where the ESR of C1 is neglected and
the right-hand side of (1) should be made as small
2 3
as possible, e.g., by making n or VCj [(m + d)T] ¡1
0
small. It is shown later, however, that n is directly A1 = 4 kCRL 5 (8)
proportional to the efficiency and VCj [(m + d)T] 0 0
inversely proportional to the size of the semiconductor 2 ª 3
devices and the capacitors. Thus, it is desirable to 0
6 kC 7
keep the right-hand side of (1) as close to Vin as B1 = 4 5 (9)
possible. ª
0
In a real circuit the MOSFETs and diodes have C
· ¤ ¸
parasitic capacitances that must be charged and iMc
u¤ = : (10)
discharged during switching. The charging and vF¤
discharging of these capacitors results in switching
losses [10, 11], reducing the output power and with For a constant input U, the solution of (7) is [14]
it the output voltage. It is shown later that this is ¤
vC1 (t) = e¸1 (t¡mT) vC1 (mT)
equivalent to having a net reduction of charging
current through C1 ¡ Cn . In Fig. 2(a), this reduction in ª Ion
+ ¸¡1
1 (e
¸1 (t¡mT)
¡ 1) (11)
current is shown as Iloss , which represents the average kC
charging current loss over the charge interval. The ¤ ª Ion
vCj (t) = vCj (mT) + (t ¡ mT) (12)
average charging current during the charge interval is C
then given by
Ion ¡ Iloss = ª Ion (3) where
1 ¡1
¸1 = ¼ : (13)
where ª is determined later from the switching loss ¿1 kCRL
(Ploss ) and the output power without switching loss
For the discharge interval shown in Fig. 2(b):
(P00 ): s
P x_ ¤ = A2 x¤ + B2 u¤ (14)
ª = 1 ¡ loss : (4)
Po0
where
2 ¡(n ¡ 1) n¡1 3
IV. ANALYSIS AND DESIGN
6 kC((Ron + Resr )kRL ) kC(Ron + Resr ) 7
A. Derivation of State-Space Equations A2 = 6
4
7
5
1 ¡1
This section analyzes the SCDDC using the C(Ron + Resr ) C(Ron + Rest )
MSSA method, and suggests a design procedure (15)
based on analysis results. MSSA seeks to model the 2 ¡(n ¡ 1) 3
slowly varying “envelope” x(t), constructed from 0
6 kC(Ron + Resr ) 7
the regularly sampled points xm derived from the B2 = 6
4
7:
5 (16)
1
instantaneous state vector x¤ (t). The frequent choices 0
C(Ron + Resr )
for xm are x¤ (mT), the value of x¤ (t at the beginning
of each switching period [12], and hx¤ (t)im , the For a constant input U, the solution of (14) is [14]
average of x¤ (t) over a switching period [13]. The
various choices for xm are related to each other by x¤ (t) = eA2 (t¡(m+d)T) xm+d
transformations. Since the ripple in an SCDDC is + A¡1 A2 (t¡(m+d)T)
¡ I)B2 U:
2 (e (17)
generally nonlinear, it is convenient to let the MSSA
state variable be Using (11), (12), and (17), the discrete derivative
xm = x¤ (mT) (5) of the state can be approximated using the Euler

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approximation [14] also increase. The condition that ¿2a À T is still valid,
xm+1 ¡ xm and (27) still holds. The exponential function in (26)
_
x_ m = x(mT) ¼ : (18) can no longer be approximated by zero, nor by the
T
first two or three terms in its series expansion as in [8]
From (11) and (12), the boundary condition at t = and [12]. Therefore, in MSSA, the exponential term
(m + d)T is containing ¿2b is carried along as a constant ¹, where
vC1 [(m + d)T] = vC1 (mT)e¡dT=kCRL 0
¹ = e¡d T=¿2b : (28)
¡dT=kCRL
+ ª Ion RL (1 ¡ e ) (19)
Since ¿1 À T also holds, the exponential term in
dTª Ion (19) containing this eigenvalue can be approximated
vCj [(m + d)T] = vCj (mT) + : (20)
C as
From (17), the boundary condition at t = (m + 1)T is dT
e¡dT=¿1 ¼ 1 ¡ : (29)
0 0 ¿1
xm+1 = eA2 d T xm+d + A¡1
2 (e
A2 d T
¡ I)B2 U: (21)
This allows (19) and (20) to be rewritten in matrix
Use of (19) and (20) in (21) allows the expression form as
of xm+1 in terms of xm . Thus, (18) can be cast in the xm+d = (I + dTA1 )xm + dTB1 U (30)
following continuous state-space form:
or
x_ = Ax + BU (22)
xm+d = Nxm + PU (31)
where A and B are given later.
Because of the availability of MOSFETs with where the transformation matrices N and P are given
Ron less than 0.1 ohm [15], and multilayer ceramic by
capacitors with Resr values ranging from a few 2 dTª 3
· ¸ 0
milliohms to a few tenths of milliohms [16], the ¾ 0 6 kC 7
following practical constraints are invoked to simplify N= P =4 5 (32)
0 1 dTª
the exact analytical results to design criteria. 0
C
² RL À (Ron + Resr ) À R1 dT
² For low ripple, C1 À (C2 + C3 + ¢ ¢ ¢ Cn ) ¾ =1¡ : (33)
kCRL
As stated previously, the nonlinear ripple is due Equations (21) and (23)—(33) allow A and B in
to an exponential current spike sent to the output (22) to be written as
during the discharge interval, meaning that one of 2 · ¸ 3
the eigenvalues of A2 is on the order of the switching T
¡ + (1 ¡ ¹)(1 ¡ ®)¾ (1 ¡ ¹)(1 ¡ ®)
frequency. Under the stated assumptions, these A¼4 kCRL 51
T
eigenvalues are given by the following: (1 ¡ ¹)¾® ¡(1 ¡ ¹)®
1 ¡1 (34)
¸2a = ¼ (23) 2 dª
¿2a (k + n ¡ 1)RL C ¡(1 ¡ ¹)(n ¡ 1) 3
[1 + (1 ¡ ¹)(n ¡ 1)]
kC kT
1 ¡1 B¼4 5: (35)
¸2b = ¼ (24) dª ¹ 1¡¹
¿2b ®(Ron + Resr )C C T
where
C1 kC B. Approximate Steady-State Solution
®= =
C1 + C2 + ¢ ¢ ¢ Cn kC + (n ¡ 1)C
The steady-state capacitor voltages at the
k beginning of the charge interval can be found by
= : (25)
k+n¡1 setting the derivative in (22) equal to zero:
In the practical case, a “low” power converter
X = ¡A¡1 BU (36)
has ¿2b ¿ T and ¿2a À T. For these conditions, the
exponential functions in (21) can be approximated as or
0
e¡d T=¿2b ¼ 0 (26) VC1 (mT) ¼ ndª Ion RL (37)
and VCj (mT) ¼ VC1 (mT) + VF
0 d0 T
e¡d T=¿2a ¼ 1 ¡ : (27) μ ¶
¿2a d
+ ¹dª Ion Ron + Resr + :
However, as the power increases to a “medium” fC(1 ¡ ¹)
level, ¿2b can become very close to T, because C must (38)

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In the limit as C goes to infinity and with Iloss = 0, the
results in (37) and (38) can be shown to reduce to the
state-space results in [3].
A designer usually does not have much control
over the VC1 (mT) and VF terms in (38) because, as
shown later, VC1 (mT) ¼ Vo and VF is the on-drop of
the diodes. Therefore, if VCj [(m + d)T] is to be kept
small as dictated by (1) to keep MC in saturation, the
capacitive reactance 1=fC and the parasitic resistances
(Ron + Resr ) need to be made small. In particular,
since Ion could be several amperes at medium power
levels (e.g., 50 W), (Ron + Resr ) needs to be on the
order of 1 − or less. Consequently, ¿2b defined in
Fig. 4. Output ripple as function of duty cycle for d > 1=n and
(24) is comparable to T, making the output waveform d · 1=n for circuit of Fig. 3.
(Fig. 3(d)) nonlinear and necessitating MSSA. One
may argue that (Ron + Resr ) should be made as small
as practically allowed so that the same VCj [(m + d)T] where tmax is shown in Fig. 3(d). For d · 1=n, (45)
can be achieved with a small value of C. However, becomes
there are several problems with this argument. First, ¢Vo = vo¤ [(m + d)T + tmax ] ¡ vo¤ (mT): (47)
practical capacitors are made such that a lower Resr
corresponds to a larger C. Secondly, a MOSFET with If (46) and (47) are plotted as a function of d, they
too small an Ron would be difficult to drive because of intersect at a minimum point where d ¼ 1=n. Fig. 4
the large gate capacitance. Thirdly, if (Ron + Resr ) is so shows a MATLAB [17] plot of (46) and (47) for the
small that ¿2b ¿ T, C2 ¡ Cn would discharge into C1 in circuit of Fig. 3, where n = 4. The two equations
the form of exponential current spikes with high peak intersect at a minimum ripple of ¢Vo = 0:098 V at
value, causing electromagnetic interference problems. d = 0:25. In Section V the estimated value for ¢Vo is
Thus, it is recommended that if possible, Ron and C be shown to be 0.096 V.
selected such that For the minimum ripple condition (d = 1=n), the
value of ¢Vo is given by (47), which can be written
0:25d0 T · ¿2b · d0 T: (39) using (43) as
From (31)—(33), the voltage of C1 at the beginning ¤
¢Vo ¼ vC1 ¤
[(m + d)T + tmax ] ¡ vC1 (mT): (48)
of the discharge interval is given by
¤
Expansion of (17) gives vC1 during the discharge
dTª Ion interval, and the value of tmax can be found from
VC1 [(m + d)T] = ¾VC1 (mT) + : (40)
kC ¤
where the derivative of vC1 equals zero. Substitution
Under the assumption that ¿1 À T, (40) reduces to of (17), and (37)—(44) into (48) will result in the
simplified equation
VC1 [(m + d)T] ¼ VC1 (mT): (41)
dTª Ion (1 ¡ ®)
From (20), the voltage of Cj at the beginning of the ¢Vo ¼ [1 ¡ ©(1 ¡ ln ©)] (49)
C
discharge interval is
where
dTª Ion ¿2b n
VCj [(m + d)T] = VCj (mT) + : (42) ©¼ : (50)
C T n¡1
Since C1 can be chosen so that R1 is small The efficiency is calculated from
enough to be neglected, the output voltage can be Po (V )2 1
approximated as ´= = o ¢ (51)
Pi RL dIon Vin
v0¤ ¼ vC1
¤
: (43)
which can be rewritten using (44) as
This gives the steady-state average output voltage as
nVo
Vo ¼ VC1 (mT) ¼ ndª Ion RL : (44) ´= ª: (52)
Vin
The output voltage ripple is calculated from
C. Switching Losses
¢Vo = max(vo¤ ) ¡ min(vo¤ ): (45)
There are two cases that must be considered in 1) Introduction: As previously stated, switching
evaluating (45). For d > 1=n, (45) becomes losses occur as the parasitic capacitances of the
MOSFETs and diodes charge and discharge. The
¢Vo = vo¤ [(m + d)T + tmax ] ¡ vo¤ [(m + d)T] (46) switching losses take away from the available output

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power, reducing the output voltage. In (44), this effect terminal. The first term represents energy lost as
is shown to be equivalent to reducing the charging vdg goes from zero to VjM , while the second term
current from Ion to ª Ion , as shown in Fig. 2(a). represents the energy lost when vdg goes from zero
The MOSFET and diode capacitance model used to ¡Vlin . The drain-gate capacitance is a constant Cdgo
is similar to the one in [11], and is given by when vdg · 0. The value for Cmdg is taken from the
μ ¶¡0:5 manufacturers capacitance-voltage curves where Vm is
v given by (57) when j = n (Vm = VnM ).
Cp (v) = Cm : (53)
Vm Using (56), the energy lost to the constant
The Cm and Vm terms are taken from capacitance- gate-source capacitor of Mj is given by
voltage plots derived from manufacturer’s data Cgso
sheets. Notice that Cm is the capacitance value when Ejgs = [(Vo )2 + (Vlin )2 ]: (59)
2
v = Vm .
The energy lost to a voltage-dependent capacitor as The energy lost to the drain-source capacitor of Mj
it charges and discharges from a voltage of zero to V is given by
" #
and back is given by 2 (VjM ¡ Vo )2
0:5 1:5
Z V Ejds = 4Cmds (Vm ) (VjM ¡ Vo ) 1¡
3 (Vm )2
E=2 vCp (v) dv (54)
0 (60)
which, using (53), simplifies to where Vm = VnM ¡ Vo .
" μ ¶2 # 3) Diode Energy Loss: In the circuit of Fig. 1, it
2 V
E = 4Cm (Vm )0:5 (V)1:5 1 ¡ : (55) can be seen that there are two types of diodes, charge
3 Vm and discharge. The charge diodes (type “A” diodes)
are forward-biased during the charge interval. The
For a capacitor whose value remains constant with
discharge diodes (type “B” diodes) are forward-biased
voltage (Cp (v) = Cm ), (54) simplifies to
during the discharge interval. During the charge
E = Cm V2 : (56) interval, the jth B-diode voltage goes from VF to ¡VjB ,
where
2) MOSFET Energy Loss: The capacitance model
of a power MOSFET is made up of three capacitors: VjB = Vo + (j ¡ 1)VF + (j ¡ 2)VCj ((m + d)T):
the voltage-dependent drain-gate and drain-source (61)
capacitors, and the constant gate-source capacitor [10].
During the discharge interval, the jth A-diode voltage
During a switching cycle the drain-gate voltage of Mj
goes from VF to ¡(VCj ((m + d)T) + VF ). Neglecting VF ,
goes from ¡Vlin to VjM and back; and the drain-source
the energy lost to DjA is then given by
voltage goes from zero to VjM and back, where for
j = 2, 3, : : : n, EjA = 43 Cmda (VCj ((m + d)T))2 : (62)
VjM = Vo + (j ¡ 1)VF + (j ¡ 1)VCj ((m + d)T): The energy lost to DjB is
(57) " μ ¶2 #
0:5 1:5 2 VjB
When the gate voltage rises from zero to Vo + Vlin , EjB = 4Cmdb (VnB ) (VjB ) 1¡ :
3 VnB
the energy lost to the drain-gate and gate-source
capacitors is donated by the gate-drive circuit. When (63)
the gate voltage falls to zero from Vo + Vlin , the energy In (62), Vm = VCj ((m + d)T), and in (63), Vm = VnB .
lost to the drain-gate and gate-source capacitors is 4) Switching Power Loss: The total energy lost
donated by the converter power stage. Therefore, the per switching cycle, Eloss , is the sum of the energy lost
net energy lost by the converter is one-half of the from each parasitic capacitor, or
values given in (55) and (56). Thus, the energy lost
n
X
to the drain-gate capacitor of Mj can be calculated as
Eloss = (Ejdg + Ejds + Ejgs + EjA + EjB ):
" μ ¶2 # j=2
0:5 1:5 2 VjM
Ejdg = 2Cmdg (VnM ) (VjM ) 1¡ (64)
3 VnM
The total power lost due to switching is then given
Cdgo (Vlin )2
+ : (58) by
2 Ploss = fEloss : (65)
The subscript j represents the jth MOSFET, while The output voltage can be calculated using
the subscripts d and g represent the drain and gate p
terminals. A similar designation s applies to the source Vo = RL Po (66)

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where
Po = Po0 ¡ Ploss : (67)
The variable Po0 can be thought of as the desired
output power, while Po is the actual output power
reduced by switching losses. The variable Po0 clearly
has no physical meaning since there are always
switching losses, but to aid in the following design
procedure it is useful to define it using (44) and (66) as
Po0 = (ndIon )2 RL ª = 1: (68)
D. Design Procedure
The design procedure can be used to obtain either
the highest possible efficiency or the smallest possible
value (and physical size) of the charging capacitance
C. The procedure is an iterative process that tries to
predict the value of Po in (66) that will produce the
desired value for Vo . Given the input voltage Vin , the
desired output voltage, the desired output power, and
the value for the output ripple, the design proceeds as
follows.
1) Set Vo equal to the desired output voltage, and
estimate the number of stages using
Vin
n¼ : (69)
Vo
Round n down to the nearest integer. Until Po0 is
available from Step 10, set Po0 equal to the desired
output power.
2) Set the duty cycle to d = 1=n for minimum
ripple.
3) Until ª and Ion are available from Step 10,
set ª = 1 and calculate Ion and RL using (44) and
(68). This value of RL does not change in subsequent
iterations. The average current through MC is then
given by
IMc = dIon : (70)
Letting the blocking voltage be Vin , the selection of MC
is now possible, and the value of gm is now known.
4) Letting the blocking voltage be Vin and the
average current through DjA be IMc , the selection of
DjA is now possible. For convenience, let DjB be the
same diode. The values of VF , Cmda , and Cmdb (using
(61)) are now known.
5) Calculate Vd sat using (2). Set Resr = 0,
vC1 [(m + d)T] = Vo , and calculate VCj [(m + d)T]
using (1).
6) Until k is available from Step 12, arbitrarily
set the output capacitance to 10 times that of the
sum of the other capacitors, or k = 10 and from (25),
® = 0:909.
7) Set ¹ = 0 and use (38) to estimate VCj (mT).
If VCj [(m + d)T] < VCj (mT), reduce n by one and
start again at Step 2. Until the switching frequency
is available from Step 13, set f = 100 KHz.
8) Calculate C using (42). The value of Resr is
now known.
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9) Using (24) and (39), calculate the value of Ron .
Letting the blocking voltage be Vin , the selection of Mj
is now possible. The capacitance values of Cmdg , Cmds ,
Cdgo , and Cgso (using (57)) are now known.
10) Using the MOSFET and diode capacitance
parameters and setting Vlin = 10 V, compute Vo using
(57)—(67). If Vo equals the desired output voltage,
proceed to Step 11. If not, decrease ª , increase Ion by
the factor (ª )¡1 , and increase Po0 by the factor (ª )¡2 .
Set Vo to the desired output voltage and repeat Steps
3—10 until Vo in (66) equals the desired output voltage.
11) Use all known parameters to recalculate
VCj [(m + d)T], VCj (mT), and ¹ using (1), (38), and
(28). Recalculate C using (42).
12) Compute k from the output ripple using
(23)—(25), (28), and (49)—(50). Modify k until the
desired value of output ripple is obtained.
13) Calculate the efficiency using (52). To decrease
the value of C, increase the switching frequency
and repeat Steps 1—13. It is recommended that the
upper limit for the switching frequency be 1 MHz. To
increase the efficiency, reduce the switching frequency
and repeat Steps 1—13. From (52), the maximum
possible efficiency obtainable from a particular circuit
is
V
´max = n o ª = 1: (71)
Vin
V. VERIFICATION
A design example is now given to show that a high
efficiency, medium power converter is feasible. The
specifications are Vin = 55 V, Vo = 12 V, Po = 48 W,
and 1% or less output ripple. Using hte preceding
design procedure, the following results are obtained:
n = 4; d = 0:25; f = 100 KHz; 1N5822 for DjA and
DjB , VF = 0:3 V, Cmda = 143 pF, Cmdb = 70:4 pF;
VCj [(m + d)T] = 13:37 V; IRF520 for Mj , Ron = 0:3 −,
tf = 50 ns, Cmds = 86:1 pF, Cmdg = 12:2 pF, Cgso =
378:1 pF; C = 9:6 ¹F, Resr = 3 m−; ª = 0:999;
Ion = 4:006 A; ¢Vo = 0:096 V (k = 9); Vo = 12 V;
´ = 87:2%.
PSPICE simulation [18] gave the following
results: Vo = 11:98 V; ¢Vo = 0:094 V; VCj [(m + d)T] =
13:40 V.
An experimental prototype similar to this example
was built and tested. Since small multilayer ceramic
(MLC) capacitors were unavailable, relatively large
polyester film capacitors were used. The footprint of
he power circuit measured 114 mm £ 152 mm (4:5 in
£6 in), and the height was about 25.4 mm (1 in).
The large circuit layout introduced large parasitic
inductances and resistances, causing oscillations and
switching spikes which can be seen in the ripple
waveform in Fig. 5(a). The value of the ripple was
0.100 V, which was slightly greater than the calculated
value of 0.096 V. The efficiency was found to be
82.3%.
393
 takes advantage of practical approximations to realize
an operational, low to medium power, high-efficiency,
switched-capacitor dc-dc converter. Design examples
showed close agreement between theory, simulation,
and experimental verification, except as noted.
Topics to be addressed in the future might include
switching frequency and power density optimization,
new switching techniques, and dynamic analysis.
The power density (and performance) could be
improved by the use of MLC chip capacitors. Since
an 8.2 ¹F MLC chip capacitor measures approximated
9 mm £ 10 mm £ 2:5 mm [19], the capacitors of the
experimental SCDDC would fit into a volume of
40 mm £ 40 mm £ 2:5 mm. For a given commercial
capacitor, it would be interesting to determine the
optimal switching frequency and the maximum power
density at various power levels.
One way to improve the power density may be
to use a small LC filter between C1 and the load to
reduce the size of C1 .
Dynamic analysis appears manageable for the
converter discussed herein, but may not be so with
the inclusion of an LC filter.

REFERENCES

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Intersil Applications Handbook, 1988, 6-32—6.40.
[2] Linear Technology Corp. (1989)
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Linear Technology Corp., 1989.
Fig. 5. From an experimental 48 W converter: (a) output ripple,
[3] Webster, J. R., and Ngo, K. D. T. (1994)
(b) drain voltage of MC , (c) current through M4 . Horizontal scale
Steady-state analysis and design of a switched-capacitor
is 1 ¹s/div.
dc-dc converter.
IEEE Transactions on Aerospace and Electronic Systems,
30, 1 (Jan. 1994), 92—101.
The drain voltage of MC is shown in Fig. 5(b),
[4] Cheong, S. V., Chung, S. H., and Ioinovici, A. (1992)
and the current through M4 is shown in Fig. 5(c). The Development of power converters based on
shapes of the waveforms obtained from the prototype switched-capacitor circuits.
are very similar to their PSPICE counterparts shown In Proceedings of IEEE International Symposium on
in Fig. 3. Circuits and Systems, 1992, 1907—1910.
Extensive PSPICE simulation over a wide range [5] Umeno, T., Takahashi, K., et al. (1990)
New switched-capacitor dc-dc converter with low input
of values for Vo , Po , and n has been done to verify current ripple and is hybridization.
the design procedure and the switching loss analysis. In Proceedings of IEEE Midwest Symposium on Circuits
Because PSPICE models the drain-gate capacitance and Systems, 1990, 1091—1094.
as a constant value independent of bias, the MOSFET [6] Mak, O., Wong, Y., and Ioinivici, A. (1995)
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model was modified to include a voltage-dependent
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drain-gate capacitance. IEEE Transactions on Industrial Electronics, 42, 1 (Feb.
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[7] Cheong, S. V., Chung, S. H., and Ioinovici, A. (1994)
VI. CONCLUSION Inductorless dc-dc converter with high power density.
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design of an SCDDC with low to medium output [8] Middlebrook, R. D., and Cuk, S. (1976)
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 [9] Antognetti, P., et al. (1986) [14] Kailath, T. (1980)
Power Integrated Circuits: Physics, Design and Linear Systems.
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[11] Sabate, J. A., et al. (1990) [17] MATLAB User’s Guide.
Design considerations for high-voltage high-power The Math Works, Inc., 1993.
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William S. Harris was born at Eglin AFB, Florida, in 1956. He received the
B.E.E. in electrical engineering from Auburn University, Auburn, AL, in 1978.
In 1988 he received the M.S. degree in systems analysis from the University of
West Florida, Pensacola. He is currently working towards the Ph.D. in electrical
engineering at the University of Florida in Gainesville.
Since 1978 Mr. Harris has been employed by the United States Air Force at
Eglin AFB as a civilian electrical engineer. His responsibilities include the design
of electronic instrumentation systems for airborne and range use. His most recent
work has been in designing flight termination systems for guided weapons. His
research interest is in the area of power electronics.

Khai D. T. Ngo (S’82–M’84) received a B.S. degree in electrical and electronics

engineering from California State Polytechnic University, Pomona in 1979, and
an M.S. and Ph.D. degree in the same discipline from California Institute of
Technology, Pasadena, in 1980 and 1984, respectively.
He was a member of the technical staff at General Electric Corporate Research
and Development Center in Schenectady, NY from 1984 to 1988. He has been an
Associate Professor in the Department of Electrical Engineering at the University
of Florida since 1988. His current research interests are low-profile magnetics,
power semiconductor devices and integrated circuits, soft-switched power
converters, and power quality.

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