module addbit(input logic [3:0]a,b,input logic ci, output logic [3:0]sum, output

logic co);
assign{co,sum}= a+b+ci;
endmodule

interface test_ifc (input clk);

logic [3:0]a,b;
logic co,ci;
logic[3:0]sum;
//modport dut (input a,b,ci, output sum,co);
modport tb (output a,b,ci, input sum,co,clk);
endinterface

module test (test_ifc.tb io);

initial begin
@(posedge io.clk)
io.a=1001; io.b=0110;
$display ("a=%b,b=%b,ci=%b,sum=%b,co=%b",io.a,io.b,io.ci,io.sum,io.co);
#10s io.a=0000; io.b=0000;
$display ("a=%b,b=%b,ci=%b,sum=%b,co=%b",io.a,io.b,io.ci,io.sum,io.co);
#10s io.a=1111; io.b=1111;
$display ("a=%b,b=%b,ci=%b,sum=%b,co=%b",io.a,io.b,io.ci,io.sum,io.co);
end
endmodule

module top ();

logic [3:0]a,b;
logic ci,clk;
wire [3:0]sum;
wire co;
initial begin
clk<=0;
forever #5s clk= ~clk;
end
test_ifc io(clk);
test d1(io);
addbit d2(.a(io.a),.b(io.b),.ci(io.ci),.sum(io.sum),.co(io.co));
endmodule