Interrupts of 8085

1. 1. INTERRUPTS
2. 2. What Are Interrupts?  A Suspension of a process such as the execution of a computer
program, caused by an event external to that process, and performed in such a way that
the process can be resumed.  These devices occasionally need CPU service, but we can’t
predict when, so Interrupt is a process where an external device can get the attention of
the microprocessor.  The process starts from the I/O device  The process is
asynchronous.  Interrupt is a subroutine call initiated by external hardware device and is
asynchronous, meaning it can be initiated at any time without reference to the system
clock. However, the response to an interrupt is directed or controlled by the
microprocessor.
3. 3. Polling  CPU periodically checks each device to see if it needs service  Takes CPU
time even when no requests pending  Overhead may be reduced at expense of response
time  can be efficient if events arrive rapidly “Polling is like picking up your phone
every few seconds to see if you have a call. …”
4. 4. Alternative of Polling is Interrupts  Give each device a wire (interrupt line) that it can
use to signal the processor.  When interrupt signaled, processor executes a routine called
an interrupt handler to deal with the interrupt.  No overhead when no requests pending.
5. 5. Polling vs. Interrupts  “Polling is like picking up your phone every few seconds to see
if you have a call. Interrupts are like waiting for the phone to ring.”  In polling CPU
keeps on checking I/O devices at regular interval whether it needs CPU service whereas,
in interrupt, the I/O device interrupts the CPU and tell CPU that it need CPU service. 
Interrupt becomes inefficient when devices keep on interrupting the CPU repeatedly and
polling becomes inefficient when CPU rarely finds a device ready for service.
6. 6. Classification of Interrupts  When the Microprocessor receives an interrupt signal, it
suspends the currently executing program and jumps to an Interrupt Service Routine
(ISR) to respond to the incoming interrupt. They can be classified into three categories 
Vectored and Non-Vectored Interrupts  Hardware and Software Interrupts  Maskable
and Non-Maskable Interrupts  There are 6 pins available in 8085 for interrupt: 1. TRAP
2. RST 7.5 3. RST6.5 4. RST5.5 5. INTR 6. INTA
7. 7. Vectored and Non-Vectored Interrupts  In vectored interrupts, the processor
automatically branches to the specific address in response to an interrupt.  But in non-
vectored interrupts the interrupted device should give the address of the interrupt service
routine (ISR).  In vectored interrupts, the manufacturer fixes the address of the ISR to
which the program control is to be transferred.  The TRAP, RST 7.5, RST 6.5 and RST
5.5 are vectored interrupts  The INTR is a non-vectored interrupt. Hence when a device
interrupts through INTR, it has to supply the address of ISR after receiving interrupt
acknowledge signal.
8. 8. Vector addresses
9. 9. Hardware and Software Interrupts  When microprocessors receive interrupt signals
through pins (hardware) of microprocessor, they are known as Hardware Interrupts. There
are 5 Hardware Interrupts in 8085 microprocessor. They are – INTR, RST 7.5, RST 6.5,
RST 5.5, TRAP.  Software Interrupts are those which are inserted in between the
program which means these are mnemonics of microprocessor. There are 8 software
interrupts in 8085 microprocessor. They are – RST 0, RST 1, RST 2, RST 3, RST 4, RST
5, RST 6, RST 7.  A software interrupt is a type of interrupt that is caused either by a
special instruction in the instruction set or by an exceptional condition in the processor
itself.
10. 10. Software Interrupt  The software interrupt instructions are included at the
appropriate (or required) place in the main program.  When the processor encounters the
software instruction, it pushes the content of PC (Program Counter) to stack. Then loads
the Vector address in PC and starts executing the Interrupt Service Routine (ISR) stored
in this vector address.  At the end of ISR, a return instruction - RET will be placed.
 When the RET instruction is executed, the processor POP the content of stack to PC.
Hence the processor control returns to the main program after servicing the interrupt.
Execution of ISR is referred to as servicing of interrupt.
11. 11. HARDWARE INTERRUPTS  An external device, initiates the hardware interrupts
of 8O85 by placing an appropriate signal at the interrupt pin of the processor.  The
processor keeps on checking the interrupt pins at the execution of the current instruction.
 If the processor finds a valid interrupt signal and if the interrupt is unmasked and
enabled, then the processor accepts the interrupt. The acceptance of the interrupt is
acknowledged by sending an INTA signal to the interrupted device.  The processor
saves the content of PC (program Counter) in stack and then loads the vector address of
the interrupt in PC.  It starts executing ISR in this address. At the end of ISR, a return
instruction, RET will be placed. When the processor executes the RET instruction, it POP
the content of top of stack to PC. Thus the processor control returns to main program after
servicing interrupt.
12. 12. MASKABLE & NON-MASKABLE INTERRUPTS:  TRAP is non-maskable
interrupt while RST 7.5, RST 6.5 and RST 5.5 are maskable interrupt.  Masking is
preventing the interrupt from disturbing the main program.  When an interrupt is masked
the processor will not accept the interrupt signal.  The interrupts can be masked by
moving an appropriate data (or code) to accumulator and then executing SIM instruction.
(SIM - Set Interrupt Mask).  The status of maskable interrupts can be read into
accumulator by executing RIM instruction (RIM - Read Interrupt Mask).
13. 13. Contd.  All the hardware interrupts, except TRAP are disabled, when the processor
is resetted. They can also be disabled by executing Dl instruction. (Dl-Disable Interrupt).
 When an interrupt is disabled, it will not be accepted by the processor. (i.e., INTR, RST
5.5, RST 6.5 and RST 7.5 are disabled by DI instruction and upon hardware reset).  To
enable (to allow) the disabled interrupt, the processor has to execute El instruction (El-
Enable Interrupt).
14. 14. Interrupt Vectors and the Vector Table  An interrupt vector is a pointer to where the
ISR is stored in memory.  All interrupts (vectored or otherwise) are mapped onto a
memory area called the Interrupt Vector Table (IVT).  The IVT is usually located in
memory page 00 (0000H - 00FFH).  The purpose of the IVT is to hold the vectors that
redirect the microprocessor to the right place when an interrupt arrives.  The IVT is
divided into several blocks. Each block is used by one of the interrupts to hold its
“vector”
15. 15. The 8085 Non-Vectored Interrupt Process  The interrupt process should be enabled
using the EI instruction.  The 8085 checks for an interrupt during the execution of every
instruction.  If there is an interrupt, the microprocessor will complete the executing
instruction, and start a RESTART sequence.  The RESTART sequence resets the
interrupt flip flop and activates the interrupt acknowledge signal (INTA)  Upon
receiving the INTA signal, the interrupting device is expected to return the op-code of one
of the 8 RST instructions
16. 16. Contd.  When the microprocessor executes the RST nstruction received from the
device, it saves the address of the next instruction on the stack and jumps to the
appropriate entry in the IVT.  The IVT entry must redirect the microprocessor to the
actual service routine.  The service routine must include the instruction EI to re-enable
the interrupt process.  At the end of the service routine, the RET instruction returns the
execution to where the program was interrupted.
17. 17. Contd.  The 8085 recognizes 8 RESTART instructions: RST0 - RST7 ,each of these
would send the execution to a predetermined hard-wired memory location:
18. 18. Restart Sequence  The restart sequence is made up of three machine cycles  In the
1st machine cycle: • The microprocessor sends the INTA signal. • While INTA is active
the microprocessor reads the data lines expecting to receive, from the interrupting device,
the opcode for the specific RST instruction.  In the 2nd and 3rd machine cycles: • The
16-bit address of the next instruction is saved on the stack. • Then the microprocessor
jumps to the address associated with the specified RST instruction
19. 19. Contd.  The location in the IVT associated with the RST instruction can not hold the
complete service routine. – The routine is written somewhere else in memory. – Only a
JUMP instruction to the ISR’s location is kept in the IVT block.
20. 20. Hardware Generation of RST Opcode  How does the external device produce the
opcode for the appropriate RST instruction? – The opcode is simply a collection of bits. –
So, the device needs to set the bits of the data bus to the appropriate value in response to
an INTA signal. The following is an example of generating RST 5: RST 5’s opcode is EF
= D D 76543210 11101111
21. 21. Contd.  During the interrupt acknowledge machine cycle, (the 1st machine cycle of
the RST operation): – The Microprocessor activates the INTA signal. – This signal will
enable the Tri-state buffers, which will place the value EFH on the data bus. – Therefore,
sending the Microprocessor the RST 5 instruction.  The RST 5 instruction is exactly
equivalent to CALL 0028H