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    26 views17 pages

    US10679723

    Uploaded by

    Francisco
    US Patent

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    © All Rights Reserved
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    2) United States Patent 6a om ~ 0) o a @ Gt Lee et al. DIRECT MEMORY CHARACTERIZATION USING PERIPHERY TRANSISTORS, Applicant: PDF Solutions, Ine., Santa Clara, CA ws) Inventors: Dong Kyu Lee, Santa Clam, CA (US) Kelvin ¥ih-Yuh Dong, Zhubei (IW), Tuan Pham, Santa Clara, CA (US) Klaus Sehuegraf, Santa Clara, CA Schneider, Santa Clare, CA (US) Assignee: PDF SOLUTIONS, INC., Santa Clara, cA WS) Notice: Subject to any disclaimer, the tem ofthis patent is extended of adjusted under 35 USC. 184(b) by 0 days. Appl. Nos 16/211,845 Filed: Dee. 6, 2018. Im. Cl, Glic 2956 HOLL. 234528 (2006.01) (2006.01) HOI 27711526 (201701) HOLL 2166 (2005.01) GUC 1614 (2006.01), NOL 2711573 (2017.01), Gok 30/394 (202001) Go6F 30333 (202001), us. Cl CPC. GUC 2086016 (2013.01); GaBE 30/394 (2020.01); GE 1618 201301); HOLL 22/14 (2013.01); HOLL. 2/524 (2013.01), HOLL 27/11526 (2013.01); HOLL 271873 (2013.01); GosF 30333 (202001) 1US0106797. 1 3B (10) Patent No.: (4s) Date of Patent: US 10,679,723 B1 jun. 9, 2020 (58) Fleld of Classification Search CBC GLC 29/56016; GLIC 16/14: GOSE 30/394 GO6F 30/333; HOLL 27/11573; HOIL 20/11526, HOLL 23/528; HOLL. 22/14 See application file for compete seal histor: 60) References Cited US. PATENT DOCUMENTS ° 365185 19 627.188 B2* 12014 Weingarten ... GOBE 111068 6918509 2060: ‘Goin 312889 3245008 * cited by examiner Primary Esaminer —Bac 8 Aw (74) Attornes, Agent, or Firm Pittman LLP Pillsbusy Winthrop Shaw on Disclosed is a system and method for perfoming direct memory characterization of memory ces ina memory array ‘sing peripheral transistors. A memory array is fabricated using a:mask layer defining routing for a set of first staze periphery transistors electrically connected to the word ines of the memory array. A revised mask is used for defining a tiflerent routing fora set of second stage periphery transis- ‘ors including different characteristics than the first stage periphery transistors, Testing is conducted by applying. a ‘Simulated Erase signal to the nonvolatile memory cells and determining which cells ate erssod. Based on this test, ‘certain characteristics ofthe fist andor second stage periph ry transistors can be identified that provide improved conditions for the noavoltile memory cells A prodet chip san be manufactured using modified versions of the fist sage periphery transistors that incomporate the charaters- ties that provide the improved condition(s). ABSTRACT 20 Claimns, 9 Drawing Sheets MEMORY. ARRAY 400 ‘ © US 10,679,723 B1 Sheet 1 of 9 Jun. 9, 2020 U.S. Patent (uy 40nd) Old TOL s0yssuesy 9jag e+ g DOT N29 Aiowew &~{) 8 is ee eto He sep , tH onc ve + ack Hie PE OH HE 3 x] Benepe eof ei 2 i OOL AVEYV ANON (2ur7 POM) IM. eee (eur vg) Te US 10,679,723 B1 Sheet 2 of 9 Jun. 9, 2020 U.S. Patent v2 ‘Old OFT (ueyduied) sped urea Q BOT (Atoydued) sped aye a . aa ba | adfy soysisuesy Auoydueg 7 TOT s0;s}suesy y99;9g aq DOT 199 Aiowey @-{|{ we V00e AVEYV AXONS U.S. Patent Jun. 9, 2020 Sheet 3 of 9 US 10,679,723 B1 FIG. 2B MEMORY ARRAY 200B Gate Pads (Periphery) 128 e s e4 2 oS a o 3 3 a g Z a “I fw Select Transistor 107 Periphery Transistor Type 1 Periphery Transistor Type 2 * « 2 ae 2 ole gala sass EEE US 10,679,723 B1 Sheet 4 of 9 Jun. 9, 2020 U.S. Patent Ve “Sls eounos, e ujerg 1 area a SNOUIPA JO} YSIXO Appayje sioysisuey J9yjQ = vir PTT aur7 (eI, STM 0} pajouucs 5Or suojsisues) jeulbuC s a 00€ SS300ud US 10,679,723 B1 Sheet 5 of 9 Jun. 9, 2020 U.S. Patent ge ‘Sid anos BuiBueyo ym UONEN|EAS JO} SIMA 0} JOOUOD. S vi PTT our ele SM 0} paysauuoo siojsisuey jeulbuCQ S at 00€ $Ssd90dd US 10,679,723 B1 Sheet 6 of 9 Jun. 9, 2020 U.S. Patent oe “Sls yy6ue7, AID Pey!POW, a sesodind SNOUeA JO} ISIKe Apeaiye sioysisuey ioujo S vir DTT aur ein STM 0} pejseuu0d suoysisues) jeulBUC Ss ar U.S. Patent Jun. 9, 2020 Sheet 7 of 9 US 10,679,723 B1 FIG. 4 MEMORY ARRAY 400 US 10,679,723 B1 Sheet 8 of 9 Jun. 9, 2020 U.S. Patent s ‘Old Ca) SONSHSEIEYO PeyHUEp] By) epNjou] yey) sioysisues) Aueydued Buisr sijeq Koweyy eunjoenuey + we sile9 Aiowew 40} uoRIpuod penouduu} 104 sonsHe}eIeUD AjRUEPI + 3 ys01 Buung paserg ary sja9 Aioway YoIyAA euILA}eg ‘ sij@9 A1oway 0} feubig eseu3 peyeinwig Burkiddy Aq ysay yonpucg 4 rE —~I siojsisues, Aiayduied aBeig puoseg 01 Bunnoy auyag o1 ¥SeW asinoy 4 sio}sisuesy Areydueg e621 ysi14 0} Sunoy seuyeg yseWy [eUIBUO 005 SSd00ud US 10,679,723 B1 Sheet 9 of 9 Jun. 9, 2020 U.S. Patent 9°SId vous | rp cis) AANYSLNI 509 i) aoinag ynduy i \ 1 ™, ‘B01Aeq 10S. ee (suosseoag tt t \ ' 05 708 ' ee pe}UL wayskg ' SHOMION Kiowiayy \ l------ 05 DRIOMLEN Janieg, K/ 8e5 sones | reg wones | ggg yy 009 WALSAS US 10,679,723 BL 1 DIRECT MEMORY CHARACTERIZATION USING PERIPHERY TRANSISTORS TECHNICAL FIELD. This disclosure relates generally to testing and develop- ‘ment of wonvolatile memory arrays, and more partiulaey t0 improved tochnigues for charscterizing nonvolatile memory cells in a memory ary using one or more sages of Periphery transistors BACKGROUND ‘To increase memory density, memory products are con- ventionally formed as an array structure consisting of & ber of single memory cells sharing the same word ine (CWL”) andor the same bitline ("BL"). FIG. 1 depicts @ block diagram of an example nonvolatile memory” array ‘configured with a plurality of WL pads and BL pals in 3 ‘direct probing characterization vehicle used for testing pr poses aosonding tothe prior an. Prior art memory ata’ 100 may bea nonvolatile memory array. Inthe diagram, peor at ‘memory amy 100 is shown comprising a plurality of WLs 102 and a plurality of BLs 104 arranged in a eross-point ‘configuration, wherein each memory cell 106 is located at ‘one ofthe intersections of the WLs 102 and Bs 104, ith, a comesponding set of WL pads 103 and BL pads 108 disposed around the periphery of the memory stray 100. The WL paals 103 andlor BL pads 105 can be used for receiving test probe devi that can perform testing on the memory cells ofthe memory array according to one or more testing algorithms as would be appreciated by persons of onlinary stall nthe ar. in the diggram, the WLs 102 and BL 104 are directly connected tothe probing pas 103 and 108, respec tively. Memory amy 100 further includes a set of select transistors 107 that are used to gate signals driven out onto the BLs 104 of the array. ‘To access a specific memory cell, voltage bias levels are applied to the memory cell during an appropriate time period. When this happens, neighboring memory cells that share ether the same WL andior BL are known to sur "unwanted stress conditions. This ean disturb the neighboring cells, and in some cases cause the value stored in the ‘memory cello change to an incorrect value (eg. the stored Bit value inthe memory cell can be lipped fom zero (0 @ ‘one or from a one to a zero, Disturbance isthe tem of at used to deseribe such unwanted stress conditions Fo the ‘array’strocture during operations such as writing data to the ‘memory cells (Program), erasing data (Erase) stored in the memory cells, or reading data (Read) fom the memory cals ile memories such as for example fleating gate memories, use high impedance conditions ("Hi-Z") across the memory cel transistors ofthe neighboring memry cells ‘o improve immunity to such disturbance. In Boating gate memories, Program operations inject electrons. from the ‘memory cell irinsistor bulk channel into the change trap Jayer (hating gate), whereas Erase operations pul electrons ‘out of the change trap layer back into the bulk (or channel) ‘of the memory cell transistor. The difference between the ‘eased -memory cells and erase-inhibited neighboring remory cells is the gate potential of the memory cell transistor For example, Flash memory uses a high gate-o-channel (orwell or bulk) elevtic field across the cell transistor ofthe ‘memory cell to Frase a memory cell or block of cells. After ‘1 Program operation the selected memory cells or block of 0 2 cells should be erased and nejghboring memory cells should ‘not be erased, The electric potential gap between the gate ‘and hulk or ehtnnel ofthe cell transistor should be high for the erased memory cells and should be held close to zero volts for the erase-inhibited neighboring. memory cells. ‘erefore, in prior at solutions the operating conditions of the memory cells should be carefully selected 10 avoid inducing a high electric field in the neighboring memory cells that are aot being aocessed, but that share either the same WI. or BL. This can help prevent the bit values (zero fr one) programmed into the neighboring, memory cells fom being adversely affected during any Program, Erase andior Read operation In general, Hoating gate nonvolatile memories use Hi-Z conditions forthe neighboring memory cells to counteract the electric field disturbance that may arise across the neighboring memory cell asa result of accessing the target ‘memory cells. To cancel ont the electric Field across the gate ‘and channel of the neighboring memory’ cell teansstors, prior art solutions apply # reversed bins having the same ‘magnitude between the gate voltage and the channel (or well or bulk) voltage during a specified time period to inhibit erasing the neighboring memory cells. In prior at solutions, {his is accomplished using sophisticated circuit design toch. niques which require addtional cieuits and precise syn- chronization. Such circuit techniques are employed in conventional ‘ethos to prevent the gate potential of the erase-inhibited ‘neighboring’ memory cells rom dropping too low. Ithe gate potential of the erase-inhibited memory cells drops too low. the reverse bias applied across the noighboring memory cells ‘may aot be high enough to inhibit it from Mipping to an ‘incorrect value, causing a failure in the memory aeay. The root cause of such failure stem from the characterises of the transistors that drive Program, Fase of Read signals out ‘onto the nonvolatile memory cells ofthe memory array. The agate potential ofthe neighboring memory cells can bacome {oo low due to hip leakage current from the transistors that drive signals out to the memory cells andlor high parasitic ‘apacitance coming from the driving trasisiors, I'he drain (or source) of driving transistors are leaky or the gate capacitance and/or junction capacitance ofthe driving tan- sistors is high, the momory cell gate potential becomes 100 Tow and the memory cells are accordingly susceptible to being inadvertently erased, Adkitionally, during testing ofthe memory aray, the gate capacitance andr junction capacitance af the memory cell {ransistors can beeomte too low because of the high parasitic loading capacitance stemming from the testing deviee (eg. ‘est probe) structure, outing, andior pad probing. SUMMARY, In one aspect, the techniques deseribed in this disclosure fre directed toa system and method in a memory array fabricated on « semiconductor substrate comprising a ph rality of nonvolatile memory cells electrically connected ‘with a plurality of word fines and bit lines arranged in the mory array such that each memory cell i disposed at an ‘one of the word lines and bit lines in a exoss- imilar configuration, The memory array ean be point or fabricatedon the semiconductor substrate using amask layer that defines a routing configuration wherein each word line js electrically connected with one ofa plurality of fist stage periphery transistors. The mask layer can be revised (oF a Special mask layer constructed) to define a second routing configuration different from the fist outing configuration US 10,679,723 BL 3 for eleticaly connesting 2 group of one or more of the word Fines ofthe memory aay with one of a plurality of second stage periphery transistors dit include one or more ‘harictersicydlfeent fom the eoresponding characterise ties of the ist stage periphery transistors. The fist and secon stage periphery transistors ach nce agate region lectrcally connected with gate pad ana devin (r sours) region electrically connected with drain (e source) pad in the memory amy. The gate and drain (or souree) pas can be used for connecting witha testing probe device for performing testing operations on the nonvolatile memory feels of the memory’ aay This aspect furtr includes conducting one or more texts based on applving the test probe to one oF ore of the gate pads and dia (or source) pads ofthe purity of fist and Second stage periphery tansstor The test may’ inelude (I) applying simulated erase signal the nonvolatile memory cells the word lines of the memory array via te fist and second stage periphery transistors: and (2) detemniing which ofthe navolale memory cells ae erased during the test. Based on the rss ofthe test, one oF more eharae- terintice ofthe int andor second stage periphery trnsstrs ‘cat be ideniid that provide one or more improved conde tions for the nonvolatile memory cells in the memory array. > ‘A product chip containing the memory array of noavoll- tile memory cells ean then be manufactired using modified versions of the plurality of fist stage periphery lransistors that each incorporate the identified characteristics providing the improved conditions) forthe nonvolatile memory cells ‘he improved conditions may include reduoed gate ‘capacitance andor junction capacitance level forthe modi fied periphery transistors and the identified characterisies may be adapted to reduce the gate capacitance andlor junction capacitance level associated with the modified periphery transistors. The improved conditions may also Include reduced leakage currents from the mesifed periph- ‘ery transistors and the identified characteristics may be adapted to reduce the leakage currents associated with the modified periphery transistors, BRIBE DESCRIPTION OF THE DRAWINGS ‘The above aspects and other festures of the innovative techniques deserted in tie dislosure will eeome apparent to those skilled in the art upon review of the following ‘description in conjunction with the accompanying. Figures, ‘wherein FIG. 1 depicts. block diagram of an example nonvolatile memory areay configured with a plurality of WL pads and BBL pads used for testing purposes in accordance with the prior a FIG. 2A depicts @ conceptual diagram of an example ‘embodiment of a memory aray having WI. pads replaced by ‘plurality of periphery transistors for testing purposes in sevordance with the techniques describad inthis dislosure FIG. 2B depicts a conceptual diagram of an example ‘embodiment of a memory aray having WL pads replaced by 4 plurality of periphery transistors of different types fo testing purposes in accordance with the techniques deseribed in this disclosure. FIGS, 3A-3C depict an example embodiment of process for direct. memory characterization using a plurality of periphery transistors stages for testing purposes in accor- ‘dance withthe techniques described inthis disclosure. TIG. 4 depicts » conceptual diagram of an example ‘embodiment of a memory array having WL pads and BL. 0 o 4 pads replaced by a plurality of periphery transistors for ‘esting purposes in accordance with the techniques described inthis disclosure, FIG. 5 depicts conceptual flow chart depicting an ‘example embodiment of a process for direct memory char- acterization using periphery transistors in accordance with the technigues described in this disclosure FIG. 6 depicts an example overview block diagram of 3 system upon which the embodiments described in this disclosure may be implemented DETAILED DESCRIPTION OF THE EMBODIMENTS, ‘Throughout this description numerous details are set forth n order fo provide a thorough understanding of the various embodiments described in this disclosure, which ate pro- Vided as illustrative examples to enable those of skill in the arte practice such embodiments. will be apparent those stile in the art, however, that the techniques described in this disclosure may be practiced without some of these specific details or in other instances, well-known structures The drawings and examples provided are not ued 10 Tit the seope (0 auy single embodiment, 38 oxer embodiments are possible by way of interchanging oF clements ‘Where csnsin elements of these embodiments can be rarially oF flly implemented wsing Known components, fly those portions of sich kaowa components that art necessary for an understanding ofthe embodiments will be described and detailed descriptions of eher potions of sich ‘now components willbe omited so as oto obscure the description. Moreover applicants do nat intend fr anything inthe specification orelaims tobe ascribed an uncommon or special meaning unless expicly et for as sos, Furor tho seape ofthe described embodiments encompasses pres: cat and ft known equivalents the components refered to herein by way of iustation ‘The techniques described inthis disclosure are dicted to 4 method for characterizing nonvolatile memory ells of @ ‘memory array wing one oF more sages of penipery tant stor located dace tothe memory array to find the most ‘lable periphery traitor conditions. In memory arays there ae Topi pte, such as NAND, NOR, XOR, XNOR, cult around the ery and sed rive signals oto the ‘memory eels inthe memory array via the WLs or BLs for performing Program, Erne and Reid operations. These Fogic gates may’ comprise various eircuit elements such a8 auress decoders, seaseampliien, WL diver, BL divers, te, which may be arranged in several loge stages and may comprise several dillerent types and sies of transistors tt include differen transistor characterises (eg. width, length andlor doping profi, cc). The transistors for these logic stages are refered to in the art as “perphry trans tos ty are pysealy disposed andthe erie HG. 28 depicts a conceptual diggam of an example embodiment of a memory aray having WL pads replaced by {plurality of periphery trusistors foe tesing purposes. At the ots it should be noted that although cain elements ‘ay bo dpictd as separate componcas, in some instances fone or more of the components may be combine info & Single device or sytem. Likewise, although cera Tine: tionality may be deseibed as heing performed by a single clement or componeat within the system, the Functionality US 10,679,723 BL 5 may in some instanees be performed by multiple compo- nents or elements working together in a Tunetionally coor inated manner. In addition, hardwired cireuity may be used indepen ‘dently or in combination with software instretions to imple ‘ment the techniques described in this disclosure. The ‘embodiments describe in this disclosure are not limited t0 any specific combination of hardware oF software. For ‘example, the described funetionality may be performed by ‘custom hardware components containing hardwired logic Jor performing operations, by general-purpose computer hardware containing a memory having stored thereon pro- tgrummed instructions for perfomning operations, or by any ‘combination of computer hurlware and programmed com- ponents, The embodiments may als be practiced in dstib- uted computing environments, such asin private or public ‘loud network, where operations may be performed by remote data processing devices or systems that are in ‘communieat ‘or wireless networks, In FIG. 2A, the WLs 102 of memory array 200A. are ‘connected tothe source terminals ofthe periphery transistors ‘of Type 1. The Type | periphery transistors may include, for ‘example, the transistors that deve signals out onto the gate terminals 117 of the memory cells 106, Inthe illustrated ‘embosiiment, each of the Type 1 periphery transistors are shown as including a gate probe pad 108 anda drain probe pad 110, In one aspect, the Type I. periphery transistors perform the function of isolating the WL 102 irom the gate probe pads 108 and the drain probe pads 110 s0 that the parasitic capacitance of the test probe does not reach the WLs 102 when connocted withthe probe pods 108 and 110. The parasitic capacitance on the WL 102 as seen by the pate terminals 117 ofthe memory cells 106 such configuration js much smaller than the parasitic capacitance that would be seen on the WLs 102 from the testing probe stricture, routing and/or WL or BL probing pads that are replaced by ‘connections tothe periphery transistors. In alton, in a product chip the characteristics of the different periphery transistors can be different de to their physial placement in the chip and due to interference from Surrounding componentry (eg. neighboring ellets, local Tayout effects, ete). The techniques described herein are ‘adapted to optimize he transistor characteristic ofthe such periphery transistors. The periphery tansisiors used for the Innovative techniques ofthis dislosure canbe used from the periphery transistors (suchas Type I shown in the figure) in ‘4 memory array of an existing product chip. The existing periphery transistors of various stages in an existing memory uray operate Jor their own purposes in the product chip. The ‘described techniques are adaptod t change the routes of these existing periphery transistors to connect them with the ‘gate terminals 117 of the memory cells 106 in the memory ‘array 200A for testing. This may be accomplished using a sliffoent mask layer (generally a metal mask) to provide the foutes fo the connections regardless of their original funetion(s) inside the produet chip. The periphery transistor ude logie stages built array that are used to drive signals onto the array (ea, deving trunsistors forthe WLs andor BLs of the memory array). The periphery transistors may also include other periphery tansisors at different stages and having different factions as will be discussed in more detail below. In other embodiments, the periphery transistors of ‘Type 1 can be specially consimcted on a test vehicle specifically designed for lest a with one another through one or more Wired. 0 o 6 ‘When using the periphery transistors already on an exist ing product chip, a mask revision or special mask—such as those used in, for example, Direct Probing Characterization Vehicle ("DPCV") solutions—may be used to revise the ‘metal routing to connect the existing periphery transistors to the appropriate one ofthe memory cells in the memary array for testing. So while there may not be complete freedom for the circuit designer to select transistor sizes forthe existing periphery transistors on a particular memory ary 200A in f product chip, there are many diferent types of periphery transistors already available that can be connected with the siemory cells 106 via the WLs 102 and/or BLs 104 of the ‘memory array using a revised mask or special mask, whieh is different from the mask used for connecting the WLs and BBLS to the orginal driving transistors inthe product chip. The revised or special mask layer may change the routes ‘on the original product chip to connect some oral the WLs 102 audios BL 104 to other sets of periphery transistors (| dierent stages and different types, sizes, et.) to obtain a Tull set of data upon which the testing algorithm cin evaluate the periphery transistors and determine the most suitable ‘ransistor characteristics to mitigate the leakage eurents and gle capacitance andior junction capacitance issues seen at the gate terminals 117 of the memory cells 106. In atleast certain embodiments, only some of the routes are changed and some of the original routes are left in place so that the testing algorithm can provide a dataset to compare the rwlatve characteristics of the original driving transistor stages withthe newly connected periphery transistor stages ‘using the modified o special mask layer. There ae generally ‘many different sets of stages of periphery transistors that already exist in a product chip with many different functions fd characteristics that may aot he related to testing. The isclosed techniques ulize such transistor logic stages for the evaluation purposes regardless of ther original function inside the produet chip. "The disclosed techniques may utilize different sets of periphery transistors fr testing a st of memory cells 106 t0 tense the logie stages of any neighboring memory cells are ‘ot improperly ipped to an incorrect value during Erase operations. For example, FIG. 2B depicts 2 conceptual iagram of an example embodiment of a memory array having WI. pade ceplaced by a plurality of periphery tran- istors of dllerent types for testing purposes in aevordance with the techniques described in this disclosure, Each ofthe ileren types of tests ean be ron onthe memory aeray 2008 ‘using testing algorithm and testing probe devieo(s) that is configured to connect with the gate pads 128 andor drain pads 130 of the periphery transistors of both Type 1 and Type 2 as shown in the figure. The different periphery teansistors (eg., Type 1 and Type 2 as shown in FIG. 2B) ‘may be used together with one or more testing algorithms 10 interrogate the memory seray 2008 aad perform the testing ‘operations using each of « plurality of different sets of periphery transistors Type 1 and Type 2 to discover the transistor characteristics (such as transistor width, length, \Width-o-length ratio, doping profile, ete) that provide the ‘most suitable conditions for the memory eels 106 in the nocy array 2008 from the perspective of reducing gate capacitance andior junction capacitance and leakage eur ens on the WLS 102 as diseussed previously. The testing ‘an be performed by placing the test probe onthe gate pads 128 andior drain pads 130 ofthe periphery transistors and by ‘sing a testing algorithm. In other aspects, the configuration of the source or drain ofthe peripbery transistors may be ‘ed interchangeably for testing depending om the particular ements US 10,679,723 BL 1 ‘he characterises for the driving transistors that provide the most suitable conditions for the memory cells 106 may be ascertained! based on the reslis of the testing. These results ean then be wsed to optimize the characteristics ofthe driving transistors that dive the Program, Erase or Read signals out onto the memory ees 106 inthe memory array 2008, for example, by revising the transistor characterises such as transistor widths, lengths, width-to-length rion, andor doping profiles, ete, of the driving transistors. These ‘charicteistcs can then be used in manueturing the final product. In particular, the driving transistors ean be designed (o minimize leauge currents and parsitie capacitances for the various diffrent transistor sizes that wero discovered during testing. In sum, based on the evaluation results, the Type | transistors ean be changed toa new Type I transistor having. characteristics that improve the condition of the memory cells in the memory array TIGS, 3A-3C depict an example embodiment of a process for dicect memory characterization using a plurality of periphery transistors siages Tor testing purposes in accor 2 ‘dance with the techniques described in this disslosure. The ‘ystrated embodiment in FIG, 34 shows memory cells 106 having WLs 102 connected withthe original driving tran- sistors 112 (periphery transistors) via metal routing ines 18 as well a other periphery transistors 114 already existing on the produet chp for various purposes. Process 300 continues ‘on FIG. 3B which shows some of the original WLs 102 have been disconnected from the original driving tansistors 112 and connected instead with the other periphery transistors 114, This can be performed using a revised or specially ‘constricted mask layer that inclies the outing to the other periphery transistors 114 using metal routing Hines 118 as Shown. At the mask revision, some of WLs 102 renin ‘connected to the original transistors 112 for comparison, and folhers are connected to different types of trsistrs for ‘evalation, Process 300 continues to FIG. 3C. After testing is con- “ducted and the periphery transistor chareteristies have boon, ‘deified that provide the most suitable conditions for the memory cells 106, the produet chip ean be manufactured using the optimized transistor characteristics for the original «diving transistors 112 connected with the WLs 102 of the memory aray. IF the test results indicate lavorable condi- tions fora longer gate length for the transistors hen the gate length of the WL driver transistors ia the final product cua be manufactured using an increased gate length as long as the layout space on the chip permis. Indeed, in certain aspeets the parasitic capacitance andor leakage currents can be made Design of Experiment DOE") with varying the Jayout properties ofthe periphery transistors to confim an soceptable capacitance andor junction leakage level with the layout properties of the transistors. The layout properties ‘ean include transistor souree are, junction profile, transistor ‘gate width andlor gate ide thickness ete. In this example, ‘4 modified gate length for the original periphery transistors 112-in particular, a larger gate fength was determined during the evaluation and used in manufacturing the final product chip. The meta lines 114 ate shown coanected back to the modified original driving transistors 112 forthe WLs 102 of the memory array: This completes process 300 in ‘seconiance with one example embodiment. "The techniques descried above with respect to the WL 102 ofthe memory array ean be usd inthe same manner for the BLs 104 of the memory army. FIG. 4 depicts a concep- ‘wal diagram of an example embodiment of memory array having WL pads and BL. pads replaced by a plurality of Perilery transistors for testing purposes in accordance with 0 o 8 the techniques described in this disclosure In this example, memory aay 400 includes periphery transistors of Type 1 ‘connected with the WEs 102 and Bs 104 In particular, the Type 1 periphery trnsistors connected with the BL.s 104 include their own gate probe pads 120 and drain probe pads 122 used for testing purposes in accondance with the th- niques deseribed in this disclosure FIG. 5 depicts a conceptual flow chart depicting an ‘example embodiment ofa process for direct memory char- acterization using periphery tramsistors in accordance with the techniques deseribed inthis disclosure. It is noted that the process deseribed helow is exemplary in nature and are provided fr illustrative purposes and ot intended to limit the scope of the disclosure to any. particular example embodiment. For instance, methods in accordance with sone embodiments described in this disclosure may inelude ‘omit some oral of the operations deseribed below or may include steps in a different order than deseribed in this disclosure. The particular methods described are_not intended to be limited 10 any panicular set of operations exclusive ofall other potentially intermediate operations. In addition, the operations may be embodied in computer- executable code, which may cause a general-purpose or special-purpose computer hardware to perform operations. In other instances, these operations may be performed by specific hardware components or hardwired circuitry, or by ‘any combination of programmed computer components and feastom hardware citcuitry ‘In at Teast certain embodiments, process $00 refers tothe clements and components descr above with respect to PIGS, 2-21 aod 34-32 including a memory array’ fabri. cated on semiconductor substrate comprising a plurality of nonvolatile memory cells 106 electrically connected with 3 plurality of Ws 102 and BL 104 arranged such that each ‘memory ell 106 is disposed at an intesecting one of the WLs 102 and Bs 104 and ananged in a cross-point configuration. The memory array may be fabricated on the semiconductor substrate using & mask layer defining the routing configuration that eletecally connects each WL 102 with source (or drain) of one of a plurality of first stage periphery transistors that is used for driving the Program, Erase and Read signals out t the memory cells 106 in the memory are. Process 500 begins at operation block S02 wherein the original mask layer defines the routing on an existing product chip from the frst stage periphery transistors (ez Ariving periphery transistors 112 of FIGS. 3A-3B) to the memory cells 106. This outing includes connections between the driving periphery transistors 112 and the gate terminals of the memory cells 106 in the memory array. ‘Once the existing product goes into testing, at operation S04 a revised mask can be used to define new routing for some for all of the WLs 102 50 that they connect with a set of second stage periphery transistors (c.g, transistors 114 of FIGS. 3A-3B) already existing on the product chip for various purposes that may be unrelated to testing. This may include a specially constructed mask layer ora revised mask Jayer that defines the second routing configuration for elee- {really eonnecting group of one or more of the word lines of the memory array with one the second stage periphery none aspect, the second routing configuration is different from the fist routing configuration, The second periphery ‘ransistors may include one or more characteristics different from the conesponding characteristics of the fist stage periphery transistors, The frst and second stage periniery US 10,679,723 BL 9 transistors each have a gate region electrically eonnected with a gate probe pad andor a desi (or source) probe pad. Process $00 continues at operation $06 wherein one oF more tests are conducted on the memory cells ofthe memory array based on upplying a test probe to one or more of the ‘gate pads andor drain (or source) pads of the frst and Second stage periphery transistors. In one embodiment, the ‘est may include (1) applying simulated Erase signal to the nonvolatile memory eells on the WLs 102 of the memory ‘array via the fs and second stage periphery transistors, and (Q) determining which of the nonvolatile memory cells are ‘erased during the test. Based on the results ofthis test, ether the erased cells were supposed to be ered, and hence are ‘acceptable, or were supposed to be erase-inhiited, and hence a memory failure has occurred. This determination is made in process 500 at operation 508. Process $00 continues to operation $10 whereby the {information obtained from the one or more tests ean then be used to identify characteristics of the first andior second sage periphery transistors that provide one or more ‘improved conditions forthe nonvolatile memory cells in the setory stray. In one embodiment, the improved conditions may include reduced gate capacitance andlor junction ‘capacitance level forthe modified periphery transistors and the identified characteristics may be adapted to reduce the gale capacitance andlor junction capacitance level assoc ‘ated with the nonvolatile memory cells, The improved ‘conditions may also include reduced leakage curents in the dled periphery transistors and the identified character Istcs may be adapted to reduce the leakage currents asso-

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