6.

VLSI System Design  

Fees (Rs.)Module
Foundation Course on ASIC Design, RTL coding for a simple sequence,
VLSI Physical Introduction to Place and Route, Design Setup, Floor planning
Design & (Lecture), Timing Setup, Placement, Clock Tree, Synthesis, Routing,
80 12000.00
VerificationTo Post- and in-route optimization and CTO, Design for Manufacturing,
 
picsHrs. Writing files for Static Timing Analysis sign-off, Physical Verification,
Introduction to DRC, ERC, LVS
TOOL Options(or both)
SYNOPSYS
 Astro 2004.06
 Formality 2004.06

 PrimeTime 2004.06

 StarRC-XT 2004.06

 Jupiter XT 2004.06

 Hercules 2004.06
Introduction to Verilog/VHDL, 60
Verilog/VHDL programming
styles, Basic FPGA Architecture
FPGA design techniques,
Spartan/Virtex FPGA
architecture, Synchronous
Design Techniques
Synthesis Techniques, Core
generator, DSP/Communication
IP, EDK introduction, Embedded
C Programming, Microblaze/PPC
architecture, Hardware Design,
Adding Custom IP’s to Designs
Software/Application
Development, H/W & S/W Co
verification, Case studies
(development of complex
applications)
Tools Used:
Xilinx ISE 7.1, Xilinx Core
Generator, Xilinx EDK, Model
Sim
 
ASIC Introduction to Synthesis, Effective RTL Coding for Logic Synthesis, 80 10000.00
 Partitioning for Synthesis
Synthesis, DC Tcl – An Introduction, Timing Issues in ASIC’s, Static Timing
testing, timing Analysis, Compile Strategies
analysis & Before, During and After Synthesis, High Level Synthesis, Advanced
formal Logic Synthesis, Design for Testability, Understanding Scan Testing,
verification Controlling Formality, Setting up and running Formality, Debugging
designs proved not equivalent
TOOLS USED
SYNOPSYS
 Design Compiler 2004.06
 PrimeTime 2004.06

 Formality 2004.06

 DFT Compiler 2004.0

Introduction, What is Verilog? 60
What is SystemVerilog? How do
they compare to VHDL?, Verilog
Basics, Procedural Code, Tasks
and Functions, Understanding
tasks • Task arguments • Task
synchronization • Functions, A
Better Verilog (Start point for
Verilog users), SystemVerilog –
Better RTL descriptions;
assertion-based verification;
high-level verification,
Improving RTL Productivity,
Interfaces, Clearing the
Verification Bottleneck,
Assertions
Introduction to High Level
Verification
Tools Used:
• VCS 7.1 (Synopsys), NC Sim
 
CMOS layout for IC Design, Managing Data and CAD Environment,
Understanding RC effects in the design, Plan, Draw and Verify a leaf
CMOS Digital
cell, Recognizing the parts of a Schematic, Assembling and verifying a
Design and 80 10000.00
Layout Hierarchy, Design and draw a Datapath FUB plan, Determine a
verification
layout schedule, Draw and verify the Datapath cells and Datapath FUB,
Incorporating engineering change into layout. Scripting using PERL.
TOOLS USED
 H-Spice

 Tanner S-Edit
  Tanner L-edit

 Tanner LVS