Digital

& Microprocessors
(Solutions for Volume‐1Class Room Practice Questions)

03. Ans: (c)

01. Number System Sol: In 2’s complement representation the sign
bit can be extended towards left any number
of times without changing the value. In
01. Ans: (d)
given number the sign bit is ‘X3’, hence it
Sol: 135x + 144x = 323x
can be extended left any number of times.
(1×x2 + 3 × x1 + 5 × x0)+(1×x2+4×x1+ 4×x0)
= 3x2 + 2x1 + 3x0
04. Ans: (c)
 x2+3x+5+x2+4x+4 = 3x2+ 2x + 3
Sol: Binary representation of +(539)10:
x2  5x  6 = 0
(x6) (x+ 1) = 0 (Base cannot be negative) 2 539
2 269 –1
Hence x = 6.
2 134 –1
(OR) 2 67 –0
As per the given number x must be greater 2 33 –1
2 16 –1
than 5. Let consider x = 6 2 8 –0
(135)6 = (59)10 2 4 –0
2 2 –0
(144)6 = (64)10
1 –0
(323)6 = (123)10
(59)10 + (64)10 = (123)10 (+539)10 =(10000 11 0 11)2= (00100 0011011)2
So that x = 6 2’S complement  110111100101
Hexadecimal equivalent (DE5)H
02. Ans: (a)
Sol: 8-bit representation of 05. Ans: 5
+12710 = 01111111(2) Sol: Symbols used in this equation are 0,1,2,3
1’s complement representation of Hence base or radix can be 4 or higher
 127 = 10000000. (312)x = (20)x (13.1)x
2’s complement representation of 3x2 + 1x +2x0 = (2x+0) (x+3x0+x-1)
 127 = 10000001.  1
3x2+x+2 = (2x)  x  3  
No. of 1’s in 2’s complement of  x
 127 = m = 2 3x2 + x + 2 = 2x2 + 6x + 2
No. of 1’s in 1’s complement of x2 – 5x = 0
 127 = n = 1 x(x –5) = 0
 m: n = 2:1 x = 0(or) x = 5
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x must be x > 3, So x = 5
Examples
1. A = +7 0111
06. Ans: 3 B = +7 0111
Sol: 1235 = x8y 14 1110  x y z
1  52 + 2  51 +3 50 = x.y1 + 8 y0 2. A = +7 0111
25 + 10 + 3 = xy+8 B = +5 0101
12 1100  x y z
 xy = 30
3. A = –7 1001
Possible solutions: B = –7 1001
i. x = 1, y = 30 –14 10010  x y z
ii. x = 2, y = 15 4. A = –7 1001
iii. x = 3, y = 10 B = –5 1011
–12 10100  x y z
 3 possible solutions exists.

07. Ans: 1 02. Ans: (b)

Sol: The range (or) distinct values Sol: Truth table of XOR
For 2’s complement  –(2n–1 )to +(2n–1–1)
A B o/p
For sign magnitude 0 0 0
n–1 n–1
 –(2 –1) to +(2 –1) 0 1 1
Let n = 2  in 2’s complement 1 0 1
– (22–1) to + (22–1 –1) 1 1 0
– 2 to +1  –2, –1, 0, +1  X = 4
n = 2 in sign magnitude  –1 to +1 Stage 1:
Y = 3 Given one i/p = 1 Always.
X–Y=1 1 X o/p
-----------------
02. Logic Gates & Boolean Algebra 1 0 1 = X
1 1 0 = X
01. Ans: (c)
Sol: Given 2’s complement numbers of sign bits For First XOR gate o/p = X
are x & y. z is the sign bit obtained by Stage 2:
adding above two numbers.  Overflow is X X o/p
indicated by = x y z  x y z -----------------
0 1 1
1 0 1
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For second XOR gate o/p = 1.

Similarly for third XOR gate o/p = X & for At A
0 1 2 3 4 5 6 7 8 9 10
fourth o/p = 1
For Even number of XOR gates o/p = 1 At P
For 20 XOR gates cascaded o/p = 1.
At Q

03. Ans: (b) At R

② ④
Sol: ① ③
At B
w,x w,x
y,z y,z
1 1 1 1 06. Ans: (c)
1 1 1 1 1 1 1 1 Sol: x 1  x 3  x 1 x 3  x 1 x 3  y

1 1 1 1 x2  x4  x2 x4  x2 x4  z
yz
1 1 1 1 x 1  
 x3  x2  x4 
v=0 v=1  y  z  0 , when y = z
x  option (c) is true
For all cases option A, B, D not satisfy.
04. Ans: (c)
Sol: 07. Ans: (b)
f1 x Sol: M(a,b,c) = ab + bc + ca
f2 f4
M(a , b, c) = b c  a b  a c
M(a, b, c ) = ab + b c + c a
f3
M( M (a , b, c) , M(a,b, c ), c)
x  f1f 2
= b c  ab  a c (ab  bc  ac )
f4 = f1. f2 + f3
 (ab  b c  ca )c  b c  ab  a c c
 b c  ab  a c ( ab  b c  ac )
05. Ans: (d)
b c  ab  a c (c)  abc
Sol:
= ab c  abc  abc  abc
A Q B
= c[ab  ab]  c[ab  ab ]
P R =  m(1, 2, 4, 7)
 M (x, y, z) = a  b  c
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Where x = M(a , b, c) , y = M(a,b, c ), z = c 02. Ans: (b)
Sol: ab
cd 00 01 11 10
08. Ans: 40 00 1   1
Sol: t(ns)
t=0 t = 20 t = 40 t = 60 t = 80 01  1
(A) 
11 bc
(C)
B(without delay) 10 1 
B (with delay) 
bd
A B (with delay)

Z(without delay)
f bdbc
Z (with delay)
40 n sec

03.
Sol: x+w
 Z is 1 for 40 nsec POS wz
xy 00 01 11 10
00 0  0 0
09. Ans: (c)
01 0  1 1
Sol: Logic gates X  Y  XY  XY1
11 1 1 1 1
Where Y1  Y
10 0  0 0
y
It is a NAND gate and thus the gate is
‘Universal gate’. = y(x+w)

SOP wz
03. K‐Maps xy 00 01 11 10
00 0  0 0
01. Ans: (b) 01 0  1 1 wy

Sol: wx 11 1 1 1 1
yz 00 01 11 10
1 10 0  0 0
1
00
xy
= xy+yw
01  1

11  1 SOP: x y + y w
POS: y(x + w)
10 1 
1

04. Ans: (a)

Sol: For n-variable Boolean expression,
f  xz  xz Maximum number of minterms = 2n
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Maximum number of implicants = 2n yz

wx 00 01 11 10
2n
Maximum number of prime implicants = 00 1 1
2
01 1 1 1
n 1
=2 11
10 1

05. Ans: (c)

Sol: 04. Combinational Circuits
AB
C 00 01 11 10
0 1 1 0 0 01. Ans: (d)
1 0 1 1 0 Sol: Let the output of first MUX is “F1”
F1 = AI0+AI1
F(A, B, C) = A C  BC
Where A is selection line, I0, I1 = MUX
Inputs
06. Ans: 1 F1  S1 .W  S1 .W  S1  W
Sol: After minimization = A  B  C  D   Output of second MUX is
= ABCD F  A.I 0  A.I1
 only one minterm.
F  S2 .F1  S 2 .F1
F  S 2  F1
07. Ans: 3
Sol: w z  w xy  x yz But F1  S1  W
F  S 2  S1  W
i.e., F  W  S1  S 2

02. Ans: 50
Sol: Y3 X3 Y2 X2 Y1 X1 Y0 X0

Z4 FA3 Z3 FA2 Z2 Z1
FA1 FA0 Z0

S3 S2 S1 S0

Initially all the output values are ‘0’, at t = 0, the inputs to the 4-bit adder are changed
to X3X2X1X0 = 1100, Y3Y2Y1Y0 = 0100
- - - - - - indicates critical path delay to get the output
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A0
0 X0 0  ‘0’ is updated as ‘1’ after 20ns
20 20 S0=01
0 Y0
[t=20 ns]

C0 0
B0 15
15 10  ‘0’ is updated again to ‘0’ (or)
Z1=0
0
[t=0 ns]
‘0’ is not changed, i.e.
Z1 is available @ t= 0 ns
Z0=1

0 X1 A1 0
20 20 S1=0
0 Y1
[t=0 ns]  ‘0’ is updated again to ‘0’ (or)
‘0’ is not changed

C1 0
B1 15
15 10 Z2=0  ‘0’ is updated again to ‘0’ (or)
C [t=0 ns] ‘0’ is not changed, i.e.
Z2 is available @ t= 0 ns
Z1=0

A2
1 X2 0
20 20 S2=0  ‘0’ is updated again to ‘0’ (or)
1 Y2
[t=0 ns] ‘0’ is not changed

C2
B2 15
15 10
1 Z3=01
[t=50ns,  ‘0’ is updated to ‘1’ after
t1=25ns] 25 ns
Z2=0

A3
1 X3 1
20 20 S3=0
0 Y3  ‘0’ is updated again to ‘0’ (or)
[t=0ns]
‘0’ is not changed
1
C3 1
B3 15  ‘0’ is updated as ‘1’ after 25ns
15 10 Z4=01
0 when Z3 is arrived
1 [t=50ns,
t2=25ns]

Z3=1
Total time taken = t1 + t2 = 50 ns
i.e. critical time (or) maximum time is taken for Z4 to get final output as ‘1’
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03. Ans: (a) 05. Sequential Circuits

Sol: The given circuit is binary parallel
adder/subtractor circuit. It performs A+B, 01. Ans: (c)
A–B but not A + 1 operations. Sol: Given Clk, X1, X2
Output of First D-FF is Q1
K C0 Operation
0 0 A+B (addition)
Output of Second D-FF is Q2
0 1 A+B+1(addition with carry) 1 2 3 4
1 0 A+ B (1’s complement addition)
1 1 clk
A+ B +1(2’s complement subtraction)

04. Ans: (d) X1

Sol: It is expansion of 2:4 decoders to 1:8
demultiplexer A1, A0 must be connected to X2
S1, S0 i.e.., R = S0, S = S1
Q must be connected to S2 i.e., Q = S2 Q1
P is serial input must be connected to Din
Q2

05. Ans: 6 Y=Q1Q2

Sol: T = 0 → NOR → MUX 1 → MUX 2
2ns 1.5ns 1.5ns
02. Ans: 4
Delay = 2ns + 1.5ns + 1.5ns = 5ns
Sol: In the given first loop of states, zero has
T = 1 → NOT → MUX 1→NOR→ MUX 2
repeated 3 times. So, minimum 4 number of
1ns 1.5ns 2ns 1.5ns
Flip-flops are needed.
Delay = 1ns + 1.5ns + 2ns + 1.5ns = 6ns
Hence, the maximum delay of the circuit is 03. Ans: 7
6ns Sol: The counter is cleared when
QDQCQBQA = 0110
06. Ans: –1
Sol: When all bits in ‘B’ register is ‘1’, then only Clk QD QC QB QA
it gives highest delay.
0 0 0 0 0
 ‘–1’ in 8 bit notation of 2’s complement 1 0 0 0 1
is 1111 1111 2 0 0 1 0
3 0 0 1 1

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4 0 1 0 0
Counter outputs Decoder inputs Decoder outputs
5 0 1 0 1 Q1 Q0 a b d3 d2 d1 d0
0 0 0 0 0 0 0 1
6 0 1 1 0
0 1 0 1 0 0 1 0
7 0 0 0 0 1 0 1 0 0 1 0 0
1 1 1 1 1 0 0 0

As the clear input is given to be The overall circuit acts as 4-bit ring counter
synchronous so it waits upto the next clock n=2
pulse to clear the counter & hence the  k = 22 = 4, k-bit ring counter
counter get’s cleared during the 7th clock
pulse. 06. Ans: (b)
 mod of counter = 7 Sol:
CLK Serial in= A B C D
BC D
04. Ans: (b) 0 1 0 1 0
Sol: The given circuit is a mod 4 ripple down 1 1 1 1 0 1
counter. Q1 is coming to 1 after the delay of 2 0 0 1 1 0
3 0 0 0 1 1
2t. 4 0 0 0 0 1
CLK Q1 Q0 5 1 1 0 0 0
0 0 6 0 0 1 0 0
7 1 1 0 1 0
1 1 1
2 1 0
3 0 1  After 7 clock pulses content of shift
4 0 0 register become 1010 again

05. Ans: (c) 07. Ans: (b)

Sol: Assume n = 2 Sol:
J K Q Qn T  J  Q n  Qn+1
Q1
2 4 1
0
K  Q  n

clk 2-bit 0 0 0 1 0.1 = 0 0

counter decoder2
0 0 1 0 1.0 = 0 1 Qn
3 0 1 0 1 0.1 = 0 0
Q0
0 1 1 0 1.1 = 1 0 0
1 0 0 1 1.1 = 1 1
Outputs of counter is connected to inputs of 1 0 1 0 1.0 = 0 1 1
decoder 1 1 0 1 1.1 = 1 1
1 1 1 0 1.1 = 1 0 Qn

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KQn 00 01 11 10 09. Ans: (b)

J
Sol:
0 1 Present Next State Output (Y)
State X=0 X=1 X=0 X=1
1 1 1 A A E 0 0
1
B C A 1 0
C B A 1 0
T = J Q n +KQn = (J+Qn) (K + Q n ) D A B 0 1
E A C 0 1
08. Ans: 1.5
Sol: Step (1):
Clk Q1 Q2 Q3 Q4 Q5 Y= Q3 + Q5 By replacing state B as state C then state
0 0 1 0 1 0 0 B, C are equal.
1 0 0 1 0 1 1
Reducing state table
2 1 0 0 1 0 0
3 0 1 0 0 1 1 Present state Next state
4 1 0 1 0 0 1 X=0 X=1
5 0 1 0 1 0 0 A A E
B B A
B B A
The waveform at OR gate output, Y is [A = D A B
+5V] E A B
A

0 T 2T 3T 4T 5T Step (2):
T1 = 5T
Reducing state table
Average power Present state Next state
V 2
1 1 T1  X=0 X=1
P
R
  TLt1 
Ao
R T1 
o
y 2 ( t ) dt 
 A A E
B B A
1  2T 2
A 2 dt 
5T


RT1  T
A dt  3 T 
D
E
A
A
B
B
A2
 (2T  T)  (5T  3T)
RT1
State D, E are equal, remove state E and
A 2 .3T 52.3
   1.5 mW replace E with D in next state.
R (5T) 10  5

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Reducing state table
06. AD and DA Converters
Present state Next state
X=0 X=1
A A D 01. Ans: (b)
B B A Sol:
D A B CLK Counter Decoder V0
D A B Q2 Q1 Q0 D3 D2 D1 D0
1 0 0 0 0 0 0 0 0
Finally reduced state table is 2 0 0 1 0 0 0 1 1
3 0 1 0 0 0 1 0 2
Reduced state table 4 0 1 1 0 0 1 1 3
5 1 0 0 1 0 0 0 8
Present state Next state 6 1 0 1 1 0 0 1
9
X=0 X=1 7 1 1 0 1 0 1 0
10
A A D 8 1 1 1 1 0 1 1 11
B B A
D A B 02. Ans: (b)
Sol:
R R R 2R
 3 states are present in the reduced state VR
table I/2 I/4 I/8 I/16
2R 2R 2R 2R
10. Ans: (c)
Sol: State table for the given state diagram

State Input Output

S0 0 1 Requ = (((((2R||2R)+R)||2R)+R)||2R)+R)||2R)
Requ = R = 10k  .
S0 1 0
VR 10V
S1 0 1 I= = = 1mA.
R 10k
S1 1 0 I
Current division at
Output is 1’s complement of input. 16
110 3
11. Ans: (c) = = 62.5  A
16
Sol: In state (C), when XYZ = 111, then
Ambiguity occurs 03. Ans: (c)
Because, from state (C) Sol: Net current at inverting terminal,
 When X = 1, Z = 1 I I 5I
Ii = + =
 N.S is (A) 4 16 16
When Y = 1, Z = 1  N.S is (B)
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5I 05. Ans: (b)

V0 = Ii R =   10k 
16 Sol: The magnitude of error between VDAC & Vin
 5 110 3 10 10 3 at steady state is VDAC  Vin = 6.5  6.2
= = 3.125V
16 = 0.3 V

04. Ans: (d) 06. Ans: (a)

3
Sol: In Dual slope
Sol: Given that VDAC = 2 n 1
b n Volts
n 0 ADC  Vin T1  VR .T2
1
VDAC = 2 b 0  2 b1  2 b 2  2 b 3
0 1 2
VR T2
 Vin 
 VDAC = 0.5b0 + b1 + 2b2 + 4b3 T1
Initially counter is in 0000 state 100 mV  370.2 ms

300 ms
Up VDAC(V) o/p of
counter o/p comparator DVM indicates  123.4
b3 b2 b1 b0
0 0 0 0 0 1 07. Ans: (d)
0 0 0 1 0.5 1 Sol: Ex: fin = 1 kHz  fs = 2 kHz
0 0 1 0 1 1
0 0 1 1 1.5 1 fin = 25 kHz  fs = 50 kHz
0 1 0 0 2 1 1. Max conversion time = 2N+1T = 211.1 s
0 1 0 1 2.5 1
= 2048 s
0 1 1 0 3 1
0 1 1 1 3.5 1 2. Sampling period = Ts  maximum
1 0 0 0 4 1 conversion time
1 0 0 1 4.5 1
Ts  2048 s
1 0 1 0 5 1
1 0 1 1 5.5 1 1 1
3. Sampling rate fs = 
1 1 0 0 6 1 Ts 2048 10 6
1 1 0 1 6.5 0
fs  488 fs  500 Hz
fs
When VDAC = 6.5 V, the o/p of comparator 4. fin =  250 Hz
2
is ‘0’. At this instant, the clock pulses to
the counter are stopped and the counter
08. Ans: (d)
remains in 1101 state.
Sol: In an ADC along with S-H circuit (sample
 The stable reading of the LED display
and hold) circuit, to avoid error at output,
is 13.
voltage across capacitor should not drop by
more than   / 2 , where  is step size.

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10  0
Here,   9.77510 3 V A2 0
(2  1)
10 1
A3 0
 1
Hence  4.887510 3 V
2 A4 0 0
So conversion time (maximum) should be 1 1 Chip select  0
A5
such that the drop across capacitor voltage
must reach maximum value  / 2 . A6 1 0
Hence, time taken for this 0
A7
/2 4.887510 3
t 
drop rate 10 4 V / m sec  Address space is 60H to 63H
t  49 m sec Ao to A11 are used for line selection
A12 to A15 are used for chip selection
07. Architecture, Pin Details of 8085
& Interfacing with 8085 A15 A14 A13 A12 A11 - - - - - A0
1 1 1 0 0-------0 =E000H
01. Ans: (a)
Sol: chip select is an active low signal for
chipselect  0 ; the inputs for NAND gate
must be let us see all possible cases for
1 1 1 0 1 - - - - - - - - 1 =EFFFH
chipselect  0 condition
A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 X X 02. Ans: (d)
0 0 1 1 0 0 X X Sol:  Both the chips have active high chip
0 1 0 1 0 0 X X
0 1 1 0 0 0 X X  60H (A1A0=00) select inputs.
1 0 0 1 0 0 X X  Chip 1 is selected when A8 = 1, A9 = 0
1 0 1 0 0 0 X X Chip 2 is selected when A8 = 0, A9 = 1
0 0 0 0 1 1 X X
 Chips are not selected for combination
0 0 1 1 1 1 X X
0 1 0 1 0 0 X X of 00 & 11 of A8 & A9
0 1 1 0 0 0 X X 63H(A1A0=11)  Upon observing A8 & A9 of given
1 0 0 1 0 0 X X address Ranges, F800 to F9FF is not
1 0 0 0 0 0 X X
represented
The only option that suits hare is option(a)
A0 & A1 are used for line selection 03. Ans: (d)
A2 to A7 are used for chip selection Sol: The I/O device is interfaced using “Memory
Mapped I/O” technique.

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The address of the Input device is 05. Ans: (d)

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Sol:

1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 =F8F8H A15 A14 A13 A12 A11 A10 A9 - - - - A0

0 0 0 0 1 0 0----0 =0800H
The Instruction for correct data transfer is
= LDA F8F8H
0 0 0 0 1 0 1----1 =0BFFH

0 0 0 1 1 0 0----0 =1800H
04. Ans: (b)
 Out put 2 of 38 Decoder is used for 0 0 0 1 1 0 1----1 =1BFFH
selecting the output port. Select code
0 0 1 0 1 0 0----0 =2800H
is 010
A15 A14 A13 A12 A11 A10 -- A0
0 0 1 0 1 0 1----1 =2BFFH
0 1 0 1 0 0 --- - 0
 5000H 0 0 1 1 1 0 0----0 =3800H
 This mapping is memory mapped I/O
0 0 1 1 1 0 1----1 =3BFFH

06. Ans: (a)

Sol: Address Range given is
cs

13 8 kB
ROM
A12  A0

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1000H  0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
2FFFH  0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1

To provide cs as low, The condition is

A15 = A14 = 0 and A13 A12 = 01 (or) (10)
i.e A15 = A14 = 0 and A13 A12 shouldn’t be 00, 11.
Thus it is A15 + A14 + [A13A12 + A13 , A12 ]

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 : 15 : Postal Coaching Solutions

07. Ans: (a) AC =1

Sol: ; (A) = 69H
A15
6016H : MOV H,A ; (H)(A) =69H
6017H : PCHL ; (PC)(HL) = 6979H

A13 02. Ans: (c)

A12 3:8 Sol: 0100H : LXI SP, 00FFH ; (SP) = 00FFH
A11 Decoder
0103H : LXI H, 0107 H ; (HL) = 0107H
0106H : MVI A, 20H ; (A) = 20H
0108H : SUB M ; (A)(A)-(0107)
; (0107) = 20H
A14
; (A) = 00H
A15, A14 are used for chip selection The contents of Accumulator is 00H
A13, A12, A11 are used for input of decoder
03. Ans: (c)
A15 A14 A13 A12 A11 A10 ------ Sol: SUB1 : MVI A, 00H A← 00H
A0 CALL SUB2  program will shifted to
Enable Input of Address of SUB 2 address location
of decoder chip A
SUB 2 : INR A 
decoder
01H
11
Size of each memory block = 2 = 2K
RET  returned to the main program
08. Instruction set of 8085 &  The contents of Accumulator after
Programming with 8085 execution of the above SUB2 is 02H

01. Ans: (c) 04. Ans: (c)

Sol: Sol: The loop will be executed until the value in
6010H : LXI H,8A79H ; (HL) = 8A79H register equals to zero, then,
6013H : MOV A, L ; (A)(L) = 79 Execution time
6014H : ADD H ; (A) = 0111 1001 =9(7T+4T+4T+10T)+( 7T+4T+4T+7T)+7T
+
; (H) = 1000 1010 = 254T
; (A) = 0000 0011
CY = 1, AC = 1 05. Ans: (d)
6015H : DAA ; 66 Added to (A) Sol: H=255 : L = 255, 254, 253, ----0
since CY=1 &
H=254 : L = 0, 255, 254, -------0
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: 16 : Digital & Microprocessors
|
07. Ans: (d)
H=1 : L = 0,255,254,253,---0
Sol: The operation SBI BEH indicates
H=0 : A-BE  A where A indicates accumulator
 In first iteration (with H=255), the value in Thus the result of the subtraction operation
L is decremented from 255 to 0 i.e., 255 is stored in the accumulator and the contents
times of accumulator are changed.
 In further remaining 254 iterations, the
value in L is decremented from 0 to 0 i.e., 08. Ans: (c)
256 times Sol: If the content in register B is to be
 ’DCRL’ instruction gets executed for multiplied with the content in register C, the
 [255  (254  256)] contents of register B is added to the
accumulator (initial value of accumulator
 65279 times
is 0) for C times.

06. Ans: (a)

Sol: “STA 1234H” is a 3-Byte Instruction and it
requires 4 Machine cycles (Opcode fetch,
Operand1 Read, Operand2 Read, Memory
write). The Higher order Address (A15 – A8)
sent in 4 machine cycles is as follows
Given “STA 1234” is stored at 1FFEH
i.e., Address Instruction

1FFE, 1FFF, 2000 : STA 1234H

Machine Address Higher order

cycle (A15-A0) address
(A15-A8)
1. Opcode 1FFEH 1FH
fetch
2. Operand1 1FFFH 1FH
Read
3. Operand2 2000H 20H
Read
4. Memory 1234H 12H
Write
i.e. Higher order Address sent on A15-A8 for
4 Machine Cycles are 1FH, 1FH, 20H, 12H.

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