CPU

Condition Code Register (CCR)

This register contains five status indicators, two interrupt masking bits, and a STOP
disable bit. The register is named for the five status bits since that is the major use of the
register. The five status flags reflect the results of arithmetic and other operations of the
CPU as it performs instructions. The five flags are half carry (H), negative (N), zero (Z),
overflow (V), and carry/borrow (C). The half-carry flag, which is used only for BCD
arithmetic operations, is only affected by the add accumulators A and B (ABA), ADD,
and add with carry (ADC) addition instructions (21 opcodes total). The N, Z, V, and C
status bits allow for branching based on the results of a previous operation. Simple
branches are included for either state of any of these four bits. Both signed and
unsigned versions of branches are provided for the conditions <, , =, , , or >.
The H bit indicates a carry from bit 3 during an addition operation. This status indicator
allows the CPU to adjust the result of an 8-bit BCD addition so it is in correct BCD
format, even though the add was a binary operation. This H bit, which is only updated by
the ABA, ADD, and ADC instructions, is used by the DAA instruction to compensate the
result in accumulator A to correct BCD format. The N bit reflects the state of the most
significant bit (MSB) of a result. For two’s complement, a number is negative when the
MSB is set and positive when the MSB is zero.
The N bit has uses other than in two’s-complement operations. By assigning an often
tested flag bit to the MSB of a register or memory location, the user can test this bit by
loading an accumulator. The Z bit is set when all bits of the result are zeros. Compare
instructions do an internal implied subtraction, and the condition codes, including Z,
reflect the results of that subtraction. A few operations (INX, DEX, INY, and DEY) affect
the Z bit and no other condition flags. For these operations, the user can only determine
= and . The V bit is used to indicate if a two’s-complement overflow has occurred as a
result of the operation. The C bit is normally used to indicate if a carry from an addition
or a borrow has occurred as a result of a subtraction. The C bit also acts as an error flag
for multiply and divide operations. Shift and rotate instructions operate with and through
the carry bit to facilitate multiple-word shift operations.
The STOP disable (S) bit is used to allow or disallow the STOP instruction. Some users
consider the STOP instruction dangerous because it causes the oscillator to stop;
however, the user can set the S bit in the CCR to disallow the STOP instruction. If the
STOP instruction is encountered by the CPU while the S bit is set, it will be treated like a
no-operation (NOP) instruction, and processing continues to the next instruction.
The interrupt request (IRQ) mask (I bit) is a global mask that disables all maskable
interrupt sources. While the I bit is set, interrupts can become pending and are
remembered, but CPU operation continues uninterrupted until the I bit is cleared. After
any reset, the I bit is set by default and can only be cleared by a software instruction.
When any interrupt occurs, the I bit is automatically set after the registers are stacked
but before the interrupt vector is fetched. After the interrupt has been serviced, an RTI
instruction is normally executed, restoring the registers to the values that were present
before the interrupt occurred. Normally, the I bit would be zero after an RTI was
executed.
The XIRQ mask (X bit) is used to disable interrupts from the XIRQ pin. After any reset, X
is set by default and can only be cleared by a software instruction. When XIRQ is
recognized, the X bit (and I bit) are automatically set after the registers are stacked but
before the interrupt vector is fetched. After the interrupt has been serviced, an RTI
instruction is normally executed, causing the registers to be restored to the values that
were present before the interrupt occurred. It is logical to assume the X bit was clear
before the interrupt; thus, the X bit would be zero after the RTI was executed. Although
XIRQ can be re-enabled within an interrupt service routine, to do so is unusual because
nesting of interrupts becomes possible, which requires much more programming care
than single-level interrupts.

EEPROM
This 512-byte EEPROM memory can be used in the same ways ROM would be used,
but some interesting possibilities arise that are not possible with ROM or RAM
memories. Once information is programmed into the on-chip EEPROM, it remains
unchanged even if V DD power is removed indefinitely. Unlike information in ROM,
information in EEPROM can be erased or reprogrammed under software control.

Basic Operation of the EEPROM

The following paragraphs briefly describe how the EEPROM operates. Figure 1, a
condensed schematic of the EEPROM array, provides insight into the operation of the
EEPROM system and illustrates the complexity of a byte-erasable EEPROM. Each byte
in the EEPROM array consists of 17 transistors, eight floating-gate transistors, a select
transistor for each floating-gate transistor, and a byte-select transistor. The floating-gate
transistor is the storage element in the EEPROM cell. Since the floating gate is isolated
by thin oxide layers, any charge on this gate remains indefinitely unless a large enough
field is created, as in programming and erase modes. When a large enough field is
present, Fowler-Nordheim electron tunneling allows charge to be transferred to or from
the floating gate, depending on the polarity of the field. In the following discussion, V DD
is nominally 5 V and V PP is about 20 V..

Figure 1 Condensed Schematic of EEPROM Array

 Figure 2 EEPROM Cell Terminology

Figure 3 Erasing an EEPROM Byte

In erase mode (see Figure 3), the array ground is connected to V SS. The row and
column selects cause the control gates of the byte(s) being erased to be connected to
VPP . Other bytes in the array that are not being erased would have their control gates
connected to an undriven logic zero. The bit-select devices are all turned on by V PP on
the word lines; however, the drains of the bit-select devices are high impedance.
Thus, the drains of the floating-gate transistors are effectively floating. The high voltage
on the control gate of the floating-gate transistor is capacitively coupled onto the floating
gate. The large field between the floating gate and the substrate results in electron
tunneling from the substrate to the floating gate. After erasure, the floating gate has a
negative charge, which keeps the floating-gate transistor turned off during reads. If
leakage in the floating-gate transistor caused the negative charge to leak off so that
there was no charge on the floating gate, the bit would still read back as one. This fact
implies that long-term retention errors cannot cause a logic-one bit to deteriorate.

Figure 4 shows an EEPROM byte being programmed to the value $55 (0101 0101) to
demonstrate the effect of programming both ones and zeros. Since the erased state of
an EEPROM bit is one, programming a one is the same as doing nothing. During
programming, the array ground is not driven. The control gates of the byte to be
programmed are driven to zero through the row-select and column-select path. Control
gates for bytes not being programmed will be high impedance because the column-
select and/or row-select device will be off. The bit-select devices are turned on hard
because the row select, for the row containing the byte being programmed, is driven to
VPP. The bit lines are driven to V DD for bits not being programmed (ones) and to V PP for
bits being programmed (zeros). For bits not being programmed (ones), the drain of the
floating-gate transistor is at V DD, and the control gate is at V SS. This configuration does
not result in a large enough field for tunneling to occur; thus, no charge transfer occurs.

Figure 4 Programming an EEPROM Byte

For bits being programmed (zeros), the drains of the floating-gate transistors are at V PP–
TN (because of the drain-to-source threshold voltage drop across the bit-select device),
and the control gate is at V SS. This configuration results in a large enough field so
electrons can tunnel from the floating gate to the drain region of the floating-gate
transistor. Since the floating gate of a programmed bit has a positive charge, the
floating-gate transistor will conduct during reads.
Figure 5 shows an EEPROM byte being read. During a read operation, the bit lines are
precharged to one. Column selects enable the bit lines from the byte being read to the
sense amp inputs. The row select for the row containing the byte being read is driven to
VDD to enable the bit-select devices. The array ground is connected to V SS.
The floating gate devices of programmed bits conduct and pull the corresponding bit
lines to zero. The floating-gate devices of bits not programmed do not conduct;
therefore, the corresponding bit lines remain at the precharged level and read as ones.
EEPROM operations are actually much more complicated than this discussion suggests,
but the following general statements may be useful to designers using the EEPROM.
1) Since no high voltages are present during read operations, no degradation of data
can result from repeated read operations. 2) Erase operations normally take less time
than programming operations. 3) The most common EEPROM failure (write ones) is an
unintended bit change from one to zero during programming of $FF data. This failure
occurs during endurance testing as the part approaches wear-out (typically after tens of
thousands of write-erase cycles). 4) Retention failures result in programmed zeros
reverting to ones due to leakage of the floating-gate charge. 5) Ones never revert to
zeros without an explicit programming operation (though the programming operation
need not involve any zeros in the pattern being programmed).

Figure 5 Reading an EEPROM Byte

EEPROM programming and erasure involve the movement of charge through a thin
oxide layer. This charge movement requires a relatively large field to be present for a
significant length of time (milliseconds). Noise is not likely to cause individual bits to
change state. Most failures of the EEPROM involve breakdowns due to the relatively
high voltages or to an oxide degradation phenomenon (trapped charge). After many
cycles of programming and erasure, charge may become trapped in the thin oxide
layers isolating the floating gate. This trapped charge causes programming and erase
operations to take longer as the amount of trapped charge increases. When the cell fails
to program to zero in the allotted time, it is worn out. In many cases, these bits can still
be programmed and erased provided the program and erase times are increased. The
useful life of an EEPROM byte cannot be extended very far by extending the
programming time because a worn bit exhibits a reduced ability to retain valid zeros for
very long time periods.