Integration, the VLSI Journal xxx (xxxx) xxx

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Integration, the VLSI Journal

journal homepage: www.elsevier.com/locate/vlsi

A survey on fault injection methods of digital integrated circuits

Mohammad Eslami a, *, Behnam Ghavami a, Mohsen Raji b, Ali Mahani a
a
Department of Engineering, Shahid Bahonar University of Kerman, Kerman, 7345199665, Iran
b
School of Electrical and Computer Engineering, Shiraz University, Shiraz, 71348-51154, Iran

A R T I C L E I N F O A B S T R A C T

IndexTerms: One of the most popular methods for reliability assessment of digital circuits is Fault Injection (FI) in which the
Reliability assessment behavior of the circuit is simulated in presence of faults. In this paper, we present a survey of FI techniques as well
Fault simulation as classifying these techniques considering different aspects and criteria to bring out their similarities and dif-
Fault injection
ferences. The goal of this paper is to help the researchers and reliable circuit designers in gaining insights into the
Digital circuits
state-of-art in FI techniques and motivate them to further improve these techniques for more efficient reliability
evaluation of digital circuit designs of tomorrow.

1. Introduction Then, by using the appropriate analytical approaches, required parame-

Fault has become an inevitable member in electronics world. Pres-
ence of faults is usually originated from a particle strike to a chip surface
or environment radiation such as cosmic rays [1]. The probability of fault
occurrence depends on many factors such as the environmental condi-
tions, meters above sea level, and amount of the radiation in the opera-
tional location [2]. So, establishing proper conditions for fault generation
is a real threat for reliable and safe operation of an electronic component
[3–5]. Hence, to ensure the correct operation of an electronic component,
fault tolerant techniques should be exploited.
Several methods have been developed to increase the reliability of the
electronic components against probable faults. These methods have
different complexities, different amounts of time needed for imple-
mentation, and a wide range of costs depending on their applications
(real time, critical, and normal applications) [6–8].
Before using techniques for recovering the circuit from the faulty
condition, it is necessary to detect the sensitive areas of the design;
generally speaking, if a fault appears in a sensitive area, it has a higher
chance to be transformed to an error and affects the normal operation of
the circuit. So, by identifying the sensitive areas and exploiting appro-
priate fault tolerant techniques, unnecessary overheads such as compu-
tational overheads and costs will be avoided during increasing the
reliability of the circuits.
One of the most common approaches to identify the sensitive areas
and measuring the reliability of the circuits is the fault injection tech-
nique [9–15]. In this technique, faulty condition is simulated for the
circuit by injecting a fault into the circuit and tracking its impacts in it.
ters such as the circuit failure rate and the other parameters related to the
tolerance of the circuit against faults are calculated. The fault injection
techniques can be categorized into three main groups:
i) hardware-based (physical) fault injection approaches
ii) simulation-based software fault injection approaches
iii) emulation-based fault injection approaches
In hardware-based fault injection approaches, a hardware framework
is needed to simulate the faulty condition of the design. Comparing with
the software-based approaches, these approaches are better in speed but
have more complexities in implementation and impose significant costs
to the designers. In contrast, software-based approaches are less expen-
sive, simpler to implement and do not need any extra hardware, but have
significant computational overheads [16]. Emulation-based approaches
generally use Field Programmable Gate Arrays (FPGAs) for fault injection
that help them to take advantages of the acceleration provided by FPGA
during the fault injection process.
In this paper, we study and compare the features of different fault
injection approaches in digital circuits (Fig. 1). The rest of the article is
organized as follows: In section II, we study the fundamental concepts
about fault, error, and failure. After that, in section III the software-based
fault injection techniques are investigated. Section IV studies the fault
injection approaches based on FPGA or the emulation-based fault injec-
tion approaches. In section V, the hardware-based fault injection ap-
proaches are explored. Section VI provides a discussion and finally,
section VII concludes the paper.

* Corresponding author.
E-mail addresses: eslami@eng.uk.ac.ir (M. Eslami), ghavami@uk.ac.ir (B. Ghavami), mraji@shirazu.ac.ir (M. Raji), amahani@uk.ac.ir (A. Mahani).

https://doi.org/10.1016/j.vlsi.2019.11.006
Received 29 July 2019; Received in revised form 11 October 2019; Accepted 11 November 2019
Available online xxxx
0167-9260/© 2019 Elsevier B.V. All rights reserved.

Please cite this article as: M. Eslami et al., A survey on fault injection methods of digital integrated circuits, Integration, the VLSI Journal, https://
doi.org/10.1016/j.vlsi.2019.11.006
M. Eslami et al. Integration, the VLSI Journal xxx (xxxx) xxx

Fig. 1. Different approaches for fault injection in digital circuits.

2. Fault, error and failure in hardware
Generally, the main threat for a system reliability is the fault-error-
failure chain. Fault may be generated from a particle strike to the chip
surface or an electric migration between the transistor interconnections.
The first case is an example of a transient fault and the second one is an
example of a permanent fault in the system. Permanent faults are those
that remain in the system until a recovering action is done in order to
replace the faulty component. In comparison, transient faults are those
which temporarily affects the system and their effect may lead to an error
or may be dissolved in by the system. A transient fault cannot be a
directly disrupt the normal operation of a system, but if it is converted to
an error, this generated error may lead to system failure in some specific
conditions. When a particle strikes to the chip surface, a transient voltage
pulse called Single Event Transient (SET) may be generated at the output
of the struck gate [9]. SET may be propagated through the logic gate until
it reaches to one of the latching components of the circuit and be stored in
it. In this condition, the produced error is called soft error. There are some
barriers through the path from the fault location to the latching com-
ponents of the circuit that may prevent the fault to become an error.
These factors are known as triple masking effects which includes electrical,
timing, and logical masking effect [10]. In the following, more details are
provided about these three masking effects.
voltage level of the generated SET will be decreased more. During
propagation in the circuit, the voltage level of the SET may be so
decreased that the SET is not recognized in the input of the next gate or
the latching element of the circuit as a valid voltage pulse. In this case,
the SET is dissolved in the circuit because of the electrical masking effect.
2.2. Timing masking effect
If a SET reaches to a latching element of the circuit without being
dissolved due to electrical masking effect, we cannot still be sure that the
SET will be stored in the latching element. In order to be stored in the
latching element, the SET should reach at the input of the element at the
clock edges considering the setup time and the hold time constraints of
the latching element [1] (Fig. 3). Hence, if a SET reaches to the input of a
latching component of the circuit outside its latching time frame, it will
not be stored and it is dissolved in the circuit due to the timing masking
effect.

2.1. Electrical masking effect

When a SET occurs in the circuit, it has a specific level of voltage.

During propagation in the circuit and by passing through the several
gates of the circuit, the voltage level of SET rapidly decreases because of
the electrical attenuation [16] (Fig. 2). As the path between the fault
location and the latching element of the circuit becomes longer, the

Fig. 2. A SET dissolved in the circuit due to electrical masking effect. Fig. 3. A SET dissolved in the circuit due to the timing masking effect.

2
M. Eslami et al.
2.3. Logical masking effect
It is possible for a SET to be dissolved in the circuit due to the logical
value of the inputs of the gates which are propagating the SET. As shown
in Fig. 4, the generated SET in the output of gate G1 has no effect on the
output value of gate G4 because it's another input (and thus, its output) is
zero without considering the SET value. In this condition, the SET dis-
solves in the circuit because of the logical masking effect.
If the SET is not dissolved due to the mentioned triple masking effects,
it will be stored as a soft error or Single Event Upset (SEU) in the circuit
[13]. As one of the most common error occurring in the digital circuits is
the soft error, a great part of researches has been done to evaluate the
tolerance of designs against soft errors including different approaches of
fault injection.
3. Simulation-based software fault injection
Simulation-based software fault injection approaches have been used
widely because of their simplicity and versatility. Although most of the
software-based fault injection approaches are not the expensive ones, but
they take a lot of time to complete the simulation process. Hence, re-
searchers have been trying to accelerate the software-based approaches
by applying different techniques.
One of the most important parameters in evaluating the reliability of
the circuit is the Soft Error Rate (SER) [17–44]. As there is no limitation
for considering the triple masking effects in software-based fault injec-
tion approaches, the SER of the circuit can be computed with high ac-
curacy. Although in other two fault injection techniques
(hardware-based and emulation-based) it is tried to consider the triple
masking effects during soft error generation in the circuit, but
software-based approaches are still the best in the aspect of accuracy.
The software-based fault injection approaches are divided into two
main categories:
1) dynamic approaches
2) static approaches
In dynamic approaches [17–28], first one (or more than one) fault(s)
is inserted (injected) into the circuit and then, the circuit is simulated
with different input vectors to compute the number of faults that are
latched and converted to the error. Of course, in some of dynamic ap-
proaches, element pre-characterizations are used for simulating the cir-
cuit. On the other hand, in static approaches that are also considered as
the approximate approaches, two group of symbolic and analytical
methods are used. In the symbolic approaches, specific data structures
such as matrices or graphs are used to keep the information about the
Fig. 4. A SET dissolved in the circuit due to the logical masking effect.
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Integration, the VLSI Journal xxx (xxxx) xxx
triple masking effects. The analytical approaches take advantages of the
mathematical formulations such as Boolean satisfaction or probability
rules to evaluate the impacts of triple masking effects. In the following,
we briefly describe the approaches of each category.
3.1. Dynamic approaches
There are several software-based approaches presented in the dy-
namic category. In Ref. [17], the proposed fault injection method uses
two type of element pre-characterizations called logical
pre-characterization and flip-flop pre-characterization. In the logical
pre-characterization, different current pulses are injected in the output of
different gates for generating different pulse widths of SETs and then, the
voltage-current characteristics are extracted from the standard library for
the gates and they are stored in a table called the voltage-current char-
acteristics table. In the flip-flop pre-characterization, the voltage pulses
with different pulse widths are injected into the inputs of the flip-flops.
Then, a counter is used to store number of the times that the transient
pulse is latched. In the next step, this information is stored in a table
known as the timing table. To compute the logical masking rate of the
gates, logical simulation is performed for different input vectors. A
similar approach is presented in Ref. [18]. In this approach, first the
pre-characterization of the logical gates is computed and then, the error
rate of each logical gate is computed for each input vector by circuit
simulations and they are stored in a specific table. To compute the error
rate of available paths from each gate to the circuit flip-flops, logical
simulation for different inputs of the circuit is performed. In this condi-
tion, the SER is computed only for a group of paths. So, the SER in other
paths are approximated using the available SER of the closest path.
Another approach based on the pre-characterization is represented in
Ref. [19]. This approach uses HSPICE tool for simulating the circuit in
order to extract the probability distribution of the transient pulse widths
for different situation of particle striking to each gate. For this purpose, a
large number of the samples from the paths that include different logical
gates are generated and then, for each generated path, different pulses
are injected and propagated through it. By using the information of the
propagated transient pulses, several tables are created for keeping the
information about the electrical, timing, and logical masking parameters.
Finally, for each injected pulse, the error rate is obtained for each gate by
referring to this table in each fault location.
Another framework based on pre-characterization approach called
“SEAT-LA” is presented in Ref. [20]. SEAT-LA supports the designs which
are based on cell libraries. These libraries are characterized based on the
soft error rate. Also, this framework takes advantages of the analytical
equations for modelling the electrical pulse propagation to the input of a
flip-flop.
Another approach named “SERA” is presented in Ref. [21]. In this
approach, the logical masking ratio of each fault location is computed
using the graph theory and the fault simulation. Then, by making
equivalent paths with an inverter chain and performing the circuit level
simulations using the SPICE tool, the electrical and timing masking ratios
are obtained. In Ref. [22], an approach for computing the electrical,
timing, and logical masking probability is presented using the random
input vectors, but it is so time consuming for the large circuits.
An approach presented in Ref. [23] aims to avoid the unnecessary
details of injected faults to achieve a better speed-up during the simu-
lation process. For this purpose, the authors categorize the faults sets into
three subsets and for each subset, they choose the fastest abstraction level
to inject faults (i.e. transfer level, instruction-set level, and host-compiled
level). Furthermore, it is possible to switch between the abstraction levels
during the fault injection campaign for better acceleration. A similar
approach presented in Ref. [24] tries to achieve a better speed-up by
ignoring unused register files in order to limit the fault space. In this
approach first a golden run is performed in the target circuit to obtain the
fault-free values from the outputs. Then, faults are injected in a parallel
fashion. This makes the fault injection process to be performed much
M. Eslami et al.
faster specially in manycore systems. Finally, the results are compared
with the golden ones to assess the reliability of the system.
In Ref. [25], fault injection is performed on the LEON3 micropro-
cessor model using a novel iterative algorithm. In this approach, the
number of the experiments are defined dynamically based on estimation
of the experiments leading to failure. So, fault injection can be stopped by
the user anytime in order to estimate the error rate of the circuit.
Although this approach supports only one fault model (single bit-flip),
but it has an acceptable accuracy among the similar approaches.
An approach based on the parameterized descriptor is presented in
Ref. [26]. In this approach, transient pulses are defined using a Weibull
distribution. To estimate the SER, the transient pulse descriptor is
injected into each node of the circuit and then, the descriptor is propa-
gated through the paths in the design. SER estimation approaches based
on the signature [27,28] are also categorized in this group. In these
works, signature is defined as the bit pattern generated in the node of the
circuit by applying different input vectors to the primary inputs of the
circuit. To extract the signature, it is needed to simulate the circuit using
the random inputs.
3.2. Static approaches
As mentioned before, symbolic approaches (based on the specific data
structures such as matrix or the binary decision tree) and the analytical
approaches (based on the algebra or probabilistic theories) are used in
static approaches. These approaches are categorized as follows:
3.2.1. Symbolic approaches
In this group, specific data structures are used to maintain the in-
formation about logical and electrical masking effects. In Ref. [29], an
approach is presented in which the circuit under study and the transient
pulses are both defined as a matrix. Then, the effect of the transient pulse
on the circuit is investigated using some presented operators on these
matrices. For this purpose, all responses of the gates to the different
pulses are pre-characterized and stored in a matrix.
In some other approaches of this group, a fault is defined as a sym-
bolic function of the logical gate inputs. In order to study the logical
masking effect, the transient pulse is modelled by a Binary Decision Di-
agram (BDD). For modelling a function using the BDD, the outputs of the
function for different values of the inputs are kept in the terminal nodes
in forms of the available values. So, in order to obtain the value of the
function for a specific input vector, it is needed to start from the root node
and select each branch based on the input vector to reach to a terminal
node. For modelling the triple masking effects in the BDD, the transient
pulse information is kept in the related data structures in a way that each
terminal node, not only contains the output value of the logical function,
but also have the information about the transient pulse related to this
output value. To propagate the fault, the BDD is constructed from the
fault location to the Primary Output (PO) of the circuit for each fault and
finally, the SER is estimated.
In Ref. [30], an approach is presented to analyze the susceptibility of a
combinational circuit to soft errors based on the BDD and the circuit
partitioning. In this approach, transient pulses are coded by a BDD and
propagated at the gate level. Another similar approach based on BDD is
presented in Ref. [31]. In this approach, the BDD is used to keep the
information of the critical paths and the soft error parameters.
To compute all three masking factors uniformly and consider the ef-
fects of the re-convergent paths in the fault injection process and the SER
estimation, an approach is presented in Ref. [32] that uses the BDD and
the Algebra Decision Diagram (ADD) simultaneously. In this approach,
the gates that have the largest impacts on the reliability of the circuit are
chosen in order to be resized. Then, the SER of the circuit is computed
and it shows better results after resizing the gates. A public infrastructure
based on the probability transmission matrices is presented in Ref. [33].
The ADD is used to build the probability transmission matrices in this
approach.
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Integration, the VLSI Journal xxx (xxxx) xxx
3.2.2. Analytical approaches
In this group of approaches, the probabilistic and the mathematical
rules (i.e. the Boolean algebra) are used. So, these approaches can be
divided into two categories: 1) approaches based on the Boolean satis-
faction and 2) the probability propagation approaches.
In the approaches based on the Boolean satisfaction, first the SER
estimation problem is changed to an equivalent Boolean satisfaction
problem and then, by using the Boolean satisfaction solving tools, the
SER is obtained. An approach presented in Refs. [33,34] uses the Boolean
satisfaction. In this approach, the gate level description of the circuit is
traversed and the probability of an error in the output of each gate is
computed using the Boolean satisfaction rules.
Another group of the analytical approaches are based on probability
propagation. In these approaches, the probability of the fault occurrence
is propagated in the critical paths using the signal probabilities, instead of
propagating the fault itself.
An analytical approach for SER estimation considering the logical
masking effect is presented in Refs. [35,36] using the probability prop-
agation concepts. To consider the effect of the re-convergent paths, this
work is developed in Ref. [37] using the correlation coefficients of the
different gates of the circuit. However, in this approach, the electrical
and timing masking effects are not considered.
In Ref. [38], the model presented in Ref. [35] is developed consid-
ering the electrical and timing masking effects. For this purpose, the
electrical masking model presented in Ref. [20] and the timing masking
model presented in Ref. [39] are used. This procedure has been devel-
oped by presenting a model for considering the re-convergent paths in
Ref. [40]. In Ref. [41], an approach based on the signal probability
propagation using a new data structure. In this approach, the probability
of a signal to have a correct or incorrect value is shown by a 2  2 matrix.
The probability of the output of each gate is defined regarding to matrix
that includes the input probabilities and the transmission matrix of that
gate. The transmission matrix shows the probability of the correct/in-
correct operation of the gate and depends on the reliability of each logical
gate. Propagation of the input signal probabilities of a logical gate is done
by multiplying the matrices that include the input probabilities and the
transmission matrix of that gate. This continues until reaching to the POs
of the circuit and finally, the probabilities of correct and incorrect out-
puts are obtained.
The presented approach in Ref. [42] tries to make a tradeoff between
the accuracy of the estimation and the amount of information needed for
SER estimation. For this purpose, first it suggests a model for estimating
the SER of a gate without considering any of the triple masking effects.
This model is presented in Ref. [43] and it is obtained by performing
some experimental measurements and simulations. Then, the triple
masking effects are considered in this model incrementally. For the
electrical masking, a simple assumption is considered in which, the
amount of the critical load that generates after the strike is considered to
be so high that the generated pulse will pass through the circuit paths,
without being attenuated and the electrical masking has no effect on the
transient pulse. For the timing masking, the model presented in Ref. [44]
is used. To compute the SER of a gate considering the timing masking
effect, first the SER is computed for each of the possible values of the
critical load without considering this masking effect. Then, this value is
multiplied by the probability of latching the pulse generated from this
load and finally, all values are added together.
4. Hardware-based fault injection approaches
Hardware-based fault injection techniques also known as physical
fault injection approaches, are the fastest but the most expensive ap-
proaches among all fault injection methods [45–52].
Physical fault injection is performed either by contact-based ap-
proaches in which the external interface of the integrated circuit is per-
turbed (i.e. pin-level active probes and socket insertion), or without
contact approaches in which some parts of the design are bombarded
M. Eslami et al.
with the external energy resources (i.e. beams of laser, heavy ions, pro-
tons, and neutrons) to simulate the real faulty environment for the digital
components.
In both of the mentioned groups, an external hardware environment
is needed to implement these approaches. Hence, they are extremely
expensive and the labs that are capable of physical fault injection are
limited to a few countries in the world. Moreover, beside the risk of
damaging the design under the test, a fabricated piece of the hardware
should exist for the fault injection experiments leading to a real challenge
in the time-to-market for the designers and the manufacturers. Further-
more, in these approaches, it is not possible to inject faults in all desired
locations of the component leading to wrong or inaccurate results during
the experiments. However, these approaches are very fast and if the ex-
periments are done in the correct manner, the obtained results will be
very close to the real environment.
In contact-based fault injection approaches, the fault injection process
is usually performed using a pin-level tool in which faults are injected
through the probes connected to the pins of the IC (i.e. processor chips).
Example of a pin-level fault injection is introduced in Ref. [45]. In this
approach, the reputation of faults is completely controlled by user and it
can be continuously performed if needed. The architecture of this tool
contains a trace memory collecting the data on the processor bus after
injecting the faults to the target processor using the insertion technique.
So, it does not need any feedback circuit and this makes the overheads
more acceptable.
Another contact-based fault injection tool [46] uses both active
probes and socket insertion to inject faults to the target circuit. In this
approach, multiple faults can be injected to the circuit as well as the
single ones and many fault models (stuck-at, open, bridging) are sup-
ported to make the results more realistic. It also enables the user to
control the frequency and the duration of the faults.
While the available contact-based approaches are acceptable due to
their realistic environment, but they have been used rarely in recent
years due to the increase in operating clock frequency and density of
newer generation of the ICs.
On the other hand, in the physical fault injection approaches without
contact there is a device that generates the beams that may corrupt the
normal operation of the circuit for simulating the particle striking to
some parts of that. These beams are generally consisted of laser, heavy
ions, protons, and neutrons. Also, the intensity of the generated beams is
adjustable in order to reduce the power of the beams, since by performing
a high-powered beam radiation to the sensitive parts of the circuit, the
component may be destroyed [50,51].
A physical fault injection framework is presented in Ref. [51] that
uses the proton beams radiation with the intensity between 6 MeV and
37 MeV. In this approach, regarding to the proton flux in real operation
environments, the range of radiation is between 104 particles/cm2/s to
1014 particles/cm2/s. For the radiation of the proton beams to the sen-
sitive parts of the circuit, the lower proton flux should be used to avoid
damaging the component. However, if the beam flux is lower than 107
particles/cm2/s, the accurate measurement of the fault tolerance of the
circuit against the radiated beams will not be possible since the amount
of beam fluxes radiated to the circuit cannot be accurately measured.
Hence, an ionized environment as presented in Ref. [52] is used to
overcome the mentioned problem. Furthermore, in Ref. [52], some
control structures are designed to move the beam radiation device in
order to inject faults into the different parts of the circuit.
In Ref. [53], a novel laser fault injection approach is presented that
attacks thorough the sides of the IC in order to come over the problems
with laser fault injection of newer packaging technologies. These prob-
lems include newer packaging techniques that limits the efficiency of
traditional laser fault injection approaches because of absorption of laser
beams by the surface of the IC. Although this approach is more energy
consuming than the traditional ones, but it is still valuable since it con-
siders the side attacks as a potential threat for ICs in real environments.
For implementing the physical fault injection frameworks, the laser
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Integration, the VLSI Journal xxx (xxxx) xxx
Fig. 5. Physical fault injection using a) high intensity and b) low intensity
laser beam.
beam is usually preferred to the heavy ion beams. The main reason is
that, with technology improving, transistor dimension has decreased
such that transistor sizes will be less than the diameter of radiation
beams. This makes a group of components in the circuit to be uninten-
tionally exposed to radiation of the beams when radiating other com-
ponents in the circuits. In Ref. [50], an approach is presented for physical
fault injection to overcome the problem of the laser beams size. In this
approach, a group of the gates are bombarded with the laser beam
instead of one gate. Hence, different chains of the transistors are bom-
barded using laser beams with different intensities. It is obvious that,
with increasing the intensity of the laser beam, the size of the laser beam
will be larger [50]. The intensity of the laser beam is not the same in
different parts of it; i.e. the highest intensity is related to the center of the
beam [50]. By putting the circuit in front of the laser beam with different
ranges of intensity (Fig. 5), the operation of the circuit is affected by the
injected fault(s) and the output signal value may be changed considering
to the radiated beam intensity.
5. Emulation-based fault injection approaches
Fault emulation techniques try to benefit from the speed of the
hardware-based approaches and the accuracy of the software-based ap-
proaches. Hence, their implementation phases usually consist of the both
software and hardware phases. Emulation-based fault injection ap-
proaches do not need any special facility used in physical fault injection
approaches making them more cost effective. Another advantage of
emulation-based fault injection approach is that, there is no limitation in
choosing the fault locations. Also, in these approaches, there is no need to
have a physical version of the component for injecting faults and reli-
ability assessments. Hence, it is possible to validate the circuit in the
initial steps of the design [54–61].
5.1. Motivations of using the emulation-based fault injection approaches
In some large-scale circuits, the time needed for software simulations
of the circuit takes years to be completed making the simulation process
impossible. On the other hand, limitations and expensive costs in the
physical approaches makes them to be unreachable for most of the re-
searchers. To overcome these challenges, a solution is needed to imple-
ment a fast and cost-efficient framework for fault injection. One of the
most popular techniques in emulation-based fault injection approach is
emulating the behavior of the circuit using FPGAs in presence of faults.
Thus, FPGA emulates the expected behavior of the circuit under specific
conditions giving an impressive speed to the designer during the fault
injection process. The emulation-based fault injection approaches are
divided into the following categories based on the way they are
implemented:
i) Hardware reconfiguration-based approaches
ii) Instrumentation based approaches
M. Eslami et al.
5.2. Emulation-based fault injection approaches using hardware
reconfiguration
The overall procedure of emulation-based fault injection methods
based on hardware reconfiguration is shown in Fig. 6. In these methods,
in the first step, the design is described with one of the Hardware
Description Languages (HDL) by considering the type of the FPGA
framework. Then, by synthesizing the design and generating the bit-file
(that is an executable file for running on FPGA), the design is down-
loaded on the FPGA. In the next step, a benchmark is chosen to be ran on
the design to study the operation of the design under the test. Regarding
to the selected benchmark, a set of input bit-strings are applied to the
inputs of the circuit. These bit-strings include the information about the
configuration of the design on the FPGA during the operation and a set of
initial inputs for the circuit. After applying all input bit-strings to the
circuit, the output values are sent back to the host computer for further
analysis.
In order to inject faults into the circuit, a part of the circuit is chosen
and this time, a set of faulty bit-strings are replaced with the initial bit-
strings. These bit-strings also contains information about the fault loca-
tions and the time of the presence of each fault in the circuit. After
injecting each fault(s) and analyzing the effects of the injected fault(s), it
is necessary to remove the injected fault(s) and take the circuit back to
the initial state to make it ready for the further fault injections. This is
usually done by enabling a public reset signal. It should be noted that, the
duration of each fault should be long enough such that the effects of the
fault propagation are observed. The great advantage of using the hard-
ware reconfiguration for fault emulation is applying the faulty bit-string
only to a part of the circuit, instead of the whole circuit. In this condition,
only the selected part is being reconfigured and there is no need to reset
the whole circuit, saving a huge amount of time in this approach. Since
applying the faulty bit-strings to the all parts of a large circuit such as a
processor is not possible, it is necessary for the selected parts to be the
most sensitive and vulnerable parts of the circuit.
Choosing the sensitive parts of the circuit is one the most important
steps in validating the reliability of a circuit. Since the elapsed time in the
hardware reconfiguration approach is proportional to the number of the
selected parts for injecting the faults, designers have always tried to limit
the selected parts for reconfiguration. In Ref. [56], a framework based on
Xilinx FPGAs is developed to emulate the effects of the SEUs while trying
to avoid unnecessary injection of faults. The Xilinx Essential Bits tech-
nology is also used for increasing the accuracy of the framework opera-
tion during the fault injection process.
The hardware reconfiguration approach is the fastest one among the
emulation-based approaches. However, it should be noted that, the
connection framework between the host computer and the FPGA plays
the most important role in the fault emulation speed and it is always
known as the bottleneck of these approaches. Hence, without having an
Fig. 6. The emulation-based fault injection approach for simulating the
behavior of the circuit in presence of faults using the FPGA.
6
Integration, the VLSI Journal xxx (xxxx) xxx
efficient connection substrate between the host computer and the FPGA,
actually there will not be any acceleration in this approach in comparison
with the other fault injection approaches. Considering this point, in
Ref. [58], designers tried to minimize the connections between the host
computer and the FPGA. In this approach, another FPGA is responsible
for controlling the fault injection process and the transmitted data be-
tween the host computer and the controller FPGA are only limited to the
setup phase and the final instructions and the input bit-strings (Fig. 7).
However, it should be noted that the input bit-strings for running on
FPGA are only sent once from the host computer to the controller FPGA
for the first configuration run and after the next reconfigurations, the
results are stored in the memory that is located on the controller FPGA.
These results are sent altogether to the host computer at the end of the
fault injection process.
As shown in Fig. 8, designers usually select some parts of FPGA for
fault injection and download their chosen test benches and the faulty test
vectors via a host computer to analyze the circuit under the test. But most
of the fault emulation approaches based on the hardware reconfiguration
technique only target the reconfiguration memory part of the FPGA.
However, in Ref. [59], an approach is for injecting the SEU or MBU into
the memory units of the circuit using the Altera FPGA. Since this
approach applies the commercial tools for different steps of fault injec-
tion process, it makes this approach to be very flexible. This means that
the other synthesizable designs have the potential to be compatible in
this framework with performing some minor changes.
Moreover, this approach is based on developing in Altera FPGA
frameworks and its available tools. Since the most of the works in this
field is based on Xilinx FPGAs and its tools, this approach offers a wider
range of choices for designers based on their available tools and facilities.
Another advantage of this approach is the possibility of multiple fault
injections to the latching components of the circuit making the results to
be closer to the real conditions.
Fig. 7. The framework presented in Ref. [58] for fault injection using the
hardware reconfiguration approach.
Fig. 8. Different parts of the FPGA memory for injecting faults using the
hardware reconfiguration approach.
M. Eslami et al.
In Ref. [57], the circuit is separated into two parts including the
combinational and the sequential logic. Then, after injecting a SET or
Multiple Event Transients (MET) in the combinational part of the circuit,
the propagation effects are tracked using software simulations until
reaching to the latching components of the circuit. The software-based
simulation is applied for this part to handle the complexities of consid-
ering the electrical and the timing masking effects in hardware-based
approaches. Although using software-based approach leads to longer
operation time compared to the fully hardware-based approaches, the
results obtained from the propagation of the transient pulses in the circuit
are more accurate. After storing the faulty bits in the latching elements of
the circuit, the software simulation phase is completed and then,
emulation-based approach is used with the FPGA to investigate the ef-
fects of the SEUs in reaching to the main outputs of the circuit. Although
the time needed for this fault injection method is increased, the area
overhead is significantly reduced making it possible to be used for
large-scale circuits.
5.3. Emulation-based fault injection approaches based on instrumenting
the circuit
An impressive speedup can be achieved by using the hardware
reconfiguration approaches compared with the software-based ap-
proaches. However, in this category, the FPGA should be reconfigured
several times for injecting faults to different parts of the circuit. This leads
to consume a huge amount of time because of the several data trans-
missions between the host computer and FPGA. Although this amount of
time is several times less than the time required for the software simu-
lation process, it still cannot be avoided by the designers. Hence, this has
become a motivation for using the instrumentation-based fault emula-
tion. In this approach, an extra part usually called “saboteur” is added to
Fig. 9. Adding the saboteur parts to the a) input parts and b) output parts of the
circuit components.
7
Integration, the VLSI Journal xxx (xxxx) xxx
the circuit for each fault location which is responsible for changing the
value of the specific signal regarding to the fault model chosen by the
designer (Fig. 9). The saboteur part may be located in the input (Fig. 9a)
or the output parts (Fig. 9b) of the combinational or the sequential part of
the circuit. The location of this part is defined by the designer regarding
to the chosen fault model. Adding the saboteur parts to the circuit is done
by the designer only one time at the early stages of the designing. Hence,
for configuring the FPGA, the bit-file is downloaded on the FPGA once
making this approach to be much faster than the hardware reconfigu-
ration approach. However, the area overhead has a significant increase in
this approach making it impossible to be applied on very large circuits.
As shown in Fig. 9, each saboteur part has an enable signal which is
triggered in the cycles defined for injection of faults. The enable signal is
determined based on the fault model and changes the value of the signal
that goes through the saboteur part. This change can be a logical ‘1’ for
the Stuck-at-One fault model, a logical ‘0’ for the Stuck-at-Zero model, or
even a bit flip for SEU models.
As mentioned before, one of the challenges in fault emulation ap-
proaches is the complexities of modelling the electrical and the timing
masking effects. This is because, the digital design tools are incapable of
considering the timing delays after the synthesize process. To overcome
the mentioned challenge, an approach is presented in Ref. [54] to model
the delays of the circuit on the FPGA when analyzing the effects of a SET.
The proposed model first defines the delay of each input or output signals
of the circuit components to compute the critical path of the circuit.
Then, regarding the fabrication technology of the FPGA, the largest
available shift register size is defined. By dividing the maximum delay of
the gates to the size of the largest shift register, a basis unit is created for
the smallest delay unit that is possible for the FPGA. Then, each delay of
the gates is considered as an integral multiple of the basis unit. By
computing the new delay values for each gate of the circuit, the delay of
the gates can be implemented by using the shift registers. For instance,
for a gate with the new delay value of 5, a shift register with 5 blocks is
considered (Fig. 10).
As shown in Fig. 10, the delays for each gate may be a single gate
delay or a multiple gate delay. However, it should be noted that, shift
registers usually take a lot of area of the FPGA. Hence, as the large
number of the gates in the circuit have more than two inputs, considering
the multiple gate delay model for the gates of the circuit may lead to
extreme area overheads even for the small-scale circuits. Hence, the
single gate delay model is used in this approach. By implementing the
delays of the gates on FPGA, modelling the electrical and timing masking
effects which are dependent to the gate delays will be possible.
Inspired from the approach presented in Ref. [54], an approach is
presented in Ref. [55] to consider the electrical masking effect. This
approach is based on sampling the amount of the voltage passing through
the gates such that changing the voltage level from high to low and low to
high is sampled and stored on the FPGA. The samples contain the cap-
tures from the voltage curves and their range varies from 0 to VDD. On the
other hand, the delays of each gate are stored in the shift register similar
to the approach presented in Ref. [54]. Based on the changes in the
voltage curve, the counter starts to count in an ascending or descending
order and if the voltage level goes beyond or lower than the specific limit
while the counter is counting, the electrical masking effect is determined.
An approach presented in Ref. [60] tries to reduce the area overheads
in instrumented-based fault emulation approaches by performing a
Fig. 10. Modelling the gate delays based on the approach presented
in Ref. [54].
M. Eslami et al. Integration, the VLSI Journal xxx (xxxx) xxx

Fig. 11. The overall overview of the presented approach in Ref. [61] for fault injection.

Table 1
Comparison between the available fault injection techniques for the main characteristics.
Properties Software-based Techniques Hardware-based Techniques Emulation-based Techniques

Dynamic Static Contact-based Without Contact Instrumentation-based Reconfiguration-based

Cost Low Low High High Medium Medium

Time High High Low Low Low Medium
Area Overheads None None Low Low High Medium
Complexity Medium Medium Low Low High High
Risk of Damage None None High High None None
Accuracy High High Low Low High Medium

probability-aware fault injection. In this approach, a weighted distribu-

Table 2
tion is introduced based on the fault probability of the circuit elements.
Main benefits and drawbacks of fault injection techniques.
This enables the authors to only one Pseudo Random Number Generator
(PRNG) for the entire design instead of using many PRNG in similar Technique Benefits
approaches and consequently, reduce the number of logic blocks needed Software-  Enables early reliability
on FPGA. based assessments (no need for a
Another approach trying to enhance the area overhead is presented in prototype of the design)
 Does not require any extra
Ref. [61], which aims for SEU modelling by changing the default Xilinx hardware (only a device for
libraries that is capable of performing the fault emulation for the running the user-modified
large-scale circuits. In this approach, as shown in Fig. 11, first the HDL code is sufficient)
description of the design is synthesized using the Synopsis Synplify Pro  Wide range of fault models
can be injected in this
tool and a netlist is generated based on the available FPGA technology.
technique
Then, the generated netlist is taken as an input for the developed tool Hardware-  Fastest fault injection
called “MODNET” which automates the modification of the flip-flops, based technique among all other
latching components, logical elements and the multiplexers of the ones
initial netlist. The output of this tool contains several input signals added  Does not need for
implementation or modelling
to the circuit in order to enable the injection of the SETs and the SEUs. the target design
After adding the new input signals, a memory controller is also added to  Results are very close to actual
the design to manage the connections of the available SRAM memory operating environment for the
located on the FPGA. The SRAM memory stores the results of the fault circuit
 Actual permanent faults can
injection process. At the next step, the design is being re-synthesized for
be injected at the pin-level
final validation. If the modified design passes the second synthesize fault injection
process successfully, the next steps for bit-file generation of the design
and running it on the FPGA is performed. Emulation-  Early reliability assessments of
based the circuit can be done much
faster than the software-based
6. Discussion approaches
 FPGA and other commercial
Choosing a proper method for performing the fault injection process tools used in this technique
in digital circuits can be a determinative factor in reducing the imple- are available globally with an
acceptable cost
mentation costs, decreasing the time to market of a product and
 Enables the fault injection to
increasing the performance and the accuracy of a digital component. We be performed on very large
tried to give insights into the state-of-art in fault injection techniques and scaled circuits
motivate the researcher and reliable circuit designers to further improve
these techniques for more efficient reliability evaluation of future digital
Drawbacks
 Needs a lot of time for each
experiment
 Quality of the model
implementation by the user
affects the obtained result
 Actual faults in real
environment of working
circuit may be neglected
during the experiments
 High risk of damage for the
target IC
 New packaging technologies
and high level of density in
newer ICs limit the efficiency
of this technique
 Needs very expensive and
limited for fault injection
which are not available for
everyone
 Needs at least one initial
prototype of the circuit for the
experiments
 Accuracy of the results are
lower than other techniques
since it is difficult to consider
the timing delays in FPGA
 The implementation of fault
injection framework using this
technique has the highest
amount of complexity
 Significant area or
computational overheads may
be imposed in the case of fault
injection for large circuits

8
M. Eslami et al.
circuit designs. Table 1 shows a brief comparison between the available
fault injection techniques for the main characteristics in terms of cost,
amount of time needed for completing the fault injection technique,
amount of extra hardware needed, complexity of implementation, risk of
damage to the IC (if available), and the accuracy of the results. Also, in
Table 2 we summarized the main benefits and drawbacks of each fault
injection technique.
7. Conclusion
In this paper, different fault injection approaches for digital circuits
has been studied to help the researchers choose the proper fault injection
technique based on their demands. We categorized different fault injec-
tion techniques mainly based on the amount of hardware they need as
follows:
1) approaches that do not need any extra hardware for implementation
(Simulation-based software fault injection)
2) approaches that needs only commercial hardware and tools available
globally (Emulation-based fault injection)
3) approaches that needs Hi-tech tools and hardware that are very
limited (Hardware-based fault injection)
High computational overhead in software-based approaches and un-
affordable equipment costs in hardware-based approaches makes the
motivation of using the emulation-based approaches for performing the
fault injection process in digital circuits. However, choosing a fault in-
jection technique depends on many factors such as budget, time and
knowledge and the final decision is made by the user considering these
factors.
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