LABORATORIO 2

Memory Systems

PRESENTADO POR:
CARLOS JAVIER SUAREZ

ESTUDIANTE DE INGENIERIA ELECTRONICA

A:
DOCTOR:
JUAN CARLOS MARTINEZ
DOCENTE DE MICROPROCESADORES

FACULTAD DE INGENIERÍA ELECTRÓNICA

UNIVERSIDAD TECNOLÓGICA DE BOLÍVAR
CARTAGENA DE INDIAS
2012

[1]
Homework

Accessing a direct-mapped cache. Assume that memory is byte-addressable, memory

addresses are 32 bits wide, a cache line contains 2w= 16 bytes, and the cache size is 2L= 4096
lines (64KB). Show the various parts of the address and identify which portion of the address is
used to access the cache.

BYTE: tamaño de bloque

2^X= 16B X=4

INDEX: numero de lineas o tamaño de cache

2^Y= 4096 Lines Y=12

TAG INDEZ BYTE

31 16 15 4 3 0

Accessing a set-associative cache. Assume that memory is byte-addressable, memory

addresses are 32 bits wide, a cache line contains 2w= 16 bytes, sets contains 2S = 2 lines, and
the cache size is 2L= 4096 lines (64KB). Show the various parts of the address and identify
which portion of the address is used to access the cache. Cache address mapping. A 64 KB

2^X=16B X=4

2^Y=2 Lines Y= 1

2^Z= 4096 Lines Z=12

But 2^12/2= 2^11

TAG INDEZ BYTE

31 15 14 4 3 0

Cache address mapping. A 64 KB four-way set associative cache is byte-addressable and

contains 32

B lines. Memory addresses are 32 b wide.

How wide are the tags in this cache?

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