Conquering FinFET challenges

Here's a look at the challenges from custom/analogue, digital, parasitic extraction,

and signoff perspectives.
By Rahul Deokar, Gilles Lamant, Hitendra Divecha, Ruben Molina and Chi-Ping Hsu
Cadence Design Systems

In the electronics industry, the introduction of FinFET technology is the next key step forward. The FinFET’s
deployment circumvents fundamental performance and power characteristics planar transistors exhibited at 20nm
and were hampering the value proposition of node migration. FinFET’s put the industry back on track. However,
the combination of the new device types, 193nm wavelength lithography, resulting manufacturing-based rules, and
materials physics are creating new technical and collaboration challenges.
A FinFET is a new type of multi-gate 3D transistor that offers significant performance improvements and power
reduction compared to existing planar CMOS devices. In a FinFET, the gate of the device wraps over the conducting
drain-source channel (figure 1). This results in better electrical properties, providing lower threshold voltages and
better performance as well as reductions in both leakage and dynamic power.
Experience at 28nm and 20nm has shown the critical importance of a vertical approach to collaboration in creating
a complete enablement package for a new process node. This has become even truer for 16nm FinFET technology.
To create a viable offering, all of the elements comprising enablement (process, cell library, EDA, and IP) must be
optimised with respect to the other elements. As the manufacturing process evolves into a yielding node, the
enablement package must track to the changes. Because of the mutual dependence, one element cannot be change
without affecting the other elements.

Figure 1: In a FinFET, the transistor gate wraps around the channel or “fin.”

While Intel started using FinFET technology (which they called “Tri-Gate”) at 22nm, most foundries are expected to
adopt FinFETs at 16nm or 14nm. However, the backside metal layers will typically be kept at 20nm. Test chip tape-
outs for 16/14nm FinFET processes started to appear in 2012, and early customer design engagements may start in
late 2013.

Challenges
Like any new technology introduction, however, 16/14nm FinFETs pose some design challenges. Most of these
challenges are on the custom/analogue side, but there are also issues that digital designers need to be aware of.
This article looks at challenges from custom/analogue, digital, parasitic extraction, and signoff perspectives.
In addition to FinFET-specific challenges, the 16/14nm process node has challenges that would appear regardless
of transistor technology. These include:
• The need for double patterning (using extra masks) to get features to print correctly at 20nm and below
• Layout-dependent effects, which emerge at 28nm or above and become more problematic with each new
process node
• Potential 50X or more differences in resistivity between top and bottom metal layers
• Electromigration increases with each lower process node
• Dozens of new and complicated design rules
• Complexity – how are you going to design and verify billions of transistors while meeting time-to-market
demands?
Given all the challenges, Cadence expects that the EDA industry may collectively spend $1.2 billion to $1.6 billion for
design tool R&D at 20nm, 16nm, and 14nm combined. In addition to handling FinFETs, design tools at 20nm and
below must support layout analysis before final layouts are complete, colourisation of layout features for double
patterning, and accurate parasitic extraction and estimation. To handle the sheer size of advanced node designs,
tools will need high capacity and fast run-times.
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Custom/analogue design challenges
Custom designers working with standard cells, and analogue designers working on IP blocks, will notice some
changes with FinFETs. In particular, some of the design strategies they have used in the past will no longer work.
This is because the intrinsic device characteristics are different.
With planar transistors, standard cell designers can arbitrarily change transistor width in order to manage drive
current. With FinFETs, designers cannot do this – they can only add or subtract fins to change the drive current.
Fins come in discrete increments – you can’t add three-quarters of a fin. This issue is sometimes called “width
quantisation.”
There are other issues not as well-known as width quantisation. For example, body biasing will generally be
impractical. The relatively large distance of the top of the fin (the active part) from the bulk means that in order to
modify the device voltage threshold by biasing the bulk, one would need a very large voltage supply, which is not
available in 16/14nm processes.
Another challenge is a side effect of something seen as a digital advantage – flat subthreshold current (figure 2).
This rules out analogue design styles that are based upon measuring current variations for fairly small voltage
variations between the source/drain of a planar device. The bottom line is that the analogue designers are going to
have to come up with new techniques to take advantage of FinFET device characteristics.

Figure 2: Comparing the electrical characteristics of a planar FET to that of a FinFET

(sub-threshold current).

Parasitic resistance and capacitance represent another challenging area for the custom designer. As the device
shrinks further on the horizontal plane, and at the same time “rises” in the z-axis dimension, new coupling to
neighbouring elements appears and creates additional parasitic challenges.
Starting at 20nm, Cgs (capacitance gate-to-source) and Cgd (capacitance gate-to-drain) effects become an even
larger concern, and contribute to the Miller Effect that feeds the output of a circuit back into its input through the
parasitic capacitors. Also, additional parasitic resistors in the source/drain area affect device performance. What’s
needed is a design methodology that very quickly enables the designer to see the effects of these elements on the
performance of the circuit that is being developed.
Layout is not without challenges either, although these are more “mechanical” challenges than “intellectual”
challenges. There are rules, and designers must obey them. The problem is that there are so many rules that
drawing a piece of layout to follow them becomes a very tedious exercise. Thus, layout tools must automate
conformance to rules as much as possible.
One new issue is a side effect of how the fins are made. A self-aligned double patterning (SADP) process, also called
sidewall image transfer, is used to create the fins. SADP requires that all fins be aligned within a given fin area. This
forces the layout engineer to conform to a localized grid for each FinFET area, and it is not always a simple uniform
grid. This is in addition to the global manufacturing grid for the “active” layer.
Clearly, the introduction of FinFETs into the custom design world comes with new design challenges. Some are
mostly intellectual challenges (how do you take advantage of the new device characteristics), and some are
mechanical (conforming to design rules in layout). EDA can provide assistance in both areas, and should certainly
help automate any mechanical aspect of designing with FinFETs.

Digital implementation flow

If a digital designer has access to automated, FinFET-aware tools and characterized libraries, the main difference he
or she will notice with FinFETs is better power and performance characteristics. But digital designers at 16nm or
14nm will also face new and more complex design rules, double-patterning colourisation requirements, and more
restrictions on access to cells and pins.
From an EDA methodology point of view, 16/14nm digital technologies should be very similar to 20nm planar
methodologies. But some added information and some new capabilities are needed. Figure 3 provides a quick
overview of the digital implementation flow that’s required for 16/14nm FinFET technologies (DPT is double
patterning).

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 Figure 3: 16/14nm FinFET digital implementation flow.

Floorplanning, placement, and routing should be double patterning-correct, meaning that all metal topologies in the
design are validated to be free of double patterning conflicts such as odd-cycle conflicts or metal layers that violate
SAMEMASK rules in the LEF file. (SAMEMASK rules describe special handling for nets that are masked by the same
mask). One particular step in floorplanning that is important is power planning. 16/14nm EDA methodologies must
have the ability to validate that all power routing is free of double patterning violations in relation to other power
routes as well as hard macros.
Standard cell placement must be double patterning-correct, too. Standard cell and hard macro pins, if colourized,
must be separated in accordance to SAMEMASK rules, meaning that metal shapes of the same colour must not be in
adjacent tracks.
There are a couple of ways to address potential colouring issues in standard cells. One way is to insert spacing in
between violating metal shapes, while another way is to change the orientation of standard cells to prevent or fix
double patterning conflicts (figure 4). All these considerations apply to floorplanning and placement as well as
optimisation. A double patterning-correct placement and optimisation engine should ensure that these steps are
completed without introducing double patterning violations, so the user does not have to manually verify colour
correctness.

Figure 4: Double patterning-correct placement can flip or rotate a cell to

avoid colourisation conflicts.
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Double patterning rules apply to routing as well. What’s needed is a physical verification engine that allows the tool
to validate 16/14nm rules and SAMEMASK rules while routing. After routing, designers should either run an
implementation-stage check on the routes to ensure adherence to 16/14nm double patterning rules, or invoke a
signoff tool to run a signoff check.
One important aspect of 16/14nm routing is the difference in resistance of the routing layers. At 16/14nm, the
difference in resistance between a lower metal layer such as M1 or M2 can be 50X or more compared to higher
metal layers like M7 or M8. Therefore, routes that traverse a long distance should be routed using higher metal
layers as long as there are tracks available. For short-distance routes or routes in highly congested regions, this
becomes less of an option because of the high usage of vias in that route. An optimisation engine should take routing
layers into account in order to leverage higher metal layers to reduce net delays.
In short, from a placement and routing point of view, 16/14nm methodologies are similar to 20nm methodologies.
Both require double patterning correctness. In 16/14nm FinFET-based technologies, there are additional process
rules that have to be adhered to by the placer and router, which are all handled automatically.
Other aspects that are pertinent to 16/14nm physical implementation include the size of designs, as well as timing
closure requirements. From a design size point of view, 16/14nm designs will be on average double the size of
20nm designs. Design methodologies will have to be able to handle design sizes up to 200-500M instances at a full-
chip level, and up to 10M instances on a per-block basis. Because of this, technologies that are able to significantly
reduce peak memory and runtime in digital methodologies will be important.
In addition, to address the increasingly aggressive performance requirements of 16/14nm design, technologies like
clock concurrent optimisation, which merge clock tree synthesis and optimisation into a single step, are able to
improve design performance in a big way.

The parasitic extraction challenge

Of all IC design tools, parasitic extraction is probably the most affected by FinFET technology. Extraction plays a big
role in obtaining accurate timing analysis results, and parasitic extraction for FinFETs is significantly different from
that for planar CMOS devices. FinFET models are part of a 3D modelling framework that has significant challenges
in terms of capacitance modelling, since it involves gates and fins and external contacts. FinFET gate to source/gate
to drain capacitances are more complex than those for planar FETs. FinFETs pose resistance modelling challenges
as well, since current distributions are non-uniform and complex. This requires advanced modelling techniques for
accurate resistance.
From a manufacturing process point of view, the layer stacks for FinFET devices are similar in complexity to 20nm
planar devices; however, the FinFET devices themselves become 3D in nature. The existing 20nm layer stack
includes raised diffusion and co-planar base layer metal structures. In a FinFET structure, the device diffusion
moves from big diffusion polygons to discrete fins. The poly conductors run over the diffusion fins with two
thicknesses, as does the contact layer from M1 to diffusion.

Figure 5: In a 3D FinFET device structure, the fins are controlled by a poly

gate from three sides.

In FinFET devices, metal (poly) exists in the same space as the diffusion, and the diffusion metal cuts away the poly
metal with a bit of spacing to accommodate gate oxide dielectric material in between the two conductors. The net
result of this is that the capacitance becomes truly 3D as compared to planar MOSFETs. Fringe capacitance (Cgs)
now requires a 3D modelling framework to account for these effects and for better accuracy. Furthermore, a high-
quality 3D solver is needed to generate very accurate pattern libraries for building these models.

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Poly resistance is no longer planar due to the 3D electrodes of the MOSFET gate. Furthermore, the FinFET source
drain resistance network may not be accurate in the partial contacted layout—the electrical currents would
concentrate in the shortest path from V0 contacts to the MOSFET device terminals. Extracting such a resistance
network would result in uneven electrical currents into the devices, resulting in device failure. Hence, accurate
modelling techniques are required to address the correct extraction of the resistance network for better accuracy.

Signoff for 16/14nm

Designs at 16/14nm will bring added complexity and variation. This means larger designs in the hundreds of
millions of placeable instances, and an increasing number of signoff corners required to cover process and
environmental issues. Today’s signoff engineers are already feeling the pain of trying to analyse and close timing at
design sizes up to 100M instances and across as many as 300 mode/corner timing views.
The typical time spent in this part of the design phase can be anywhere from one to three months. To make matters
worse, signoff is the last step in the flow, which means that schedule estimates typically slip during early parts of
the design process, leaving less than the allocated time to complete signoff.
Getting to signoff-quality design closure will be paramount at 16/14nm in order to minimise schedule impact.
Furthermore, links to physical implementation will help to resolve uncertainty during the signoff optimisation
process. What’s needed is an engineering change order (ECO) capability that solves this problem by linking to the
layout database, performing distributed multi-mode, multi-corner (MMMC) timing analysis with signoff accuracy,
and creating timing-optimised ECOs with physical design directives.
Critical path optimisation based on path-based analysis can also help reduce pessimism. This ECO capability,
combined with a highly effective leakage optimisation engine which utilises signoff-accurate timing, provides the
best design closure turnaround time and power reduction.

Conclusion
Like any new semiconductor technology, FinFETs pose some design challenges, especially for custom/analogue
designers. 16/14nm FinFET processes will require some changes to custom/analogue and digital implementation
flows, as well as parasitic extraction and signoff. EDA providers including Cadence are making extensive R&D
investments to develop tooling that can automate 16/14nm FinFET design as much as possible, allowing designers
to simply take advantage of the power and performance benefits that FinFETs bring.
No one company can enable 16/14nm FinFET design. Today, a collaborative ecosystem including EDA providers, IP
vendors, foundries, and customers is working hard to solve FinFET design and manufacturing challenges.
Cadence, for example, has worked closely with eco-system partners to form a vertical collaboration surrounding the
deployment of 16nm FinFET process technology. By engaging at the early stages of process development, mutual
customers designing with the new node can also get started sooner. Cadence’s multi-year investment in FinFET
support is resulting in foundry test chips and industry collaboration.
What are designers going to do with all the capacity, improved performance, and power savings that FinFETs bring?
History proves that when new technologies are available, people find ways to use them to create new and often
unexpected value. FinFETs can potentially enable the next leap forward for mobile devices, cloud infrastructure,
and the “Internet of Things.” As such, they represent a new frontier for the electronics industry.

About the authors

Rahul Deokar, Gilles Lamant, Hitendra Divecha, Ruben Molina and Chi-Ping Hsu are with Cadence Design Systems.

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