Name: Writtwik Dey

ID- 161001002103

Circuit diagram

Code-
entity ha is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC;
end ha;

architecture Behavioral of ha is

begin
sum <= a xor b;
cout <= a and b;

end Behavioral;
Truth Table

A B SUM COUT (Carry)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

OUTPUT WAVEFORM -