ONIT-4 Tntreduction to Microprocenor Architechtore Trtrecluction '- The comput are broadly clasified into treo categories - Trey ae mainfrare , rin omd micro compubrs: Moinfiame:- The torpet curd most poserbyat compudens | are moinhrome..conputeis: They may occupy an gntine room: ‘they axe designe to Core ak vey high sped with large data words ord haus prowsive arnt | Premogy, | od ber military defence control, busines data procexing applicati SerTBM4381, Honeywell DPSS , ceayx~ mp/ye Mini Compubers + the gale down version Ob mainfrorre| computins gre ebten callad — mini computan + the mninicompubrs ove fen Holly pes a Single Voce Gr bax: (Mini Computon usually bts ino Si york) ard FIP More Lowly, Satter dato. weds & VAX MW a3q ~ Datogenenal - ™v/ eooon ard i Het < MAGNUM Microcomputer - microcornputin = axe. Salt Computer They Rorga gral confreuien that work dinectly with ord (om adver a few proud lenge umia tat work Jigtes ceremony to lage wnt Unt work | from yebie wordsdinectly wth 6y bit oords ond con acces milion o billion o& - bytes 6b — memoxy” Sei TBM pe/eo , ATG , Aye AT yg, etc Mico Compute :- “The. blak diagram & Simple microcompub» ghown — below . The major ports are the canta procening anié GP srremory amd Yo davcei. ~~ connecting thew ports with three StS 66 povallel Lines cated §buwer - They are addres bes) cata bus ord’ the = contaol Bos: Block diagram & microcompuder :~ ___ pata bus mnemosy CRAM £ Rom) Addie’ bus igi Block Diogeam of micro computer“Taek 6 tha Cutt siote —teorld« such" Keyboard, |vidto display ete: jout. ue addres Memosy “The memory seclion usuably consists & a rib 6 Ram and Rom - Tt roy aluoy have the magnetic hard lis or) opti disc» memoty has tuo purrpoic «pragrom memory , data memory: section ablouss the comput Inpat Joutput + the do world wd send fp bake Wn dota from outside cenbial procesirg amit i THE centro procenirg unit leintnots Ue operation & te — Compulen «The cpl os nie is coued micro prowsor adkbrect b+ The oddlrex. bus consul Of 16, 90, B421 poset ggrot nes . on Yose Lines Oo cpo ser ob He rremory location mt is Be ponte” boy oe vad from. the memory space com be defined Y number | & aan Lira: Ih te. CPU Fas ‘ny’ oddrey ines it howe 2” mamoy Locations. pata buct- The dota bus contuts ob & 16,2 portlet Sigal Lires The data bus Lines ore bre bidinectional: This menms that Ue cpu com rod lata Wn fyom = merrany, 07) bromo port on VeeLine or it cam. sero cota out to a or to opant on these Lines 7 control bas: the contre bos consists a Uto 10 panalter signal Lines: the cpu sedis ouk Signals on te contol bes tm enable te outputs of addrened memory duwice Coo post devices Typical contro gignals due. MenDay Reod , memosy write y “Yo read , Wo rite: Microproceod:- Micro procesios is the Control processing unié 6 miKvO Computer build ona Single Eleclion} chip: Tk is te Pant 6 any Computer « tystem Te is ced t? — pentorm speciic operations Like anthimetic and § lagical —openations. . Gvoluation — ef — micro processors t~ 4. History shows os that the ancient. Bobyloniauy pres Papret, WN bogus ta aikowk 908 2. Te 1642 @ lase — pascat develeped cot ing machine wring geen! ond wahrele BPuring 19yo- 50 developed wilh relays and vyocume — bubes- 4 Net the biansistors ond solid shake elactnorics wee od bo build computer in 1960"Finally » tre advent sb Ie bd tp & ook eh microprene sor monte Galuation 6h mip: WB artegosized into 6 generation 1st 9rd ard a ord 5M T* Generation :- (1941 @ 1993)‘ =| ft —mnionpenien nol, Ott uot inte jin iaaratowelpped + by Intel Tk ums oO 4 bit yor rum ok }08 H2- amd contain 2300 qhey were fabricated’ using pros ole ow Cort’, tow ipeed ard wee mot compatable proces trom sistous* fechnolagy nich prev Low intel 4040, ook, Bow CEC 29 Generation: ciaay ~ 1978)" 2" generation pronked.. Ya, beginning oh very ebpident — mivopre Leonor they sone rremugectured in pumot tach -gy © The NMOS proces offers fsb ipetd’ ord higher donsity thom pms: Some ob 24 geroo| foon precesors are Fntel 8085, rote® 'F GFOO, m6go9 , 2ilog 2803 generation Cag 1980 The 34 gereration indioduced WW 1UFR ord — doriiroted by intels goss ard vilogS 28000 whicm wae j6- bit procenorr they wee derigned by wing Hmos Cigh density ones) chyers bet speed — power product ond. hightr | get= TIntel_ ok, motovola mesooo, 286 ,1%o- 24000 ah gpreration += C.48l= 1995):- 44" genenotian mico-pr| contains = mox thom O milion tnomfutor eo oe bit prowmors, the cobs with high density cory high ypesd cmos CHe mos) taohnOlegy (toe power version ch Hos) Ger Trkel 386, 486, Mmego20, 680% CK: gh genenotion (1995 - ULL the dato): 5t generation pricre procusors contains = more thom jo miluen bomsivtors - Tnte penborn iso speed oh 266 mre 64 bik: processor maximauen Chock Sete perio 1,2, 3, 4, pro etoro process & mir controllers *~ [avo Feenlcoart i: = | | Aa Lcd [Accurutti | | 1" | ROM | | RAM | = fear ‘ | expr | City rnicro PSOSEOS ee [Prypam count | “Creu, Block diagram of wicercartota | Micro procesoy ard micro conbrollen olipgerences += micro pees is generek pup chigitol| gor pullan © “cpa "Generathay, Pe on a chip: Te contains anithmetic Logic onit Catv) prgrem counter (po) a stock ponte Cap) Sone working Registins » a clock interopt — dircuits: To rake a compel odd §=memosy , usually Ron! microcommputu9s » one mnt and RAM, momoxy dlecoder! » oscillator & 10 Jolovices: SUCH OS goth ord paraltet pore micro contyollen which is tue Computer on a contains cpy~ AW Pe, Sp and register! Bming cneuit , chip which tn octtition RM, RAM , ponolleL amd geniak T]0‘|g086 microprocenors ~ coors ard = clack Cincuit athe primary action ob mice Contrallen is contral the — openation oh a rrachine wing fixed prorer gored «= Pom. The BES howe intberopt pins: The oxden Ob priowity oh the interrupts Is TRAP, RSTHS , RSTE5, RETS+S and INTR: ‘pntetls yst 16 bit procesor . derigned voting Himes technolegy , contouns 29,000 tromsistor The ees is packed a UO pin DP and seqpiner oa gingle +8¥ Supply: The #96 doesnot have internat cwwck , e284 CuK gonenakion is xd be generale the suquied — Clock: the maximom interal cock BmHs. The 8080 vieH A 207 bie & S086 is i ‘memory a7! here 1& acceu oddtres be accen upto a0 =} mB ob memory: The 8086 com operates tn tae modes minimorn nthe moximunm — media $086 cpu divided w7bo lwo inclaperclant ob functional ports 4. Bos intenfowr onit 2 Exeuttion nit: pividirg work b/w G20 ynits- Speed up procening.| B10 Clos Tnaapoce ont) :- the giv wot oe | adden, etches inetruction — ram — mernoy , Kode | ae from memory 6 | | to posts ond memory «BU hardels alt transfow ‘ee data ord adden 0 burs hor exccition ‘umil «piv contains: instruction gueue , Rgrent snegivo_, znt@vction gorse = - = pest ard wit dato Execution onit (E0) *- The — Execution nib ob aes |veus te pio whee be fetch = Be intbmction Go) yer, dacod1 Instructors orrel Execute | | dota | ensonuctios — CO: consists Ob 1+ Flog ougiiter » 2 Generel purpoie egitim 3 control Civcultony 4. “Intbroction cecoden 5 ALU 6. point amd Tretuction regisliu: “conbiol uineuitory + control evmeuikany 66 ev jnta rol operation Le pos ING cet for phyical addvew seas’ ard a prodaceding — inuction byte Your C6 byte tong): the bos Untajace unit makes Ue System is bos Sigtols available bor &xternal inborfeci ob Oe devices r 86 achive the cleerilapped - feech amd Execution. cycter - eahile op code is fetched by RIV, the gv |\o execuky Uw previows decocid initroctions. | | | cine execution umit contains ‘the’ sugister, | get oh B08 Except segerent —nregist» one Ip | [ate he tes BF FY y, 165 bit agregi rt decoding ynit ard timing, and contrct uri evicy. | 1 | jaBepitien _orgaraiaation 8066 -| wire gore contains — ounteen 16 bit vegies grey one, groped into follasirg cabgovies | 4. General porprs Registers : | La. pointers 2 aretux RegivO” 4.sigment Regitter eqqrybuction pointe ond — peall Berea: os goes 16 thon bela |e segistin orgomization Accurnalatos AH AL | | spose, [pH pie Gereral propose | Coumten cH el aegister | Dato, oH ob Pointer. ongisten | | \ sre oxgt | te es “ | ey |e a 2p —_ finetaction pointes | Flog? status Register :Genera purpose — Register there or foun 16-bit | gprera — pusipore vregister AX, BX, CX, DX. Bach ob (these general pexspare ico 8 bit) ougister com be used Either a4 a 16° bit egister Cor) as tw0 gbit pegisrs- They one usd % held anithmatic ard kagicat oporramolo ond = eAULES- AX Sowers as Accumulator = Bx , Cx, PX ment for data ao "fpr pedal prpore x= bare segisen , ¢x- conte. px held’ To addles In multiplication Ue reult will Flore 16 bie wo AX Sane Ax Rerainden i DX “noe Uram 16-bit io indwwisieny ye"bib. quotient pointers There axe too pointns sp ord BP: Stack | pointer it ports to the stack top oddiess: 1 | contains sch added Th posi, pop, cAlt, relum | insbroctzons stack —oddbesi is Conputidl by outing ve cortents ob = Sporelss: the pp is te bose yegislan bor occening stock within stack , Sweat data 04 may exi is ued bp bold te off et OG Ge kate glock — segrren’ Gp lo cata ‘orua wma@ aad Gegisto > ST ond BT ave index sepistons. thee ord tn rmermory C0) Stack addsen corepotalin Th etoin sbiirg weblion, st is ond Lidicoit “gence ~ inde oned - B...08 olesnatien icon letnwch’ “cose contents. ab $1.02 oublad to the contere a ps th ge the actual Sowce adolrery ae is aad to tre conterts oh «tS gtk actual destination adadren o Ue dato $i, pi abo UK o4 gentat punpore megitr ‘segment Region athe * merniory oxd with om Bogs bast | sytem is duvild into te follasing foun yp Segments 4. code Segment 2. Data segment tack segment 4, xlra segment. Bach rremory “great com owt 0 Mmpacity uple 6urB the: | goss contairy tke boltawirg run Sgrnent sregittoy.| 1 coke Segment Regisan Cc g. Data segrnent Rogishn CDs) 3 Stack Seqrnent Registn C55) 4 Sb Segreent = Registun (68).Tnibuction points Ip) The inibyction sinter oti os pogrom coed - Te points ke the [rece — initroction to be Excueteol cithin the currently [Executing cote segment + ‘Te contents is aubyrotically Nireuennented! ok We SPSURIRING IG “prggiitony {proceeds the Ip holds a 16 BIE ag gek pointig 6 next inttnuction § cooe within te Canrent cake (Geode segrnerte | | Stouts Regi ter - The 9036 has one I6-bit status pegistor also called flag segiste Cr) program stot word (psw)- Te has nine bags, Suen bits semains unused: cut of nine, Six We Cortition flogs-thg can wes meee by ' cpu depending on Ge neulb. | Sore oouith netic / kngic opootio” serninirg + | | qt. ore — conbiol Hlags «There bagi am setJreet by programmer’ the — status bags % sore shown below: Hee o< Bb xe |x he at LAPT Hea x |ay a the ladkliction cor) db a bare, is | duinirg Tris wt to | ib thee i aya mse, bi portion ncultirg from om needed of ma | gupbiaction | | pooy flog cpr): Ib the Loo ovdler 8 bits ob, He Teulk tk om openotion conteirs en 0: is gt tolig it is odd is tre: ponity bi. is. # —_ ak ) pusillany coy blog? TE 1s we to axyok & BES vemllig fon OM addition o- 0 boo sgupbaction » Lowert mibble Zeno blag CLAY Be is ak hI arth metic |e rzemo 1b ew oa | js sequined — rom bie yin 3 br ib re nenulk a om gr Uegicak operation if wn In con ib js wo is eb w 1 ib te mse & 8g piog 82 me | pe sok OF OM | ‘ | oven poco too longe & bt axithrretic opeation is 7 peg COP)" “nase Ay signed apenotion, | | ping is wee be, rib the ee a | we the* no Oh bE auoiloble || [ee eed Cae ee laa eS Fe sae [= allows uxt coeiilan one etalon. & &. | progprom of ote be del99i"9 - when TF b ie ° t,o papi com be sun in Sige - Step rrooles when om interrupt is secggnized y the TF is autores cally cleared: | i | “ apptenopk flags= Te is ae. interruple.enadble./ ol | floa ap ie is geet, Ue matkatje iterrupe | | | Inte & e086 iS enabled ord ib it is 0 Ue interop iS cluabled: is ened US “tty -openodttons | ue" storing bayltd are aceered fyom memory acl e b> Low memory godess | geno. The Sing bytes ont accened te high memory aches. | pirectional egy Te high when it Is | gre los memory adden meray argorsaation of | | sonore segroentation The marcory ip am 8 036 baseol | organized os ggmented memory» The | comple pyres quailable memory may be divided into ro: lagicoh segments: Lach & | lis syk byte w sre owd aodlressed by one ob | | phe gent oagis fet ~ | gystem isthe cpu 8&6 is ape 0 addres imb Ob physical rremony - The Complete 1mB memmy com be dwidet ine 16 gegmentS each segment a 6 fhe. the addres “Op segrents © may be aes FEFF H. So thot the physical c0000H = FFFFF H* In above souid ers Lee none ovekagyicg gee aw ooooH romge bom jeonietein tht OR incase | ob aemioppirg "gepmterth a Gana a particular adetren ord UE rectiemum sre com by ov ke BM Ub omnoth® . vegrnents Stant — bepoe ris 64 Ryter The main adwomtape ot Gu segmented Meret Scheme, anc as bollact:- ) gtonts ot 4, Allows meray Capactty be 1m by althoys je? vactstot. aolores fo be: harcllad are of I6Hl Size gallows Ue plocing & cde, datr ard seack | pation the Some pregnam encifGerone pests \3. pertmits 0 program amdiox its dota bb be put links digseene area of memey soch time the prarom is executed +| [physical memory orgamisation:- Tn om 086 baseol sypter, the + |Mbs memory iS jicollyy ox gemnized a4 om odd bank and on. epee eT ade Adolres in porousl by the proces? an tren gotinens is bramsipred on Dy =D, 9 ool join bramibied 4 in aPh, Seti. the paste | pesciien FPR Tran oS eg GHE avd p, for selection & cither Eien ©? 001 0°" both the bos: the pccne’ ee Sr tereh bron memory » there one ailperene powibilitias Like | meet ee Teyl mroy be dota operands. | 2. Both the byte rey contain opeade bibs. | be code while the | gore & Ure hiyte my ope ; “otnen may be dota+ |g tre opcode od , eparionds ome idertby by jnternal dlecoolen —ckKE waith futher derives ty rg and oth OS hee inpue to Umi ggrat These contra once: penne mernaxy argon | | 20101, He =0 ] ASS aaa cad cckdvess) | even add tem | [bank abit | | oank se Se ree rreneny Or! ThE Qdlolrey Prorumitled qty pwteg “Ai, tus hase Diveoted bor hanping the dinection eo bu 6 sles Trees, an oddtrey — aevice be row ard shoes “Not Ready” stot te woik tole Tho as ieee pee ty ORE ee Chee gtois dusiyg wait period ‘oe calleol fale stole wooit tote (Ta) cor) inactive tole, The procuiby tug hee Ole for intorral housekeeping The adden token Enable (ALE) sigrak if Emitted Ue proctor Cminmodt) ov the bags dep bietan. 0 mar ond dopencUrg on the pare unig Ine Ae ar ut > soon RE pare ied dealis jngornation Tn moxenodt eats nes duxing 7, by &,s operated on etotus with higher oscar actdbrex bia ord Us be & & & are mulliplurey BHE grab « iT, .te is preens on bus hor only gral foUlowirg dlaka read Cys (7)Adtiren val cusing 7, ww0rile te pata bits BR ws valid dwirg F wroyh wy Generating physical fidolres + “The completo pheyi adoren = whidh is 20 ot borg iS gerwrrtiry: osiry gogrnené ord — efile segittr each 16 B® org. Sor _germmatirg a physical odevew . the conten Oe & kegrrent wegire called segment aclotress js Shiftest by, bbe bit wise foun times omo Oo this sent + Contents os am eth oegirtn , Called — epgick. adores is added bp pradiace a poo bIE phypsicat acotren for Exownple tb bre gegmenb —odbLress 1s joosH Bt Me Is 6555H Gren fegmen& = Adolrew 1005 H- Ord 15.0001 ‘0000 seco cr oF see less 5555.H- gifted by 4 bit por 0021 0000 0000 9104 Gog + 0101 0101 0) oF9) tb i ee a Ss set Physicok adldhress +eS stgral descxiption Of 086 3 a Ral - iguvation of 2086 1 conf Figs pa athe Boge micnoprocenoy js a 16 bit cpo ye clock rats je. 5,8, 1oOmHB- packed WO | 40- pin ceri oF plostic package tha #086 Operon ho. Sing prowuns OF moult procvor configurations b Jachieee hgh pompitrorscel’ fees ci) Beso Piast 4. poortictenr function is prinimue pee Cngle) ord ethen freon in Praximum rode (multi) athe 8086 Signals com be Cotagorired howe group athe fue om. te Sgro common ' fumction inmicinay § meximum mode - the econo ame He Sgrols utich | pour spedot furctions fer min rreda oma he thivo! ggrol. roving special —furetions for wax w we Ue modeol See SRE Ca ce The follociing Signal. dacriptons axe common bor bath| the min/ rox proces” | AD, —ADgi- These are Lime mabti pluxed mrorory odkliey nl statis Gres Caring 7, , these gre we most Signibior addres bines fpr memory operation . Dsting T/o poate these Une, are Lows Doing memay or T, operstion statis Information is awaileabe on tore Lines br hy tg, to od Ty "ThE Sy amd 5, tagethen indticale which segment — xegistey is preently beiry ose for cemeny acces S¢- Heetu 6b Inbnnopt Eroble flag bit: 5 5 aiconat oth or stock 19 tode/nere Bie sq - Gs High Erable /tohu t 11 Dato the = BHE signal. is used to indicate the ariel & data ver (Djs ~Dy) higher orden data bus + Te goes tno for Btn bamibnr Lunia 7, bos wad, unite owe intros aide yO he... Hate slwnation is walle (duing Geb, Ty Te Sgral is action low end is pidtouta curing hold: Te is Low Aig 7, for Ue birt pole db. a intarupe acknouiledlgement cyole: $s rot corrently usdRo ~ Beaat: when la, indicates Oe peripherals that U4 procenos is perborming a memy oF To ioc operation the Ro is active Low amd Showy the Shale for 7, 7, 77 hs Te oh ory ead qytle: Twistated civiirg holt. acknowedge: Reapy: This iS ack from Ce Slow clevice or meroy broreber precenor Reciving dake GEN F pata Enabler Te indicate avatlobility oF youd dato fe throyzh —odelrens [ caka bres oto / ipa i= wren the hold Une goes high it Spica, tm the procuar trot omnether rast is jy te buneces The precuer eee figned on yhe HOLD «weurert Oe hold © acknowledge HUA pin: athe gpllowing pin fumction ose applicable bo ye maximum rede operation. Fb wate Ure inathes ae statiy Line eanich indicaty the type ob operation beirg cowie out:| COCKE G51 Qs. ~ Queue sodust los, | gs.| teaication a es No operation oO ’ ode ‘ S| Fink tain ee "OT pepsequrent byte fron usu. CGromt 1 seq uiere)- RO /o7, , BB IGT, > ded by other local wy martes In mek mode | |Special procewor activitiar + proceor Reset. ard wttiglizatten t- When logic '' is lopped te te Regt pin a the — miceprocendr rs js ment “TE remam in this Sto GU Logic 1iS— agatn applind tm the nest pin. Th termiraly Fam gong progr OM te internal segitans Contents we sek © 0090 exapt cs nicl yatus FFF, Thus th Execution gtani again | prom physiol adidlress FFFFO -Due kp His EP Rom) in am 8086 System 1B interfaced so ax m howe | the. _physicat aoolress memory Locations FFFFO & | FO rnp mg ptt fant a 1 | ».FFEFE sit ie at te Sd ob the : HACT t- when procenor exacts go HLT instructions, it Enters the halt stale Fiowelen — bebpre doing it, tnoicoty thab it is entoing holt stoke in two depending upon whether ie is Ww minimum | cory ¢ or oximun = mode: FE js Bi minimum mode it | jgyuey Ate — pale byk does note. ius ary conbiol nee seolur signal: In maximur rede ig paks + ow on 8,5 s & pint amd then the bus contra, pau om ee put bet re qualibyrg Signe’ ve Ljsued the bacenly ee Inbemupe seqyien’ oF seek will foe re gore Cone ou oh the halk Stale [TEST ama — Synctmorization, with, extemal sigrals:~ when cpu execuutes woot: inibruction: , Ue cpu | woe the TET inpuk 8 bao tb it goes ta for the TET Signal be accepted , ik below — foe atleast 5 Chock cycles: The activity masse consume amy bus Cyclo. e& © wailirg §— decane, || penising Sytr Bas- | a ho 8 rouLbipurc 16 bie odolress/ data | | Bus ~ CAv0- AD) ord peultipumed + bie oaberf | | wefgnir ri fse » HE addlrey com be oy Ale. | >® " wef), ol ou Pp rat @ ‘I q Mito Daze =D tases Dening goes pre tee Sete eet the olennutti pusxirg SESGE pdicea les oboe thowe latch chips ke 74393a 5 ow at anes 5 on $8 ou “ o@ s oa aoe tt ¢ : « o ani 8 « ai tt mt ws facies oo “ ile ececer ) Somiayy sssverdoy weds SUPINE (Stou2yuE) —saOysySME ae) plow aoaoqy sassy geeg ong aumeny yo s9qumy peu Se sey sossasosdos91ur 9808 PIU] Jo WORNIOATSummary OF 80280, 80386, 8o486 AND Pentium Microprocessor80286 microprocessor: Basically this microprocessor is an advanced version of 8086. So before starting with 80286 we must know something about 8086. Intel 8086 is a 16 bit microprocessor intended to be used as a CPU in a microcomputer. The term 16 bit means that its arithmetic logic unit, its internal registers, its instructions are designed to work with 16 bit binary words. It has a 20 bit address bus and 16 bit data bus, So this means that it can address any one of the 1048576 memory locations and it can read data from or write data to the memory and ports either 16 bit or 8 bit at a time. Here the word is stored in two consecutive memory locations. Also one thing to note here is that if the first byte of the word is stored at even address, the 8086 can read the entire word in one operation. Alternatively if the first byte of the word is at odd address, then the 8086 will read the first byte in one operation and the second byte in the second operation. 8088 is. just similar to 8086 but the difference between the two is that 8088 has a8 bit data bus. The Intel 80186 is an improved version of 8086. It is also a 16 bit microprocessor but it has a programmable peripheral devices integrated in the same package. 80186 instruction set has all the instructions of 8086 but also has certain additional instructions. A program written in 8086 will execute properly on 80186 but the vice- versa is not true. With this brief introduction of 8086,8088,80186 let's explain 80286. The Intel 80286 was introduced on February 1, 1982 (also called Intel 286 or iAPX 286) belongs to the family of 8086, is a high performance 16 bit microprocessor. As explained earlier it is an advanced version of 8086 but with a different architectural philosophy. It was widely used in IBM PC compatible computers during the mid 1980s to early 1990s. Its initial releases were of 6 and 8 MHZ but theywere subsequently scaled up to 12.5 MHZ (AMD and Harris later pushed the architecture to speeds as high as 20 and 25 MHz, respectively.) On average, the 80286 had a speed of about 0.21 instructions per clock. The 6 MHZ model operates at 0.9 MIPS, the 10MHZ model at 1.5 MIPS, and the 12 MHZ model at 1.8 MIPS. The 80286's performance was more than twice of its predecessors (the intel 8086 and 8088) per clock cycle. Here the complex mathematical operations took fewer clock cycles compared to the 8086. ion ‘The 80286 eliminates the multiplexing of the buses. It has a linear address bus with 24 address lines that can address 16M bytes of memory directly. It also supports a memory management unit, and through the memory management unit it can address 1G bytes of memory, also known as virutal memory. The processor includes various built in mechanisms that can protect the system software from the user programs, and restrict access to some regions of the memory. The 80286 is specially designed for multiuser and multitasking system. It has four level memory protections and supports for operating system. There are two operating modes for 80286. The real address mode and the protected virtual address mode. As explained in the real address mode the processor can address up to 1MB of the physical memory. The virtual address mode is for multiuser and multitasking system. In this mode of operation the memory management unit can manage upto 1 GB of the virtual memory though the real memory may be much less,only 16 MB. Basically in this mode one user do not interfere with the other. Also users cannot interfere with the operating system. These features are called protection. THE 80286 contains four processing units:1.Bus unit 2.Instruction unit 3,Execution unit 4, Address unit {All memory and 1/0 read /write operations are performed by BU. While the current instruction is being executed, the BU prefetches instructions and keeps them in a queue of six bytes. The function of IU is to decode the perfected instructions and to maintain a queue of 3 decoded instructions for execution. The EU executes instruction. The address unit computes address of memory or 1/0 devices, which is to be sent by BU for read and write operation. All the four units work in parallel within the CPU. This type of parallel operation is called pipelining. All modern 16 bit CPU use pipelining. In pipeli execution units in a processor work simultaneously in parallel. 1g severalods seq <> ‘SaIMERE pur tenuo80386 Microprocessor: The Intel 30386 (also called Intel386) is a microprocessor which has been used as the CPU of many personal computers since 1986. During its design phase the processor was code- named simply “p3”, the third generation processor in the x 86 lines but it is normally referred to as eitheri386 or just 386. The 80386 operated at 5 million instructions per second to 11.4MIPS for the 33MHz model. It was the first x86 processor to have 32 bit architecture, with a basic programming model that has remained virtually unchanged for over 20 years. Successively newer implementations of this same architecture have become literally several hundred times faster than the original 1386 chip during these years. As this is a 32 bit microprocessor it has a circuitry of 275000 transistors, It was basically introduced in the year 1985. It is compatible with 8086, 8088, 80186, 80286 microprocessors. It also contains a four- level protection mechanism on the chip itself. It has a total of 129 instructions. The 80386 is a 32 bit microprocessor with a nonmultiplexed 32 bit address bus housed in a 132 pin grid array package. Basically this microprocessor has three versions: 803865X,SL and DX. The DX version has a 32 bit internal architecture and a 32 bit data bus whereas the SX and the SL version have a 32 bit internal architecture but a 16 bit wide data bus. The SL version consumes less power and is basically used in laptops and notebooks. These versions operate from 20MHz to 33MHz. It is capable of addressing 4G bytes of physical memory and through its memory management unit it can address 64 terabytes of the virtual memory. The processor can operate in two modes: Real and protected. In the real mode physical addressspace is 1Mbytes (20 address lines), which is extended to 4G bytes in the protected mode (32 address lines). The primary difference between these modes is the availability of the memory space and the addressing scheme. The 80386 has 32 bit registers and is upward software compatible with the 8086. The execution of the instructions is highly pipelined and the processor is designed to operate in a multiuser and multitasking environment. It has the protection mechanism for this type of environment. It has basically six functional units: bus interface unit, code prefetch unit, instruction decode unit, execution unit, segmentation unit and the paging unit. It has the provision for both memory segmentation and paging. A page is of fixed size 4KB each. Segment vary in size, 4GB is the maximum size of a segment. The 80386 has 11 addressing modes: register, immediate, direct, register indirect, based, indexed, scale indexed, base indexed, base scale indexed, base indexed with displacement and base scale indexed with displacement addressing. In the scale indexed addressing the contents of an indexed register are multiplied with a scaling factor and the result is added to the displacement to obtain the operand’s offset. As explained earlier it has 32 bit register and has eight general purpose registers, six 16 bit segment registers, also has a 32 bit instruction pointer, six debug registers and a 32 bit status register. The 80386 has a segment descriptor register associated with each segment register. The 80386 was widely used in powerful PCs before the 80486 was developed.oat snq ewer -- we aossazodoaoquu 9gp08 Jo WesBEIP DOI80486 Microprocessor: Basically this is an upgraded advanced version of 80386 and it was released in the year 1989. It contains a 32 bit CPU, a floating-point math coprocessor, unified instruction and data cache memory and memory management unit in a single IC. It contains an electronic circuitry of 1.2 million transistors. Its operating frequency for its different versions is 25, 33, 66 and 100MHz. It is 3 to 5 times faster than-80386. Basically this is available in two versions: DX and SX. The DX type version is a 32 bit processor housed in a 168 pin grid array package and can operate with the clock frequencies from 25 to 66 MHz as explained earlier. The important additional features of the 486 processor in comparison with the 386 processor are as follows. The 486 processor includes: ® Built in math coprocessor. In the 386 system, a math coprocessor is an external device. Therefore, the math instructions in 486 systems are executed three times faster than in 386 systems. © 8K byte of code and data cache memory on the chip. © Highly pipelined execution unit. Therefore the execution time for many instructions is one clock period. Basically we do not use 80486 but instead of that we use i486 because of a court ruling that prohibited trademarking numbers. Intel dropped number-based naming altogether with the successor to the i486-the Pentium processor. The 486 contains the following functional units: © Execution unit * Control unit © Bus interface unit * Code prefetch unit * Instruction decode unit‘* Segmentation unit © Paging unit © Cache unit © Floating point unit. The code prefetch unit contains a 32 byte queue to store fetched instruetion codes, The control unit also contains a control ROM to store microcodes. The segmentation unit calculates linear address (the starting address of the segment plus the offset) from the logical address. The address given in the program is called the logical address. It also provides 4-level of protection for isolating and protecting tasks and the operating system from each other. The paging unit provides the paging faci the physical address. The actual capacity of RAM and ROM existing in a computer is known as physical memory. The segmentation and the paging unit constitute memory management unit. ry within a segment. It translates the linear address into In summary, the 486 is a high speed, high performance 32 bit microprocessor. It executes many of its instructions in one clock cycle by using highly pipelined execution units. It is designed to facilitate the execution of high level languages and suited for multiprocessing and multitasking systems. In the early 1990s, 486 was generally used in high end microcomputers and network environments.